X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=73ff3ba4ef4327a5bf697c9ac60d5f801dbdede8;hb=87fea9e1e34fcdd7b43ab60cb03b08c716f69571;hp=ac032608ef214357c7ed036c360ba60a86709c05;hpb=5f6a016fa6cdd59a0190591de58efd721511f1af;p=libfirm

diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c
index ac032608e..73ff3ba4e 100644
--- a/ir/be/ia32/ia32_optimize.c
+++ b/ir/be/ia32/ia32_optimize.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
  *
  * This file is part of libFirm.
  *
@@ -61,8 +61,6 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
 static const arch_env_t *arch_env;
 static ia32_code_gen_t  *cg;
 
-static void peephole_IncSP_IncSP(ir_node *node);
-
 #if 0
 static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
 {
@@ -95,7 +93,7 @@ static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
 	if(!be_is_IncSP(incsp))
 		return;
 
-	peephole_IncSP_IncSP(incsp);
+	be_peephole_IncSP_IncSP(incsp);
 
 	/* must be in the same block */
 	if(get_nodes_block(incsp) != get_nodes_block(node))
@@ -119,7 +117,7 @@ static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
 	noreg = ia32_new_NoReg_gp(cg);
 	base  = be_get_IncSP_pred(incsp);
 	val   = get_irn_n(node, n_ia32_Store_val);
-	push  = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, base, val);
+	push  = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, val, base);
 
 	proj  = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
 
@@ -254,6 +252,10 @@ static void peephole_ia32_Test(ir_node *node)
 		left = get_Proj_pred(left);
 	}
 
+	/* happens rarely, but if it does code will panic' */
+	if (is_ia32_Unknown_GP(left))
+		return;
+
 	/* walk schedule up and abort when we find left or some other node destroys
 	   the flags */
 	schedpoint = sched_prev(node);
@@ -293,11 +295,74 @@ static void peephole_ia32_Test(ir_node *node)
 	be_peephole_after_exchange(flags_proj);
 }
 
-// only optimize up to 48 stores behind IncSPs
+/**
+ * AMD Athlon works faster when RET is not destination of
+ * conditional jump or directly preceded by other jump instruction.
+ * Can be avoided by placing a Rep prefix before the return.
+ */
+static void peephole_ia32_Return(ir_node *node) {
+	ir_node *block, *irn;
+
+	if (!ia32_cg_config.use_pad_return)
+		return;
+
+	block = get_nodes_block(node);
+
+	if (get_Block_n_cfgpreds(block) == 1) {
+		ir_node *pred = get_Block_cfgpred(block, 0);
+
+		if (is_Jmp(pred)) {
+			/* The block of the return has only one predecessor,
+			   which jumps directly to this block.
+			   This jump will be encoded as a fall through, so we
+			   ignore it here.
+			   However, the predecessor might be empty, so it must be
+			   ensured that empty blocks are gone away ... */
+			return;
+		}
+	}
+
+	/* check if this return is the first on the block */
+	sched_foreach_reverse_from(node, irn) {
+		switch (get_irn_opcode(irn)) {
+		case beo_Return:
+			/* the return node itself, ignore */
+			continue;
+		case beo_Barrier:
+			/* ignore the barrier, no code generated */
+			continue;
+		case beo_IncSP:
+			/* arg, IncSP 0 nodes might occur, ignore these */
+			if (be_get_IncSP_offset(irn) == 0)
+				continue;
+			return;
+		case iro_Phi:
+			continue;
+		default:
+			return;
+		}
+	}
+	/* yep, return is the first real instruction in this block */
+#if 0
+	{
+		/* add an rep prefix to the return */
+		ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block);
+		keep_alive(rep);
+		sched_add_before(node, rep);
+	}
+#else
+	/* ensure, that the 3 byte return is generated */
+	be_Return_set_emit_pop(node, 1);
+#endif
+}
+
+/* only optimize up to 48 stores behind IncSPs */
 #define MAXPUSH_OPTIMIZE	48
 
 /**
- * Tries to create pushs from IncSP,Store combinations
+ * Tries to create pushs from IncSP,Store combinations.
+ * The Stores are replaced by Push's, the IncSP is modified
+ * (possibly into IncSP 0, but not removed).
  */
 static void peephole_IncSP_Store_to_push(ir_node *irn)
 {
@@ -315,7 +380,7 @@ static void peephole_IncSP_Store_to_push(ir_node *irn)
 	assert(be_is_IncSP(irn));
 
 	offset = be_get_IncSP_offset(irn);
-	if(offset < 4)
+	if (offset < 4)
 		return;
 
 	/*
@@ -386,7 +451,7 @@ static void peephole_IncSP_Store_to_push(ir_node *irn)
 		mem = get_irn_n(store, n_ia32_mem);
 		spreg = arch_get_irn_register(cg->arch_env, curr_sp);
 
-		push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, curr_sp, val);
+		push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
 
 		sched_add_before(irn, push);
 
@@ -411,127 +476,152 @@ static void peephole_IncSP_Store_to_push(ir_node *irn)
 }
 
 /**
- * Tries to optimize two following IncSP.
+ * Find a free GP register if possible, else return NULL.
  */
-static void peephole_IncSP_IncSP(ir_node *node)
+static const arch_register_t *get_free_gp_reg(void)
 {
-	int      pred_offs;
-	int      curr_offs;
-	int      offs;
-	ir_node *pred = be_get_IncSP_pred(node);
-	ir_node *predpred;
+	int i;
 
-	if(!be_is_IncSP(pred))
-		return;
+	for(i = 0; i < N_ia32_gp_REGS; ++i) {
+		const arch_register_t *reg = &ia32_gp_regs[i];
+		if(arch_register_type_is(reg, ignore))
+			continue;
 
-	if(get_irn_n_edges(pred) > 1)
-		return;
+		if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
+			return &ia32_gp_regs[i];
+	}
 
-	pred_offs = be_get_IncSP_offset(pred);
-	curr_offs = be_get_IncSP_offset(node);
+	return NULL;
+}
 
-	if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
-		if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
-			return;
-		}
-		offs = 0;
-	} else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
-		if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
-			return;
-		}
-		offs = 0;
-	} else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
-			|| curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
-		return;
-	} else {
-		offs = curr_offs + pred_offs;
-	}
+/**
+ * Creates a Pop instruction before the given schedule point.
+ *
+ * @param dbgi        debug info
+ * @param irg         the graph
+ * @param block       the block
+ * @param stack       the previous stack value
+ * @param schedpoint  the new node is added before this node
+ * @param reg         the register to pop
+ *
+ * @return the new stack value
+ */
+static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
+                           ir_node *stack, ir_node *schedpoint,
+                           const arch_register_t *reg)
+{
+	const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+	ir_node *pop;
+	ir_node *keep;
+	ir_node *val;
+	ir_node *in[1];
 
-	/* add pred offset to ours and remove pred IncSP */
-	be_set_IncSP_offset(node, offs);
+	pop   = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
 
-	predpred = be_get_IncSP_pred(pred);
-	be_peephole_before_exchange(pred, predpred);
+	stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
+	arch_set_irn_register(arch_env, stack, esp);
+	val   = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
+	arch_set_irn_register(arch_env, val, reg);
+
+	sched_add_before(schedpoint, pop);
 
-	/* rewire dependency edges */
-	edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
-	be_set_IncSP_pred(node, predpred);
-	sched_remove(pred);
-	be_kill_node(pred);
+	in[0] = val;
+	keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+	sched_add_before(schedpoint, keep);
 
-	be_peephole_after_exchange(predpred);
+	return stack;
 }
 
-static const arch_register_t *get_free_gp_reg(void)
+/**
+ * Creates a Push instruction before the given schedule point.
+ *
+ * @param dbgi        debug info
+ * @param irg         the graph
+ * @param block       the block
+ * @param stack       the previous stack value
+ * @param schedpoint  the new node is added before this node
+ * @param reg         the register to pop
+ *
+ * @return the new stack value
+ */
+static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
+                            ir_node *stack, ir_node *schedpoint,
+                            const arch_register_t *reg)
 {
-	int i;
+	const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
+	ir_node *noreg, *nomem, *push, *val;
 
-	for(i = 0; i < N_ia32_gp_REGS; ++i) {
-		const arch_register_t *reg = &ia32_gp_regs[i];
-		if(arch_register_type_is(reg, ignore))
-			continue;
+	val  = new_rd_ia32_ProduceVal(NULL, irg, block);
+	arch_set_irn_register(arch_env, val, reg);
+	sched_add_before(schedpoint, val);
 
-		if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
-			return &ia32_gp_regs[i];
-	}
+	noreg = ia32_new_NoReg_gp(cg);
+	nomem = get_irg_no_mem(irg);
+	push  = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
+	sched_add_before(schedpoint, push);
 
-	return NULL;
+	stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
+	arch_set_irn_register(arch_env, stack, esp);
+
+	return stack;
 }
 
+/**
+ * Optimize an IncSp by replacing it with push/pop
+ */
 static void peephole_be_IncSP(ir_node *node)
 {
 	const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
 	const arch_register_t *reg;
-	ir_graph              *irg;
+	ir_graph              *irg = current_ir_graph;
 	dbg_info              *dbgi;
 	ir_node               *block;
-	ir_node               *keep;
-	ir_node               *val;
-	ir_node               *pop;
-	ir_node               *noreg;
 	ir_node               *stack;
 	int                    offset;
 
 	/* first optimize incsp->incsp combinations */
-	peephole_IncSP_IncSP(node);
+	be_peephole_IncSP_IncSP(node);
 
 	/* transform IncSP->Store combinations to Push where possible */
 	peephole_IncSP_Store_to_push(node);
 
+	if (arch_get_irn_register(arch_env, node) != esp)
+		return;
+
 	/* replace IncSP -4 by Pop freereg when possible */
 	offset = be_get_IncSP_offset(node);
-	if(offset != -4)
+	if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
+	    (offset != -4 || ia32_cg_config.use_add_esp_4) &&
+	    (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
+	    (offset != +8 || ia32_cg_config.use_sub_esp_8))
 		return;
 
-	if(arch_get_irn_register(arch_env, node) != esp)
-		return;
+	if (offset < 0) {
+		/* we need a free register for pop */
+		reg = get_free_gp_reg();
+		if (reg == NULL)
+			return;
 
-	reg = get_free_gp_reg();
-	if(reg == NULL)
-		return;
+		dbgi  = get_irn_dbg_info(node);
+		block = get_nodes_block(node);
+		stack = be_get_IncSP_pred(node);
 
-	irg   = current_ir_graph;
-	dbgi  = get_irn_dbg_info(node);
-	block = get_nodes_block(node);
-	noreg = ia32_new_NoReg_gp(cg);
-	stack = be_get_IncSP_pred(node);
-	pop   = new_rd_ia32_Pop(dbgi, irg, block, noreg, noreg, new_NoMem(), stack);
+		stack = create_pop(dbgi, irg, block, stack, node, reg);
 
-	stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
-	arch_set_irn_register(arch_env, stack, esp);
-	val   = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
-	arch_set_irn_register(arch_env, val, reg);
+		if (offset == -8) {
+			stack = create_pop(dbgi, irg, block, stack, node, reg);
+		}
+	} else {
+		dbgi  = get_irn_dbg_info(node);
+		block = get_nodes_block(node);
+		stack = be_get_IncSP_pred(node);
+		reg   = &ia32_gp_regs[REG_EAX];
 
-	sched_add_before(node, pop);
+		stack = create_push(dbgi, irg, block, stack, node, reg);
 
-	keep  = sched_next(node);
-	if(!be_is_Keep(keep)) {
-		ir_node *in[1];
-		in[0] = val;
-		keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
-		sched_add_before(node, keep);
-	} else {
-		be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
+		if (offset == +8) {
+			stack = create_push(dbgi, irg, block, stack, node, reg);
+		}
 	}
 
 	be_peephole_before_exchange(node, stack);
@@ -555,10 +645,12 @@ static void peephole_ia32_Const(ir_node *node)
 	ir_node                     *noreg;
 
 	/* try to transform a mov 0, reg to xor reg reg */
-	if(attr->offset != 0 || attr->symconst != NULL)
+	if (attr->offset != 0 || attr->symconst != NULL)
+		return;
+	if (ia32_cg_config.use_mov_0)
 		return;
 	/* xor destroys the flags, so no-one must be using them */
-	if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
+	if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
 		return;
 
 	reg = arch_get_irn_register(arch_env, node);
@@ -793,12 +885,75 @@ exchange:
 	be_peephole_after_exchange(res);
 }
 
+/**
+ * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
+ */
+static void peephole_ia32_Imul_split(ir_node *imul) {
+	const ir_node         *right = get_irn_n(imul, n_ia32_IMul_right);
+	const arch_register_t *reg;
+	ir_node               *load, *block, *base, *index, *mem, *res, *noreg;
+	dbg_info              *dbgi;
+	ir_graph              *irg;
+
+	if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
+		/* no memory, imm form ignore */
+		return;
+	}
+	/* we need a free register */
+	reg = get_free_gp_reg();
+	if (reg == NULL)
+		return;
+
+	/* fine, we can rebuild it */
+	dbgi  = get_irn_dbg_info(imul);
+	block = get_nodes_block(imul);
+	irg   = current_ir_graph;
+	base  = get_irn_n(imul, n_ia32_IMul_base);
+	index = get_irn_n(imul, n_ia32_IMul_index);
+	mem   = get_irn_n(imul, n_ia32_IMul_mem);
+	load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+
+	/* copy all attributes */
+	set_irn_pinned(load, get_irn_pinned(imul));
+	set_ia32_op_type(load, ia32_AddrModeS);
+	set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
+
+	set_ia32_am_scale(load, get_ia32_am_scale(imul));
+	set_ia32_am_sc(load, get_ia32_am_sc(imul));
+	set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
+	if (is_ia32_am_sc_sign(imul))
+		set_ia32_am_sc_sign(load);
+	if (is_ia32_use_frame(imul))
+		set_ia32_use_frame(load);
+	set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
+
+	sched_add_before(imul, load);
+
+	mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
+	res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
+
+	arch_set_irn_register(arch_env, res, reg);
+	be_peephole_after_exchange(res);
+
+	set_irn_n(imul, n_ia32_IMul_mem, mem);
+	noreg = get_irn_n(imul, n_ia32_IMul_left);
+	set_irn_n(imul, n_ia32_IMul_left, res);
+	set_ia32_op_type(imul, ia32_Normal);
+}
+
+/**
+ * Replace xorps r,r and xorpd r,r by pxor r,r
+ */
+static void peephole_ia32_xZero(ir_node *xor) {
+	set_irn_op(xor, op_ia32_xPzero);
+}
+
 /**
  * Register a peephole optimisation function.
  */
 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
 	assert(op->ops.generic == NULL);
-	op->ops.generic = (void*) func;
+	op->ops.generic = (op_func)func;
 }
 
 /* Perform peephole-optimizations. */
@@ -815,6 +970,11 @@ void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
 	register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
 	register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
 	register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
+	register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
+	if (! ia32_cg_config.use_imul_mem_imm32)
+		register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
+	if (ia32_cg_config.use_pxor)
+		register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
 
 	be_peephole_opt(cg->birg);
 }