X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=719c158d55511d645f7644079497e753d175d02a;hb=7ee810bbb58eb8d1b0eb82fec1fcc836d3d05004;hp=b9c1c732b6f4d83de05aaf5e5016cb74ceba0f6c;hpb=deb677e11e06072b06af6e259402917b8bad3a35;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index b9c1c732b..719c158d5 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -51,6 +51,7 @@ #include "ia32_optimize.h" #include "bearch_ia32_t.h" #include "gen_ia32_regalloc_if.h" +#include "ia32_common_transform.h" #include "ia32_transform.h" #include "ia32_dbg_stat.h" #include "ia32_util.h" @@ -61,96 +62,37 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) static const arch_env_t *arch_env; static ia32_code_gen_t *cg; -#if 0 -static void peephole_ia32_Store_IncSP_to_push(ir_node *node) +static void copy_mark(const ir_node *old, ir_node *new) { - ir_node *base = get_irn_n(node, n_ia32_Store_base); - ir_node *index = get_irn_n(node, n_ia32_Store_index); - ir_node *mem = get_irn_n(node, n_ia32_Store_mem); - ir_node *incsp = base; - ir_node *val; - ir_node *noreg; - ir_graph *irg; - ir_node *block; - dbg_info *dbgi; - ir_mode *mode; - ir_node *push; - ir_node *proj; - int offset; - int node_offset; - - /* nomem inidicates the store doesn't alias with anything else */ - if(!is_NoMem(mem)) - return; - - /* find an IncSP in front of us, we might have to skip barriers for this */ - while(is_Proj(incsp)) { - ir_node *proj_pred = get_Proj_pred(incsp); - if(!be_is_Barrier(proj_pred)) - return; - incsp = get_irn_n(proj_pred, get_Proj_proj(incsp)); - } - if(!be_is_IncSP(incsp)) - return; - - be_peephole_IncSP_IncSP(incsp); - - /* must be in the same block */ - if(get_nodes_block(incsp) != get_nodes_block(node)) - return; - - if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) { - panic("Invalid storeAM found (%+F)", node); - } - - /* we should be the store to the end of the stackspace */ - offset = be_get_IncSP_offset(incsp); - mode = get_ia32_ls_mode(node); - node_offset = get_ia32_am_offs_int(node); - if(node_offset != offset - get_mode_size_bytes(mode)) - return; - - /* we can use a push instead of the store */ - irg = current_ir_graph; - block = get_nodes_block(node); - dbgi = get_irn_dbg_info(node); - noreg = ia32_new_NoReg_gp(cg); - base = be_get_IncSP_pred(incsp); - val = get_irn_n(node, n_ia32_Store_val); - push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, val, base); - - proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); - - be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode)); - - sched_add_before(node, push); - sched_remove(node); - - be_peephole_before_exchange(node, proj); - exchange(node, proj); - be_peephole_after_exchange(proj); + if (is_ia32_is_reload(old)) + set_ia32_is_reload(new); + if (is_ia32_is_spill(old)) + set_ia32_is_spill(new); + if (is_ia32_is_remat(old)) + set_ia32_is_remat(new); } -static void peephole_ia32_Store(ir_node *node) -{ - peephole_ia32_Store_IncSP_to_push(node); -} -#endif - +/** + * Returns non-zero if the given node produces + * a zero flag. + * + * @param node the node to check + * @param pn if >= 0, the projection number of the used result + */ static int produces_zero_flag(ir_node *node, int pn) { ir_node *count; const ia32_immediate_attr_t *imm_attr; - if(!is_ia32_irn(node)) + if (!is_ia32_irn(node)) return 0; - if(pn >= 0) { - if(pn != pn_ia32_res) + if (pn >= 0) { + if (pn != pn_ia32_res) return 0; } - switch(get_ia32_irn_opcode(node)) { + switch (get_ia32_irn_opcode(node)) { case iro_ia32_Add: case iro_ia32_Adc: case iro_ia32_And: @@ -165,26 +107,26 @@ static int produces_zero_flag(ir_node *node, int pn) case iro_ia32_ShlD: case iro_ia32_ShrD: + assert(n_ia32_ShlD_count == n_ia32_ShrD_count); + count = get_irn_n(node, n_ia32_ShlD_count); + goto check_shift_amount; + case iro_ia32_Shl: case iro_ia32_Shr: case iro_ia32_Sar: - assert(n_ia32_ShlD_count == n_ia32_ShrD_count); assert(n_ia32_Shl_count == n_ia32_Shr_count && n_ia32_Shl_count == n_ia32_Sar_count); - if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) { - count = get_irn_n(node, n_ia32_ShlD_count); - } else { - count = get_irn_n(node, n_ia32_Shl_count); - } + count = get_irn_n(node, n_ia32_Shl_count); +check_shift_amount: /* when shift count is zero the flags are not affected, so we can only * do this for constants != 0 */ - if(!is_ia32_Immediate(count)) + if (!is_ia32_Immediate(count)) return 0; imm_attr = get_ia32_immediate_attr_const(count); - if(imm_attr->symconst != NULL) + if (imm_attr->symconst != NULL) return 0; - if((imm_attr->offset & 0x1f) == 0) + if ((imm_attr->offset & 0x1f) == 0) return 0; return 1; @@ -194,6 +136,13 @@ static int produces_zero_flag(ir_node *node, int pn) return 0; } +/** + * If the given node has not mode_T, creates a mode_T version (with a result Proj). + * + * @param node the node to change + * + * @return the new mode_T node (if the mode was changed) or node itself + */ static ir_node *turn_into_mode_t(ir_node *node) { ir_node *block; @@ -216,25 +165,92 @@ static ir_node *turn_into_mode_t(ir_node *node) reg = arch_get_irn_register(arch_env, node); arch_set_irn_register(arch_env, res_proj, reg); - be_peephole_before_exchange(node, res_proj); sched_add_before(node, new_node); - sched_remove(node); - exchange(node, res_proj); - be_peephole_after_exchange(res_proj); - + be_peephole_exchange(node, res_proj); return new_node; } +/** + * Replace Cmp(x, 0) by a Test(x, x) + */ +static void peephole_ia32_Cmp(ir_node *const node) +{ + ir_node *right; + ia32_immediate_attr_t const *imm; + dbg_info *dbgi; + ir_graph *irg; + ir_node *block; + ir_node *noreg; + ir_node *nomem; + ir_node *op; + ia32_attr_t const *attr; + int ins_permuted; + int cmp_unsigned; + ir_node *test; + arch_register_t const *reg; + ir_edge_t const *edge; + ir_edge_t const *tmp; + + if (get_ia32_op_type(node) != ia32_Normal) + return; + + right = get_irn_n(node, n_ia32_Cmp_right); + if (!is_ia32_Immediate(right)) + return; + + imm = get_ia32_immediate_attr_const(right); + if (imm->symconst != NULL || imm->offset != 0) + return; + + dbgi = get_irn_dbg_info(node); + irg = current_ir_graph; + block = get_nodes_block(node); + noreg = ia32_new_NoReg_gp(cg); + nomem = get_irg_no_mem(irg); + op = get_irn_n(node, n_ia32_Cmp_left); + attr = get_irn_generic_attr(node); + ins_permuted = attr->data.ins_permuted; + cmp_unsigned = attr->data.cmp_unsigned; + + if (is_ia32_Cmp(node)) { + test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem, + op, op, ins_permuted, cmp_unsigned); + } else { + test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem, + op, op, ins_permuted, cmp_unsigned); + } + set_ia32_ls_mode(test, get_ia32_ls_mode(node)); + + reg = arch_get_irn_register(arch_env, node); + arch_set_irn_register(arch_env, test, reg); + + foreach_out_edge_safe(node, edge, tmp) { + ir_node *const user = get_edge_src_irn(edge); + + if (is_Proj(user)) + exchange(user, test); + } + + sched_add_before(node, test); + copy_mark(node, test); + be_peephole_exchange(node, test); +} + +/** + * Peephole optimization for Test instructions. + * We can remove the Test, if a zero flags was produced which is still + * live. + */ static void peephole_ia32_Test(ir_node *node) { - ir_node *left = get_irn_n(node, n_ia32_Test_left); - ir_node *right = get_irn_n(node, n_ia32_Test_right); - ir_node *flags_proj; - ir_node *block; - ir_mode *flags_mode; - int pn = -1; - ir_node *schedpoint; - const ir_edge_t *edge; + ir_node *left = get_irn_n(node, n_ia32_Test_left); + ir_node *right = get_irn_n(node, n_ia32_Test_right); + ir_node *flags_proj; + ir_node *block; + ir_mode *flags_mode; + int pn = -1; + ir_node *schedpoint; + const ir_edge_t *edge; assert(n_ia32_Test_left == n_ia32_Test8Bit_left && n_ia32_Test_right == n_ia32_Test8Bit_right); @@ -289,10 +305,7 @@ static void peephole_ia32_Test(ir_node *node) assert(get_irn_mode(node) != mode_T); - be_peephole_before_exchange(node, flags_proj); - exchange(node, flags_proj); - sched_remove(node); - be_peephole_after_exchange(flags_proj); + be_peephole_exchange(node, flags_proj); } /** @@ -308,20 +321,6 @@ static void peephole_ia32_Return(ir_node *node) { block = get_nodes_block(node); - if (get_Block_n_cfgpreds(block) == 1) { - ir_node *pred = get_Block_cfgpred(block, 0); - - if (is_Jmp(pred)) { - /* The block of the return has only one predecessor, - which jumps directly to this block. - This jump will be encoded as a fall through, so we - ignore it here. - However, the predecessor might be empty, so it must be - ensured that empty blocks are gone away ... */ - return; - } - } - /* check if this return is the first on the block */ sched_foreach_reverse_from(node, irn) { switch (get_irn_opcode(irn)) { @@ -342,37 +341,33 @@ static void peephole_ia32_Return(ir_node *node) { return; } } - /* yep, return is the first real instruction in this block */ -#if 0 - { - /* add an rep prefix to the return */ - ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block); - keep_alive(rep); - sched_add_before(node, rep); - } -#else + /* ensure, that the 3 byte return is generated */ be_Return_set_emit_pop(node, 1); -#endif } /* only optimize up to 48 stores behind IncSPs */ #define MAXPUSH_OPTIMIZE 48 /** - * Tries to create pushs from IncSP,Store combinations. + * Tries to create Push's from IncSP, Store combinations. * The Stores are replaced by Push's, the IncSP is modified * (possibly into IncSP 0, but not removed). */ static void peephole_IncSP_Store_to_push(ir_node *irn) { - int i, maxslot, inc_ofs; - ir_node *node; - ir_node *stores[MAXPUSH_OPTIMIZE]; - ir_node *block = get_nodes_block(irn); - ir_graph *irg = cg->irg; - ir_node *curr_sp; - ir_mode *spmode = get_irn_mode(irn); + int i; + int maxslot; + int inc_ofs; + ir_node *node; + ir_node *stores[MAXPUSH_OPTIMIZE]; + ir_node *block; + ir_graph *irg; + ir_node *curr_sp; + ir_mode *spmode; + ir_node *first_push = NULL; + ir_edge_t const *edge; + ir_edge_t const *next; memset(stores, 0, sizeof(stores)); @@ -384,7 +379,7 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) /* * We first walk the schedule after the IncSP node as long as we find - * suitable stores that could be transformed to a push. + * suitable Stores that could be transformed to a Push. * We save them into the stores array which is sorted by the frame offset/4 * attached to the node */ @@ -408,20 +403,18 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) /* unfortunately we can't support the full AMs possible for push at the * moment. TODO: fix this */ - if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index))) + if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index))) break; offset = get_ia32_am_offs_int(node); /* we should NEVER access uninitialized stack BELOW the current SP */ assert(offset >= 0); - offset = inc_ofs - 4 - offset; - /* storing at half-slots is bad */ if ((offset & 3) != 0) break; - if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4) + if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4) continue; storeslot = offset >> 2; @@ -434,26 +427,35 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) maxslot = storeslot; } - curr_sp = be_get_IncSP_pred(irn); + curr_sp = irn; + + for (i = -1; i < maxslot; ++i) { + if (stores[i + 1] == NULL) + break; + } - /* walk through the stores and create Pushs for them */ - for (i = 0; i <= maxslot; ++i) { + /* walk through the Stores and create Pushs for them */ + block = get_nodes_block(irn); + spmode = get_irn_mode(irn); + irg = cg->irg; + for (; i >= 0; --i) { const arch_register_t *spreg; ir_node *push; ir_node *val, *mem, *mem_proj; ir_node *store = stores[i]; ir_node *noreg = ia32_new_NoReg_gp(cg); - if (store == NULL) - break; - val = get_irn_n(store, n_ia32_unary_op); mem = get_irn_n(store, n_ia32_mem); spreg = arch_get_irn_register(cg->arch_env, curr_sp); push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp); + copy_mark(store, push); + + if (first_push == NULL) + first_push = push; - sched_add_before(irn, push); + sched_add_after(curr_sp, push); /* create stackpointer Proj */ curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack); @@ -463,18 +465,284 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); /* use the memproj now */ - exchange(store, mem_proj); - - /* we can remove the store now */ - sched_remove(store); + be_peephole_exchange(store, mem_proj); inc_ofs -= 4; } + foreach_out_edge_safe(irn, edge, next) { + ir_node *const src = get_edge_src_irn(edge); + int const pos = get_edge_src_pos(edge); + + if (src == first_push) + continue; + + set_irn_n(src, pos, curr_sp); + } + be_set_IncSP_offset(irn, inc_ofs); - be_set_IncSP_pred(irn, curr_sp); } +#if 0 +static void peephole_store_incsp(ir_node *store) +{ + dbg_info *dbgi; + ir_node *node; + ir_node *block; + ir_node *noref; + ir_node *mem; + ir_node *push; + ir_node *val; + ir_node *am_base = get_irn_n(store, n_ia32_Store_base); + if (!be_is_IncSP(am_base) + || get_nodes_block(am_base) != get_nodes_block(store)) + return; + mem = get_irn_n(store, n_ia32_Store_mem); + if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index)) + || !is_NoMem(mem)) + return; + + int incsp_offset = be_get_IncSP_offset(am_base); + if (incsp_offset <= 0) + return; + + /* we have to be at offset 0 */ + int my_offset = get_ia32_am_offs_int(store); + if (my_offset != 0) { + /* TODO here: find out wether there is a store with offset 0 before + * us and wether we can move it down to our place */ + return; + } + ir_mode *ls_mode = get_ia32_ls_mode(store); + int my_store_size = get_mode_size_bytes(ls_mode); + + if (my_offset + my_store_size > incsp_offset) + return; + + /* correctness checking: + - noone else must write to that stackslot + (because after translation incsp won't allocate it anymore) + */ + sched_foreach_reverse_from(store, node) { + int i, arity; + + if (node == am_base) + break; + + /* make sure noone else can use the space on the stack */ + arity = get_irn_arity(node); + for (i = 0; i < arity; ++i) { + ir_node *pred = get_irn_n(node, i); + if (pred != am_base) + continue; + + if (i == n_ia32_base && + (get_ia32_op_type(node) == ia32_AddrModeS + || get_ia32_op_type(node) == ia32_AddrModeD)) { + int node_offset = get_ia32_am_offs_int(node); + ir_mode *node_ls_mode = get_ia32_ls_mode(node); + int node_size = get_mode_size_bytes(node); + /* overlapping with our position? abort */ + if (node_offset < my_offset + my_store_size + && node_offset + node_size >= my_offset) + return; + /* otherwise it's fine */ + continue; + } + + /* strange use of esp: abort */ + return; + } + } + + /* all ok, change to push */ + dbgi = get_irn_dbg_info(store); + block = get_nodes_block(store); + noreg = ia32_new_NoReg_gp(cg); + val = get_ia32_ + + push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, + + create_push(dbgi, current_ir_graph, block, am_base, store); +} +#endif + +/** + * Return true if a mode can be stored in the GP register set + */ +static INLINE int mode_needs_gp_reg(ir_mode *mode) { + if (mode == mode_fpcw) + return 0; + if (get_mode_size_bits(mode) > 32) + return 0; + return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b; +} + +/** + * Tries to create Pops from Load, IncSP combinations. + * The Loads are replaced by Pops, the IncSP is modified + * (possibly into IncSP 0, but not removed). + */ +static void peephole_Load_IncSP_to_pop(ir_node *irn) +{ + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + int i, maxslot, inc_ofs, ofs; + ir_node *node, *pred_sp, *block; + ir_node *loads[MAXPUSH_OPTIMIZE]; + ir_graph *irg; + unsigned regmask = 0; + unsigned copymask = ~0; + + memset(loads, 0, sizeof(loads)); + assert(be_is_IncSP(irn)); + + inc_ofs = -be_get_IncSP_offset(irn); + if (inc_ofs < 4) + return; + + /* + * We first walk the schedule before the IncSP node as long as we find + * suitable Loads that could be transformed to a Pop. + * We save them into the stores array which is sorted by the frame offset/4 + * attached to the node + */ + maxslot = -1; + pred_sp = be_get_IncSP_pred(irn); + for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) { + int offset; + int loadslot; + const arch_register_t *sreg, *dreg; + + /* it has to be a Load */ + if (!is_ia32_Load(node)) { + if (be_is_Copy(node)) { + if (!mode_needs_gp_reg(get_irn_mode(node))) { + /* not a GP copy, ignore */ + continue; + } + dreg = arch_get_irn_register(arch_env, node); + sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node)); + if (regmask & copymask & (1 << sreg->index)) { + break; + } + if (regmask & copymask & (1 << dreg->index)) { + break; + } + /* we CAN skip Copies if neither the destination nor the source + * is not in our regmask, ie none of our future Pop will overwrite it */ + regmask |= (1 << dreg->index) | (1 << sreg->index); + copymask &= ~((1 << dreg->index) | (1 << sreg->index)); + continue; + } + break; + } + + /* we can handle only GP loads */ + if (!mode_needs_gp_reg(get_ia32_ls_mode(node))) + continue; + + /* it has to use our predecessor sp value */ + if (get_irn_n(node, n_ia32_base) != pred_sp) { + /* it would be ok if this load does not use a Pop result, + * but we do not check this */ + break; + } + + /* should have NO index */ + if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index))) + break; + + offset = get_ia32_am_offs_int(node); + /* we should NEVER access uninitialized stack BELOW the current SP */ + assert(offset >= 0); + + /* storing at half-slots is bad */ + if ((offset & 3) != 0) + break; + + if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4) + continue; + /* ignore those outside the possible windows */ + if (offset > inc_ofs - 4) + continue; + loadslot = offset >> 2; + + /* loading from the same slot twice is bad (and shouldn't happen...) */ + if (loads[loadslot] != NULL) + break; + + dreg = arch_get_irn_register(arch_env, node); + if (regmask & (1 << dreg->index)) { + /* this register is already used */ + break; + } + regmask |= 1 << dreg->index; + + loads[loadslot] = node; + if (loadslot > maxslot) + maxslot = loadslot; + } + + if (maxslot < 0) + return; + + /* find the first slot */ + for (i = maxslot; i >= 0; --i) { + ir_node *load = loads[i]; + + if (load == NULL) + break; + } + + ofs = inc_ofs - (maxslot + 1) * 4; + inc_ofs = (i+1) * 4; + + /* create a new IncSP if needed */ + block = get_nodes_block(irn); + irg = cg->irg; + if (inc_ofs > 0) { + pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn)); + sched_add_before(irn, pred_sp); + } + + /* walk through the Loads and create Pops for them */ + for (++i; i <= maxslot; ++i) { + ir_node *load = loads[i]; + ir_node *mem, *pop; + const ir_edge_t *edge, *tmp; + const arch_register_t *reg; + + mem = get_irn_n(load, n_ia32_mem); + reg = arch_get_irn_register(arch_env, load); + + pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp); + arch_set_irn_register(arch_env, pop, reg); + + copy_mark(load, pop); + + /* create stackpointer Proj */ + pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + arch_set_irn_register(arch_env, pred_sp, esp); + + sched_add_before(irn, pop); + + /* rewire now */ + foreach_out_edge_safe(load, edge, tmp) { + ir_node *proj = get_edge_src_irn(edge); + + set_Proj_pred(proj, pop); + } + + /* we can remove the Load now */ + sched_remove(load); + kill_node(load); + } + + be_set_IncSP_offset(irn, -ofs); + be_set_IncSP_pred(irn, pred_sp); +} + + /** * Find a free GP register if possible, else return NULL. */ @@ -545,19 +813,14 @@ static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, * @return the new stack value */ static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block, - ir_node *stack, ir_node *schedpoint, - const arch_register_t *reg) + ir_node *stack, ir_node *schedpoint) { const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; - ir_node *noreg, *nomem, *push, *val; - val = new_rd_ia32_ProduceVal(NULL, irg, block); - arch_set_irn_register(arch_env, val, reg); - sched_add_before(schedpoint, val); - - noreg = ia32_new_NoReg_gp(cg); - nomem = get_irg_no_mem(irg); - push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack); + ir_node *val = ia32_new_Unknown_gp(cg); + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack); sched_add_before(schedpoint, push); stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack); @@ -567,7 +830,7 @@ static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block, } /** - * Optimize an IncSp by replacing it with push/pop + * Optimize an IncSp by replacing it with Push/Pop. */ static void peephole_be_IncSP(ir_node *node) { @@ -580,11 +843,14 @@ static void peephole_be_IncSP(ir_node *node) int offset; /* first optimize incsp->incsp combinations */ - be_peephole_IncSP_IncSP(node); + node = be_peephole_IncSP_IncSP(node); /* transform IncSP->Store combinations to Push where possible */ peephole_IncSP_Store_to_push(node); + /* transform Load->IncSP combinations to Pop where possible */ + peephole_Load_IncSP_to_pop(node); + if (arch_get_irn_register(arch_env, node) != esp) return; @@ -615,19 +881,14 @@ static void peephole_be_IncSP(ir_node *node) dbgi = get_irn_dbg_info(node); block = get_nodes_block(node); stack = be_get_IncSP_pred(node); - reg = &ia32_gp_regs[REG_EAX]; - - stack = create_push(dbgi, irg, block, stack, node, reg); + stack = create_push(dbgi, irg, block, stack, node); if (offset == +8) { - stack = create_push(dbgi, irg, block, stack, node, reg); + stack = create_push(dbgi, irg, block, stack, node); } } - be_peephole_before_exchange(node, stack); - sched_remove(node); - exchange(node, stack); - be_peephole_after_exchange(stack); + be_peephole_exchange(node, stack); } /** @@ -670,10 +931,8 @@ static void peephole_ia32_Const(ir_node *node) sched_add_before(node, produceval); sched_add_before(node, xor); - be_peephole_before_exchange(node, xor); - exchange(node, xor); - sched_remove(node); - be_peephole_after_exchange(xor); + copy_mark(node, xor); + be_peephole_exchange(node, xor); } static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node) @@ -878,11 +1137,9 @@ exchange: DBG_OPT_LEA2ADD(node, res); /* exchange the Add and the LEA */ - be_peephole_before_exchange(node, res); sched_add_before(node, res); - sched_remove(node); - exchange(node, res); - be_peephole_after_exchange(res); + copy_mark(node, res); + be_peephole_exchange(node, res); } /** @@ -914,18 +1171,14 @@ static void peephole_ia32_Imul_split(ir_node *imul) { load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); /* copy all attributes */ - set_irn_pinned(load, get_irn_pinned(imul)); - set_ia32_op_type(load, ia32_AddrModeS); - set_ia32_ls_mode(load, get_ia32_ls_mode(imul)); - - set_ia32_am_scale(load, get_ia32_am_scale(imul)); - set_ia32_am_sc(load, get_ia32_am_sc(imul)); - set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul)); - if (is_ia32_am_sc_sign(imul)) - set_ia32_am_sc_sign(load); - if (is_ia32_use_frame(imul)) - set_ia32_use_frame(load); - set_ia32_frame_ent(load, get_ia32_frame_ent(imul)); + set_irn_pinned( load, get_irn_pinned(imul)); + set_ia32_op_type( load, ia32_AddrModeS); + ia32_copy_am_attrs(load, imul); + + set_ia32_am_offs_int( imul, 0); + set_ia32_am_sc( imul, NULL); + set_ia32_am_scale( imul, 0); + clear_ia32_am_sc_sign(imul); sched_add_before(imul, load); @@ -933,11 +1186,13 @@ static void peephole_ia32_Imul_split(ir_node *imul) { res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); arch_set_irn_register(arch_env, res, reg); - be_peephole_after_exchange(res); + be_peephole_new_node(res); set_irn_n(imul, n_ia32_IMul_mem, mem); noreg = get_irn_n(imul, n_ia32_IMul_left); - set_irn_n(imul, n_ia32_IMul_left, res); + set_irn_n(imul, n_ia32_IMul_base, noreg); + set_irn_n(imul, n_ia32_IMul_index, noreg); + set_irn_n(imul, n_ia32_IMul_left, res); set_ia32_op_type(imul, ia32_Normal); } @@ -964,13 +1219,14 @@ void ia32_peephole_optimization(ia32_code_gen_t *new_cg) /* register peephole optimisations */ clear_irp_opcodes_generic_func(); - register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); - //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store); - register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP); - register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea); - register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test); + register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); + register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP); + register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea); + register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp); + register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp); + register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test); register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test); - register_peephole_optimisation(op_be_Return, peephole_ia32_Return); + register_peephole_optimisation(op_be_Return, peephole_ia32_Return); if (! ia32_cg_config.use_imul_mem_imm32) register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split); if (ia32_cg_config.use_pxor) @@ -1001,7 +1257,7 @@ static INLINE void try_kill(ir_node *node) sched_remove(node); } - be_kill_node(node); + kill_node(node); } static void optimize_conv_store(ir_node *node) @@ -1035,9 +1291,9 @@ static void optimize_conv_store(ir_node *node) set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val)); if(get_irn_n_edges(pred_proj) == 0) { - be_kill_node(pred_proj); + kill_node(pred_proj); if(pred != pred_proj) - be_kill_node(pred); + kill_node(pred); } } @@ -1162,9 +1418,9 @@ static void optimize_conv_conv(ir_node *node) exchange(node, result_conv); if(get_irn_n_edges(pred_proj) == 0) { - be_kill_node(pred_proj); + kill_node(pred_proj); if(pred != pred_proj) - be_kill_node(pred); + kill_node(pred); } optimize_conv_conv(result_conv); }