X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=700479b9c00e7b2e319ab24a9da810dbc3464214;hb=1c89dc2a2c3cccd6e29fcfbf65248496db66ab92;hp=65699a0f83073877037961f33646fe29b0822310;hpb=f9e10681f491baabe1e401a429f7f68c76b38062;p=libfirm

diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c
index 65699a0f8..700479b9c 100644
--- a/ir/be/ia32/ia32_optimize.c
+++ b/ir/be/ia32/ia32_optimize.c
@@ -40,11 +40,11 @@
 #include "irdump.h"
 #include "error.h"
 
-#include "../be_t.h"
-#include "../beabi.h"
-#include "../benode.h"
-#include "../besched.h"
-#include "../bepeephole.h"
+#include "be_t.h"
+#include "beabi.h"
+#include "benode.h"
+#include "besched.h"
+#include "bepeephole.h"
 
 #include "ia32_new_nodes.h"
 #include "ia32_optimize.h"
@@ -186,8 +186,8 @@ static void peephole_ia32_Cmp(ir_node *const node)
 	}
 	set_ia32_ls_mode(test, get_ia32_ls_mode(node));
 
-	reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
-	arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
+	reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
+	arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
 
 	foreach_out_edge_safe(node, edge, tmp) {
 		ir_node *const user = get_edge_src_irn(edge);
@@ -765,7 +765,7 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn)
 		if (loads[loadslot] != NULL)
 			break;
 
-		dreg = arch_irn_get_register(node, pn_ia32_Load_res);
+		dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
 		if (regmask & (1 << dreg->index)) {
 			/* this register is already used */
 			break;
@@ -806,10 +806,10 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn)
 		const arch_register_t *reg;
 
 		mem = get_irn_n(load, n_ia32_mem);
-		reg = arch_irn_get_register(load, pn_ia32_Load_res);
+		reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
 
 		pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
-		arch_irn_set_register(pop, pn_ia32_Load_res, reg);
+		arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
 
 		copy_mark(load, pop);
 
@@ -849,7 +849,7 @@ static const arch_register_t *get_free_gp_reg(ir_graph *irg)
 		if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
 			continue;
 
-		if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
+		if (be_peephole_get_value(reg->global_index) == NULL)
 			return reg;
 	}
 
@@ -976,7 +976,7 @@ static void peephole_ia32_Const(ir_node *node)
 	if (ia32_cg_config.use_mov_0)
 		return;
 	/* xor destroys the flags, so no-one must be using them */
-	if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
+	if (be_peephole_get_value(REG_EFLAGS) != NULL)
 		return;
 
 	reg = arch_get_irn_register(node);
@@ -1066,7 +1066,7 @@ static void peephole_ia32_Lea(ir_node *node)
 	assert(is_ia32_Lea(node));
 
 	/* we can only do this if it is allowed to clobber the flags */
-	if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
+	if (be_peephole_get_value(REG_EFLAGS) != NULL)
 		return;
 
 	base  = get_irn_n(node, n_ia32_Lea_base);
@@ -1249,7 +1249,7 @@ static void peephole_ia32_Conv_I2I(ir_node *node)
 	if (get_mode_size_bits(smaller_mode) != 16 ||
 			!mode_is_signed(smaller_mode)          ||
 			eax != arch_get_irn_register(val)      ||
-			eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
+			eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
 		return;
 
 	dbgi  = get_irn_dbg_info(node);
@@ -1439,9 +1439,9 @@ static void optimize_conv_conv(ir_node *node)
 
 			/* Argh:We must change the opcode to 8bit AND copy the register constraints */
 			if (get_mode_size_bits(conv_mode) == 8) {
+				const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
 				set_irn_op(pred, op_ia32_Conv_I2I8Bit);
-				arch_set_in_register_reqs(pred,
-				                          arch_get_in_register_reqs(node));
+				arch_set_irn_register_reqs_in(pred, reqs);
 			}
 		} else {
 			/* we don't want to end up with 2 loads, so we better do nothing */
@@ -1454,9 +1454,9 @@ static void optimize_conv_conv(ir_node *node)
 
 			/* Argh:We must change the opcode to 8bit AND copy the register constraints */
 			if (get_mode_size_bits(conv_mode) == 8) {
+				const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
 				set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
-				arch_set_in_register_reqs(result_conv,
-				                          arch_get_in_register_reqs(node));
+				arch_set_irn_register_reqs_in(result_conv, reqs);
 			}
 		}
 	} else {