X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=5f7ac531fc58d2ff9169f35f6d3f1773cf0f4ade;hb=c2ead6606a9c2f318a628b152ec0ce16cbbe4483;hp=b6b15999d2b80ecf425dc6f0df855d2113545325;hpb=78d60be6a1818431d01b10bd90a74556d12f5254;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index b6b15999d..f67ae7e19 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -1,3 +1,28 @@ +/* + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + +/** + * @file + * @brief Implements several optimizations for IA32. + * @author Matthias Braun, Christian Wuerdig + * @version $Id$ + */ #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -5,1162 +30,1108 @@ #include "irnode.h" #include "irprog_t.h" #include "ircons.h" +#include "irtools.h" #include "firm_types.h" #include "iredges.h" #include "tv.h" #include "irgmod.h" +#include "irgwalk.h" +#include "height.h" +#include "irbitset.h" +#include "irprintf.h" +#include "error.h" #include "../be_t.h" #include "../beabi.h" #include "../benode_t.h" #include "../besched_t.h" +#include "../bepeephole.h" #include "ia32_new_nodes.h" +#include "ia32_optimize.h" #include "bearch_ia32_t.h" -#include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */ +#include "gen_ia32_regalloc_if.h" +#include "ia32_transform.h" +#include "ia32_dbg_stat.h" +#include "ia32_util.h" +#include "ia32_architecture.h" -#undef is_NoMem -#define is_NoMem(irn) (get_irn_op(irn) == op_NoMem) +DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -typedef int is_op_func_t(const ir_node *n); +static const arch_env_t *arch_env; +static ia32_code_gen_t *cg; /** - * checks if a node represents the NOREG value + * Returns non-zero if the given node produces + * a zero flag. + * + * @param node the node to check + * @param pn if >= 0, the projection number of the used result */ -static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) { - be_abi_irg_t *babi = cg->birg->abi; - const arch_register_t *fp_noreg = USE_SSE2(cg) ? - &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]; +static int produces_zero_flag(ir_node *node, int pn) +{ + ir_node *count; + const ia32_immediate_attr_t *imm_attr; - return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) || - (be_abi_get_callee_save_irn(babi, fp_noreg) == irn); -} + if (!is_ia32_irn(node)) + return 0; + if (pn >= 0) { + if (pn != pn_ia32_res) + return 0; + } + switch (get_ia32_irn_opcode(node)) { + case iro_ia32_Add: + case iro_ia32_Adc: + case iro_ia32_And: + case iro_ia32_Or: + case iro_ia32_Xor: + case iro_ia32_Sub: + case iro_ia32_Sbb: + case iro_ia32_Neg: + case iro_ia32_Inc: + case iro_ia32_Dec: + return 1; -/************************************************* - * _____ _ _ - * / ____| | | | | - * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___ - * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __| - * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \ - * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/ - * - *************************************************/ + case iro_ia32_ShlD: + case iro_ia32_ShrD: + case iro_ia32_Shl: + case iro_ia32_Shr: + case iro_ia32_Sar: + assert(n_ia32_ShlD_count == n_ia32_ShrD_count); + assert(n_ia32_Shl_count == n_ia32_Shr_count + && n_ia32_Shl_count == n_ia32_Sar_count); + if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) { + count = get_irn_n(node, n_ia32_ShlD_count); + } else { + count = get_irn_n(node, n_ia32_Shl_count); + } + /* when shift count is zero the flags are not affected, so we can only + * do this for constants != 0 */ + if (!is_ia32_Immediate(count)) + return 0; + + imm_attr = get_ia32_immediate_attr_const(count); + if (imm_attr->symconst != NULL) + return 0; + if ((imm_attr->offset & 0x1f) == 0) + return 0; + return 1; + + default: + break; + } + return 0; +} /** - * creates a unique ident by adding a number to a tag + * If the given node has not mode_T, creates a mode_T version (with a result Proj). + * + * @param node the node to change * - * @param tag the tag string, must contain a %d if a number - * should be added + * @return the new mode_T node (if the mode was changed) or node itself */ -static ident *unique_id(const char *tag) +static ir_node *turn_into_mode_t(ir_node *node) { - static unsigned id = 0; - char str[256]; + ir_node *block; + ir_node *res_proj; + ir_node *new_node; + const arch_register_t *reg; - snprintf(str, sizeof(str), tag, ++id); - return new_id_from_str(str); -} + if(get_irn_mode(node) == mode_T) + return node; + assert(get_irn_mode(node) == mode_Iu); + new_node = exact_copy(node); + set_irn_mode(new_node, mode_T); -/** - * Transforms a SymConst. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir SymConst node - * @param mode mode of the SymConst - * @return the created ia32 Const node - */ -static ir_node *gen_SymConst(ia32_transform_env_t *env) { - ir_node *cnst; - dbg_info *dbg = env->dbg; - ir_mode *mode = env->mode; - ir_graph *irg = env->irg; - ir_node *block = env->block; - - if (mode_is_float(mode)) { - if (USE_SSE2(env->cg)) - cnst = new_rd_ia32_fConst(dbg, irg, block, mode); - else - cnst = new_rd_ia32_vfConst(dbg, irg, block, mode); - } - else { - cnst = new_rd_ia32_Const(dbg, irg, block, mode); - } - set_ia32_Const_attr(cnst, env->irn); - return cnst; -} + block = get_nodes_block(new_node); + res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu, + pn_ia32_res); -/** - * Get a primitive type for a mode. - */ -static ir_type *get_prim_type(pmap *types, ir_mode *mode) -{ - pmap_entry *e = pmap_find(types, mode); - ir_type *res; - - if (! e) { - char buf[64]; - snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode)); - res = new_type_primitive(new_id_from_str(buf), mode); - pmap_insert(types, mode, res); - } - else - res = e->value; - return res; -} + reg = arch_get_irn_register(arch_env, node); + arch_set_irn_register(arch_env, res_proj, reg); -/** - * Get an entity that is initialized with a tarval - */ -static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst) -{ - tarval *tv = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(cg->tv_ent, tv); - entity *res; - ir_graph *rem; - - if (! e) { - ir_mode *mode = get_irn_mode(cnst); - ir_type *tp = get_Const_type(cnst); - if (tp == firm_unknown_type) - tp = get_prim_type(cg->types, mode); - - res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp); - - set_entity_ld_ident(res, get_entity_ident(res)); - set_entity_visibility(res, visibility_local); - set_entity_variability(res, variability_constant); - set_entity_allocation(res, allocation_static); - - /* we create a new entity here: It's initialization must resist on the - const code irg */ - rem = current_ir_graph; - current_ir_graph = get_const_code_irg(); - set_atomic_ent_value(res, new_Const_type(tv, tp)); - current_ir_graph = rem; - } - else - res = e->value; - return res; + be_peephole_before_exchange(node, res_proj); + sched_add_before(node, new_node); + sched_remove(node); + exchange(node, res_proj); + be_peephole_after_exchange(res_proj); + + return new_node; } /** - * Transforms a Const. - * - * @param mod the debug module - * @param block the block the new node should belong to - * @param node the ir Const node - * @param mode mode of the Const - * @return the created ia32 Const node + * Peephole optimization for Test instructions. + * We can remove the Test, if a zero flags was produced which is still + * live. */ -static ir_node *gen_Const(ia32_transform_env_t *env) { - ir_node *cnst; - symconst_symbol sym; - ir_graph *irg = env->irg; - ir_node *block = env->block; - ir_node *node = env->irn; - dbg_info *dbg = env->dbg; - ir_mode *mode = env->mode; - - if (mode_is_float(mode)) { - if (! USE_SSE2(env->cg)) { - cnst_classify_t clss = classify_Const(node); - - if (clss == CNST_NULL) - return new_rd_ia32_vfldz(dbg, irg, block, mode); - else if (clss == CNST_ONE) - return new_rd_ia32_vfld1(dbg, irg, block, mode); - } - sym.entity_p = get_entity_for_tv(env->cg, node); - - cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent); - env->irn = cnst; - cnst = gen_SymConst(env); - } - else { - cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node)); - set_ia32_Const_attr(cnst, node); - } - return cnst; -} - +static void peephole_ia32_Test(ir_node *node) +{ + ir_node *left = get_irn_n(node, n_ia32_Test_left); + ir_node *right = get_irn_n(node, n_ia32_Test_right); + ir_node *flags_proj; + ir_node *block; + ir_mode *flags_mode; + int pn = -1; + ir_node *schedpoint; + const ir_edge_t *edge; + assert(n_ia32_Test_left == n_ia32_Test8Bit_left + && n_ia32_Test_right == n_ia32_Test8Bit_right); -/** - * Transforms (all) Const's into ia32_Const and places them in the - * block where they are used (or in the cfg-pred Block in case of Phi's). - * Additionally all reference nodes are changed into mode_Is nodes. - */ -void ia32_place_consts_set_modes(ir_node *irn, void *env) { - ia32_code_gen_t *cg = env; - ia32_transform_env_t tenv; - ir_mode *mode; - ir_node *pred, *cnst; - int i; - opcode opc; - - if (is_Block(irn)) + /* we need a test for 0 */ + if(left != right) return; - mode = get_irn_mode(irn); + block = get_nodes_block(node); + if(get_nodes_block(left) != block) + return; - /* transform all reference nodes into mode_Is nodes */ - if (mode_is_reference(mode)) { - mode = mode_Is; - set_irn_mode(irn, mode); + if(is_Proj(left)) { + pn = get_Proj_proj(left); + left = get_Proj_pred(left); } - tenv.block = get_nodes_block(irn); - tenv.cg = cg; - tenv.irg = cg->irg; - tenv.mod = cg->mod; - - /* Loop over all predecessors and check for Sym/Const nodes */ - for (i = get_irn_arity(irn) - 1; i >= 0; --i) { - pred = get_irn_n(irn, i); - cnst = NULL; - opc = get_irn_opcode(pred); - tenv.irn = pred; - tenv.mode = get_irn_mode(pred); - tenv.dbg = get_irn_dbg_info(pred); - - /* If it's a Phi, then we need to create the */ - /* new Const in it's predecessor block */ - if (is_Phi(irn)) { - tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i); - } + /* happens rarely, but if it does code will panic' */ + if (is_ia32_Unknown_GP(left)) + return; - /* put the const into the block where the original const was */ - if (! cg->opt.placecnst) { - tenv.block = get_nodes_block(pred); - } + /* walk schedule up and abort when we find left or some other node destroys + the flags */ + schedpoint = sched_prev(node); + while(schedpoint != left) { + schedpoint = sched_prev(schedpoint); + if(arch_irn_is(arch_env, schedpoint, modify_flags)) + return; + if(schedpoint == block) + panic("couldn't find left"); + } - switch (opc) { - case iro_Const: - cnst = gen_Const(&tenv); - break; - case iro_SymConst: - cnst = gen_SymConst(&tenv); - break; - default: - break; - } + /* make sure only Lg/Eq tests are used */ + foreach_out_edge(node, edge) { + ir_node *user = get_edge_src_irn(edge); + int pnc = get_ia32_condcode(user); - /* if we found a const, then set it */ - if (cnst) { - set_irn_n(irn, i, cnst); + if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) { + return; } } -} + if(!produces_zero_flag(left, pn)) + return; + left = turn_into_mode_t(left); -/******************************************************************************************************** - * _____ _ _ ____ _ _ _ _ _ - * | __ \ | | | | / __ \ | | (_) (_) | | (_) - * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __ - * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \ - * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | | - * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_| - * | | | | - * |_| |_| - ********************************************************************************************************/ + flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode; + flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode, + pn_ia32_flags); + arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]); -/** - * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION. - */ + assert(get_irn_mode(node) != mode_T); -static int ia32_cnst_compare(ir_node *n1, ir_node *n2) { - return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2); + be_peephole_before_exchange(node, flags_proj); + exchange(node, flags_proj); + sched_remove(node); + be_peephole_after_exchange(flags_proj); } /** - * Checks for potential CJmp/CJmpAM optimization candidates. + * AMD Athlon works faster when RET is not destination of + * conditional jump or directly preceded by other jump instruction. + * Can be avoided by placing a Rep prefix before the return. */ -static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) { - ir_node *cand = NULL; - ir_node *prev = sched_prev(irn); - - if (is_Block(prev)) { - if (get_Block_n_cfgpreds(prev) == 1) - prev = get_Block_cfgpred(prev, 0); - else - prev = NULL; - } +static void peephole_ia32_Return(ir_node *node) { + ir_node *block, *irn; - /* The predecessor must be a ProjX. */ - if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) { - prev = get_Proj_pred(prev); - - if (is_op_func(prev)) - cand = prev; - } + if (!ia32_cg_config.use_pad_return) + return; - return cand; -} + block = get_nodes_block(node); -static int is_TestJmp_cand(const ir_node *irn) { - return is_ia32_TestJmp(irn) || is_ia32_And(irn); -} + if (get_Block_n_cfgpreds(block) == 1) { + ir_node *pred = get_Block_cfgpred(block, 0); -/** - * Checks if two consecutive arguments of cand matches - * the two arguments of irn (TestJmp). - */ -static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) { - ir_node *in1 = get_irn_n(irn, 0); - ir_node *in2 = get_irn_n(irn, 1); - int i, n = get_irn_arity(cand); - int same_args = 0; - - for (i = 0; i < n - 1; i++) { - if (get_irn_n(cand, i) == in1 && - get_irn_n(cand, i + 1) == in2) - { - same_args = 1; - break; + if (is_Jmp(pred)) { + /* The block of the return has only one predecessor, + which jumps directly to this block. + This jump will be encoded as a fall through, so we + ignore it here. + However, the predecessor might be empty, so it must be + ensured that empty blocks are gone away ... */ + return; } } - if (same_args) - return ia32_cnst_compare(cand, irn); - - return 0; + /* check if this return is the first on the block */ + sched_foreach_reverse_from(node, irn) { + switch (get_irn_opcode(irn)) { + case beo_Return: + /* the return node itself, ignore */ + continue; + case beo_Barrier: + /* ignore the barrier, no code generated */ + continue; + case beo_IncSP: + /* arg, IncSP 0 nodes might occur, ignore these */ + if (be_get_IncSP_offset(irn) == 0) + continue; + return; + case iro_Phi: + continue; + default: + return; + } + } + /* yep, return is the first real instruction in this block */ +#if 0 + { + /* add an rep prefix to the return */ + ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block); + keep_alive(rep); + sched_add_before(node, rep); + } +#else + /* ensure, that the 3 byte return is generated */ + be_Return_set_emit_pop(node, 1); +#endif } +/* only optimize up to 48 stores behind IncSPs */ +#define MAXPUSH_OPTIMIZE 48 + /** - * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And) + * Tries to create Push's from IncSP, Store combinations. + * The Stores are replaced by Push's, the IncSP is modified + * (possibly into IncSP 0, but not removed). */ -static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) { - ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand); - int replace = 0; +static void peephole_IncSP_Store_to_push(ir_node *irn) +{ + int i, maxslot, inc_ofs; + ir_node *node; + ir_node *stores[MAXPUSH_OPTIMIZE]; + ir_node *block = get_nodes_block(irn); + ir_graph *irg = cg->irg; + ir_node *curr_sp; + ir_mode *spmode = get_irn_mode(irn); - /* we found a possible candidate */ - replace = cand ? is_TestJmp_replacement(cand, irn) : 0; + memset(stores, 0, sizeof(stores)); - if (replace) { - DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn)); + assert(be_is_IncSP(irn)); - if (is_ia32_And(cand)) - set_irn_op(irn, op_ia32_CJmpAM); - else - set_irn_op(irn, op_ia32_CJmp); + inc_ofs = be_get_IncSP_offset(irn); + if (inc_ofs < 4) + return; - DB((cg->mod, LEVEL_1, "%+F\n", irn)); - } -} + /* + * We first walk the schedule after the IncSP node as long as we find + * suitable stores that could be transformed to a push. + * We save them into the stores array which is sorted by the frame offset/4 + * attached to the node + */ + maxslot = -1; + for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) { + ir_node *mem; + int offset; + int storeslot; + + /* it has to be a Store */ + if (!is_ia32_Store(node)) + break; -static int is_CondJmp_cand(const ir_node *irn) { - return is_ia32_CondJmp(irn) || is_ia32_Sub(irn); -} + /* it has to use our sp value */ + if (get_irn_n(node, n_ia32_base) != irn) + continue; + /* Store has to be attached to NoMem */ + mem = get_irn_n(node, n_ia32_mem); + if (!is_NoMem(mem)) + continue; + + /* unfortunately we can't support the full AMs possible for push at the + * moment. TODO: fix this */ + if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index))) + break; -/** - * Checks if the arguments of cand are the same of irn. - */ -static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) { - int i, n = get_irn_arity(cand); - int same_args = 1; + offset = get_ia32_am_offs_int(node); + /* we should NEVER access uninitialized stack BELOW the current SP */ + assert(offset >= 0); - for (i = 0; i < n; i++) { - if (get_irn_n(cand, i) == get_irn_n(irn, i)) { - same_args = 0; + offset = inc_ofs - 4 - offset; + + /* storing at half-slots is bad */ + if ((offset & 3) != 0) break; - } - } - if (same_args) - return ia32_cnst_compare(cand, irn); + if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4) + continue; + storeslot = offset >> 2; - return 0; -} + /* storing into the same slot twice is bad (and shouldn't happen...) */ + if (stores[storeslot] != NULL) + break; -/** - * Tries to replace a CondJmp by a CJmpAM - */ -static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) { - ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand); - int replace = 0; + stores[storeslot] = node; + if (storeslot > maxslot) + maxslot = storeslot; + } - /* we found a possible candidate */ - replace = cand ? is_CondJmp_replacement(cand, irn) : 0; + curr_sp = be_get_IncSP_pred(irn); - if (replace) { - DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn)); + /* walk through the stores and create Pushs for them */ + for (i = 0; i <= maxslot; ++i) { + const arch_register_t *spreg; + ir_node *push; + ir_node *val, *mem, *mem_proj; + ir_node *store = stores[i]; + ir_node *noreg = ia32_new_NoReg_gp(cg); - set_irn_op(irn, op_ia32_CJmp); + if (store == NULL) + break; - DB((cg->mod, LEVEL_1, "%+F\n", irn)); - } -} + val = get_irn_n(store, n_ia32_unary_op); + mem = get_irn_n(store, n_ia32_mem); + spreg = arch_get_irn_register(cg->arch_env, curr_sp); -/** - * Performs Peephole Optimizations - */ -void ia32_peephole_optimization(ir_node *irn, void *env) { - if (is_ia32_TestJmp(irn)) { - ia32_optimize_TestJmp(irn, env); - } - else if (is_ia32_CondJmp(irn)) { - ia32_optimize_CondJmp(irn, env); - } -} + push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp); + sched_add_before(irn, push); + /* create stackpointer Proj */ + curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack); + arch_set_irn_register(cg->arch_env, curr_sp, spreg); -/****************************************************************** - * _ _ __ __ _ - * /\ | | | | | \/ | | | - * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___ - * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \ - * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/ - * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___| - * - ******************************************************************/ + /* create memory Proj */ + mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); -static int node_is_ia32_comm(const ir_node *irn) { - return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0; -} + /* use the memproj now */ + exchange(store, mem_proj); -static int ia32_get_irn_n_edges(const ir_node *irn) { - const ir_edge_t *edge; - int cnt = 0; + /* we can remove the store now */ + sched_remove(store); - foreach_out_edge(irn, edge) { - cnt++; + inc_ofs -= 4; } - return cnt; + be_set_IncSP_offset(irn, inc_ofs); + be_set_IncSP_pred(irn, curr_sp); } /** - * Returns the first mode_M Proj connected to irn. + * Find a free GP register if possible, else return NULL. */ -static ir_node *get_mem_proj(const ir_node *irn) { - const ir_edge_t *edge; - ir_node *src; - - assert(get_irn_mode(irn) == mode_T && "expected mode_T node"); - - foreach_out_edge(irn, edge) { - src = get_edge_src_irn(edge); +static const arch_register_t *get_free_gp_reg(void) +{ + int i; - assert(is_Proj(src) && "Proj expected"); + for(i = 0; i < N_ia32_gp_REGS; ++i) { + const arch_register_t *reg = &ia32_gp_regs[i]; + if(arch_register_type_is(reg, ignore)) + continue; - if (get_irn_mode(src) == mode_M) - return src; + if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL) + return &ia32_gp_regs[i]; } return NULL; } /** - * Returns the first Proj with mode != mode_M connected to irn. + * Creates a Pop instruction before the given schedule point. + * + * @param dbgi debug info + * @param irg the graph + * @param block the block + * @param stack the previous stack value + * @param schedpoint the new node is added before this node + * @param reg the register to pop + * + * @return the new stack value */ -static ir_node *get_res_proj(const ir_node *irn) { - const ir_edge_t *edge; - ir_node *src; +static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, + ir_node *stack, ir_node *schedpoint, + const arch_register_t *reg) +{ + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + ir_node *pop; + ir_node *keep; + ir_node *val; + ir_node *in[1]; - assert(get_irn_mode(irn) == mode_T && "expected mode_T node"); + pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack); - foreach_out_edge(irn, edge) { - src = get_edge_src_irn(edge); + stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + arch_set_irn_register(arch_env, stack, esp); + val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res); + arch_set_irn_register(arch_env, val, reg); - assert(is_Proj(src) && "Proj expected"); + sched_add_before(schedpoint, pop); - if (get_irn_mode(src) != mode_M) - return src; - } + in[0] = val; + keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); + sched_add_before(schedpoint, keep); - return NULL; + return stack; } /** - * Determines if pred is a Proj and if is_op_func returns true for it's predecessor. + * Creates a Push instruction before the given schedule point. + * + * @param dbgi debug info + * @param irg the graph + * @param block the block + * @param stack the previous stack value + * @param schedpoint the new node is added before this node + * @param reg the register to pop * - * @param pred The node to be checked - * @param is_op_func The check-function - * @return 1 if conditions are fulfilled, 0 otherwise + * @return the new stack value */ -static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) { - if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) { - return 1; - } +static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block, + ir_node *stack, ir_node *schedpoint, + const arch_register_t *reg) +{ + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + ir_node *noreg, *nomem, *push, *val; - return 0; + val = new_rd_ia32_ProduceVal(NULL, irg, block); + arch_set_irn_register(arch_env, val, reg); + sched_add_before(schedpoint, val); + + noreg = ia32_new_NoReg_gp(cg); + nomem = get_irg_no_mem(irg); + push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack); + sched_add_before(schedpoint, push); + + stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack); + arch_set_irn_register(arch_env, stack, esp); + + return stack; } /** - * Determines if pred is a Proj and if is_op_func returns true for it's predecessor - * and if the predecessor is in block bl. - * - * @param bl The block - * @param pred The node to be checked - * @param is_op_func The check-function - * @return 1 if conditions are fulfilled, 0 otherwise + * Optimize an IncSp by replacing it with Push/Pop. */ -static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred, - int (*is_op_func)(const ir_node *n)) +static void peephole_be_IncSP(ir_node *node) { - if (is_Proj(pred)) { - pred = get_Proj_pred(pred); - if ((bl == get_nodes_block(pred)) && is_op_func(pred)) { - return 1; - } - } + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + const arch_register_t *reg; + ir_graph *irg = current_ir_graph; + dbg_info *dbgi; + ir_node *block; + ir_node *stack; + int offset; - return 0; -} + /* first optimize incsp->incsp combinations */ + be_peephole_IncSP_IncSP(node); + /* transform IncSP->Store combinations to Push where possible */ + peephole_IncSP_Store_to_push(node); + if (arch_get_irn_register(arch_env, node) != esp) + return; -/** - * Checks if irn is a candidate for address calculation or address mode. - * - * address calculation (AC): - * - none of the operand must be a Load within the same block OR - * - all Loads must have more than one user OR - * - the irn has a frame entity (it's a former FrameAddr) - * - * address mode (AM): - * - at least one operand has to be a Load within the same block AND - * - the load must not have other users than the irn AND - * - the irn must not have a frame entity set - * - * @param block The block the Loads must/not be in - * @param irn The irn to check - * @param check_addr 1 if to check for address calculation, 0 otherwise - * return 1 if irn is a candidate for AC or AM, 0 otherwise - */ -static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) { - ir_node *in; - int n, is_cand = check_addr; + /* replace IncSP -4 by Pop freereg when possible */ + offset = be_get_IncSP_offset(node); + if ((offset != -8 || ia32_cg_config.use_add_esp_8) && + (offset != -4 || ia32_cg_config.use_add_esp_4) && + (offset != +4 || ia32_cg_config.use_sub_esp_4) && + (offset != +8 || ia32_cg_config.use_sub_esp_8)) + return; - in = get_irn_n(irn, 2); + if (offset < 0) { + /* we need a free register for pop */ + reg = get_free_gp_reg(); + if (reg == NULL) + return; - if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) { - n = ia32_get_irn_n_edges(in); - is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand); - } + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + stack = be_get_IncSP_pred(node); - in = get_irn_n(irn, 3); + stack = create_pop(dbgi, irg, block, stack, node, reg); - if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) { - n = ia32_get_irn_n_edges(in); - is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand); - } + if (offset == -8) { + stack = create_pop(dbgi, irg, block, stack, node, reg); + } + } else { + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + stack = be_get_IncSP_pred(node); + reg = &ia32_gp_regs[REG_EAX]; - is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand; + stack = create_push(dbgi, irg, block, stack, node, reg); - return is_cand; + if (offset == +8) { + stack = create_push(dbgi, irg, block, stack, node, reg); + } + } + + be_peephole_before_exchange(node, stack); + sched_remove(node); + exchange(node, stack); + be_peephole_after_exchange(stack); } /** - * Compares the base and index addr and the load/store entities - * and returns 1 if they are equal. + * Peephole optimisation for ia32_Const's */ -static int load_store_addr_is_equal(const ir_node *load, const ir_node *store, - const ir_node *addr_b, const ir_node *addr_i) +static void peephole_ia32_Const(ir_node *node) { - int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1)); - entity *lent = get_ia32_frame_ent(load); - entity *sent = get_ia32_frame_ent(store); - ident *lid = get_ia32_am_sc(load); - ident *sid = get_ia32_am_sc(store); - char *loffs = get_ia32_am_offs(load); - char *soffs = get_ia32_am_offs(store); - - /* are both entities set and equal? */ - if (is_equal && (lent || sent)) - is_equal = lent && sent && (lent == sent); - - /* are address mode idents set and equal? */ - if (is_equal && (lid || sid)) - is_equal = lid && sid && (lid == sid); - - /* are offsets set and equal */ - if (is_equal && (loffs || soffs)) - is_equal = loffs && soffs && strcmp(loffs, soffs) == 0; - - /* are the load and the store of the same mode? */ - is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0; - - return is_equal; -} + const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node); + const arch_register_t *reg; + ir_graph *irg = current_ir_graph; + ir_node *block; + dbg_info *dbgi; + ir_node *produceval; + ir_node *xor; + ir_node *noreg; + + /* try to transform a mov 0, reg to xor reg reg */ + if (attr->offset != 0 || attr->symconst != NULL) + return; + if (ia32_cg_config.use_mov_0) + return; + /* xor destroys the flags, so no-one must be using them */ + if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + return; + reg = arch_get_irn_register(arch_env, node); + assert(be_peephole_get_reg_value(reg) == NULL); + /* create xor(produceval, produceval) */ + block = get_nodes_block(node); + dbgi = get_irn_dbg_info(node); + produceval = new_rd_ia32_ProduceVal(dbgi, irg, block); + arch_set_irn_register(arch_env, produceval, reg); -/** - * Folds Add or Sub to LEA if possible - */ -static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) { - ir_graph *irg = get_irn_irg(irn); - dbg_info *dbg = get_irn_dbg_info(irn); - ir_node *block = get_nodes_block(irn); - ir_node *res = irn; - char *offs = NULL; - const char *offs_cnst = NULL; - char *offs_lea = NULL; - int scale = 0; - int isadd = 0; - int dolea = 0; - int have_am_sc = 0; - int am_sc_sign = 0; - ident *am_sc_lea = NULL; - ident *am_sc = NULL; - ir_node *left, *right, *temp; - ir_node *base, *index; - ia32_am_flavour_t am_flav; - - if (is_ia32_Add(irn)) - isadd = 1; - - left = get_irn_n(irn, 2); - right = get_irn_n(irn, 3); - - /* "normalize" arguments in case of add with two operands */ - if (isadd && ! be_is_NoReg(cg, right)) { - /* put LEA == ia32_am_O as right operand */ - if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) { - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - temp = left; - left = right; - right = temp; - } + noreg = ia32_new_NoReg_gp(cg); + xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(), + produceval, produceval); + arch_set_irn_register(arch_env, xor, reg); - /* put LEA != ia32_am_O as left operand */ - if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) { - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - temp = left; - left = right; - right = temp; - } + sched_add_before(node, produceval); + sched_add_before(node, xor); - /* put SHL as left operand iff left is NOT a LEA */ - if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) { - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - temp = left; - left = right; - right = temp; - } - } + be_peephole_before_exchange(node, xor); + exchange(node, xor); + sched_remove(node); + be_peephole_after_exchange(xor); +} - base = left; - index = noreg; - offs = NULL; - scale = 0; - am_flav = 0; +static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node) +{ + return node == cg->noreg_gp; +} - /* check for operation with immediate */ - if (is_ia32_ImmConst(irn)) { - DBG((mod, LEVEL_1, "\tfound op with imm const")); +static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val) +{ + ir_graph *irg = current_ir_graph; + ir_node *start_block = get_irg_start_block(irg); + ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, + 0, val); + arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]); - offs_cnst = get_ia32_cnst(irn); - dolea = 1; - } - else if (is_ia32_ImmSymConst(irn)) { - DBG((mod, LEVEL_1, "\tfound op with imm symconst")); + return immediate; +} - have_am_sc = 1; - dolea = 1; - am_sc = get_ia32_id_cnst(irn); - am_sc_sign = is_ia32_am_sc_sign(irn); - } +static ir_node *create_immediate_from_am(ia32_code_gen_t *cg, + const ir_node *node) +{ + ir_graph *irg = get_irn_irg(node); + ir_node *block = get_nodes_block(node); + int offset = get_ia32_am_offs_int(node); + int sc_sign = is_ia32_am_sc_sign(node); + ir_entity *entity = get_ia32_am_sc(node); + ir_node *res; + + res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset); + arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]); + return res; +} - /* determine the operand which needs to be checked */ - if (be_is_NoReg(cg, right)) { - temp = left; - } - else { - temp = right; - } +static int is_am_one(const ir_node *node) +{ + int offset = get_ia32_am_offs_int(node); + ir_entity *entity = get_ia32_am_sc(node); - /* check if right operand is AMConst (LEA with ia32_am_O) */ - /* but we can only eat it up if there is no other symconst */ - /* because the linker won't accept two symconsts */ - if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) { - DBG((mod, LEVEL_1, "\tgot op with LEA am_O")); - - offs_lea = get_ia32_am_offs(temp); - am_sc = get_ia32_am_sc(temp); - am_sc_sign = is_ia32_am_sc_sign(temp); - have_am_sc = 1; - dolea = 1; - } + return offset == 1 && entity == NULL; +} - if (isadd) { - /* default for add -> make right operand to index */ - index = right; - dolea = 1; +static int is_am_minus_one(const ir_node *node) +{ + int offset = get_ia32_am_offs_int(node); + ir_entity *entity = get_ia32_am_sc(node); - DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index)); + return offset == -1 && entity == NULL; +} - /* determine the operand which needs to be checked */ - temp = left; - if (is_ia32_Lea(left)) { - temp = right; - } +/** + * Transforms a LEA into an Add or SHL if possible. + */ +static void peephole_ia32_Lea(ir_node *node) +{ + const arch_env_t *arch_env = cg->arch_env; + ir_graph *irg = current_ir_graph; + ir_node *base; + ir_node *index; + const arch_register_t *base_reg; + const arch_register_t *index_reg; + const arch_register_t *out_reg; + int scale; + int has_immediates; + ir_node *op1; + ir_node *op2; + dbg_info *dbgi; + ir_node *block; + ir_node *res; + ir_node *noreg; + ir_node *nomem; + + assert(is_ia32_Lea(node)); + + /* we can only do this if are allowed to globber the flags */ + if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL) + return; - /* check for SHL 1,2,3 */ - if (pred_is_specific_node(temp, is_ia32_Shl)) { - temp = get_Proj_pred(temp); + base = get_irn_n(node, n_ia32_Lea_base); + index = get_irn_n(node, n_ia32_Lea_index); - if (get_ia32_Immop_tarval(temp)) { - scale = get_tarval_long(get_ia32_Immop_tarval(temp)); + if(is_noreg(cg, base)) { + base = NULL; + base_reg = NULL; + } else { + base_reg = arch_get_irn_register(arch_env, base); + } + if(is_noreg(cg, index)) { + index = NULL; + index_reg = NULL; + } else { + index_reg = arch_get_irn_register(arch_env, index); + } - if (scale <= 3) { - index = get_irn_n(temp, 2); + if(base == NULL && index == NULL) { + /* we shouldn't construct these in the first place... */ +#ifdef DEBUG_libfirm + ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n"); +#endif + return; + } - DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index)); - } - } - } + out_reg = arch_get_irn_register(arch_env, node); + scale = get_ia32_am_scale(node); + assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL); + /* check if we have immediates values (frame entities should already be + * expressed in the offsets) */ + if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) { + has_immediates = 1; + } else { + has_immediates = 0; + } - /* fix base */ - if (! be_is_NoReg(cg, index)) { - /* if we have index, but left == right -> no base */ - if (left == right) { - base = noreg; + /* we can transform leas where the out register is the same as either the + * base or index register back to an Add or Shl */ + if(out_reg == base_reg) { + if(index == NULL) { +#ifdef DEBUG_libfirm + if(!has_immediates) { + ir_fprintf(stderr, "Optimisation warning: found lea which is " + "just a copy\n"); } - else if (! is_ia32_Lea(left) && (index != right)) { - /* index != right -> we found a good Shl */ - /* left != LEA -> this Shl was the left operand */ - /* -> base is right operand */ - base = right; +#endif + op1 = base; + goto make_add_immediate; + } + if(scale == 0 && !has_immediates) { + op1 = base; + op2 = index; + goto make_add; + } + /* can't create an add */ + return; + } else if(out_reg == index_reg) { + if(base == NULL) { + if(has_immediates && scale == 0) { + op1 = index; + goto make_add_immediate; + } else if(!has_immediates && scale > 0) { + op1 = index; + op2 = create_immediate_from_int(cg, scale); + goto make_shl; + } else if(!has_immediates) { +#ifdef DEBUG_libfirm + ir_fprintf(stderr, "Optimisation warning: found lea which is " + "just a copy\n"); +#endif } + } else if(scale == 0 && !has_immediates) { + op1 = index; + op2 = base; + goto make_add; } + /* can't create an add */ + return; + } else { + /* can't create an add */ + return; } - /* Try to assimilate a LEA as left operand */ - if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) { - am_flav = get_ia32_am_flavour(left); - - /* If we have an Add with a real right operand (not NoReg) and */ - /* the LEA contains already an index calculation then we create */ - /* a new LEA. */ - /* If the LEA contains already a frame_entity then we also */ - /* create a new one otherwise we would loose it. */ - if ((isadd && !be_is_NoReg(cg, index) && (am_flav & ia32_am_I)) || /* no new LEA if index already set */ - get_ia32_frame_ent(left) || /* no new LEA if stack access */ - (have_am_sc && get_ia32_am_sc(left))) /* no new LEA if AM symconst already present */ - { - DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n")); +make_add_immediate: + if(ia32_cg_config.use_incdec) { + if(is_am_one(node)) { + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + res = new_rd_ia32_Inc(dbgi, irg, block, op1); + arch_set_irn_register(arch_env, res, out_reg); + goto exchange; } - else { - DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n")); - offs = get_ia32_am_offs(left); - am_sc = have_am_sc ? am_sc : get_ia32_am_sc(left); - have_am_sc = am_sc ? 1 : 0; - am_sc_sign = is_ia32_am_sc_sign(left); - base = get_irn_n(left, 0); - index = get_irn_n(left, 1); - scale = get_ia32_am_scale(left); + if(is_am_minus_one(node)) { + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + res = new_rd_ia32_Dec(dbgi, irg, block, op1); + arch_set_irn_register(arch_env, res, out_reg); + goto exchange; } } + op2 = create_immediate_from_am(cg, node); + +make_add: + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + noreg = ia32_new_NoReg_gp(cg); + nomem = new_NoMem(); + res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2); + arch_set_irn_register(arch_env, res, out_reg); + set_ia32_commutative(res); + goto exchange; + +make_shl: + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + noreg = ia32_new_NoReg_gp(cg); + nomem = new_NoMem(); + res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2); + arch_set_irn_register(arch_env, res, out_reg); + goto exchange; + +exchange: + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node)); + + /* add new ADD/SHL to schedule */ + DBG_OPT_LEA2ADD(node, res); + + /* exchange the Add and the LEA */ + be_peephole_before_exchange(node, res); + sched_add_before(node, res); + sched_remove(node); + exchange(node, res); + be_peephole_after_exchange(res); +} - /* ok, we can create a new LEA */ - if (dolea) { - res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is); - - /* add the old offset of a previous LEA */ - if (offs) { - add_ia32_am_offs(res, offs); - } - - /* add the new offset */ - if (isadd) { - if (offs_cnst) { - add_ia32_am_offs(res, offs_cnst); - } - if (offs_lea) { - add_ia32_am_offs(res, offs_lea); - } - } - else { - /* either lea_O-cnst, -cnst or -lea_O */ - if (offs_cnst) { - if (offs_lea) { - add_ia32_am_offs(res, offs_lea); - } - - sub_ia32_am_offs(res, offs_cnst); - } - else { - sub_ia32_am_offs(res, offs_lea); - } - } +/** + * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible. + */ +static void peephole_ia32_Imul_split(ir_node *imul) { + const ir_node *right = get_irn_n(imul, n_ia32_IMul_right); + const arch_register_t *reg; + ir_node *load, *block, *base, *index, *mem, *res, *noreg; + dbg_info *dbgi; + ir_graph *irg; + + if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) { + /* no memory, imm form ignore */ + return; + } + /* we need a free register */ + reg = get_free_gp_reg(); + if (reg == NULL) + return; - /* set the address mode symconst */ - if (have_am_sc) { - set_ia32_am_sc(res, am_sc); - if (am_sc_sign) - set_ia32_am_sc_sign(res); - } + /* fine, we can rebuild it */ + dbgi = get_irn_dbg_info(imul); + block = get_nodes_block(imul); + irg = current_ir_graph; + base = get_irn_n(imul, n_ia32_IMul_base); + index = get_irn_n(imul, n_ia32_IMul_index); + mem = get_irn_n(imul, n_ia32_IMul_mem); + load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); + + /* copy all attributes */ + set_irn_pinned(load, get_irn_pinned(imul)); + set_ia32_op_type(load, ia32_AddrModeS); + set_ia32_ls_mode(load, get_ia32_ls_mode(imul)); + + set_ia32_am_scale(load, get_ia32_am_scale(imul)); + set_ia32_am_sc(load, get_ia32_am_sc(imul)); + set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul)); + if (is_ia32_am_sc_sign(imul)) + set_ia32_am_sc_sign(load); + if (is_ia32_use_frame(imul)) + set_ia32_use_frame(load); + set_ia32_frame_ent(load, get_ia32_frame_ent(imul)); + + sched_add_before(imul, load); + + mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M); + res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); + + arch_set_irn_register(arch_env, res, reg); + be_peephole_after_exchange(res); + + set_irn_n(imul, n_ia32_IMul_mem, mem); + noreg = get_irn_n(imul, n_ia32_IMul_left); + set_irn_n(imul, n_ia32_IMul_left, res); + set_ia32_op_type(imul, ia32_Normal); +} - /* copy the frame entity (could be set in case of Add */ - /* which was a FrameAddr) */ - set_ia32_frame_ent(res, get_ia32_frame_ent(irn)); +/** + * Replace xorps r,r and xorpd r,r by pxor r,r + */ +static void peephole_ia32_xZero(ir_node *xor) { + set_irn_op(xor, op_ia32_xPzero); +} - if (is_ia32_use_frame(irn)) - set_ia32_use_frame(res); +/** + * Register a peephole optimisation function. + */ +static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) { + assert(op->ops.generic == NULL); + op->ops.generic = (op_func)func; +} - /* set scale */ - set_ia32_am_scale(res, scale); +/* Perform peephole-optimizations. */ +void ia32_peephole_optimization(ia32_code_gen_t *new_cg) +{ + cg = new_cg; + arch_env = cg->arch_env; + + /* register peephole optimisations */ + clear_irp_opcodes_generic_func(); + register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); + register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP); + register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea); + register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test); + register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test); + register_peephole_optimisation(op_be_Return, peephole_ia32_Return); + if (! ia32_cg_config.use_imul_mem_imm32) + register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split); + if (ia32_cg_config.use_pxor) + register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero); + + be_peephole_opt(cg->birg); +} - am_flav = ia32_am_N; - /* determine new am flavour */ - if (offs || offs_cnst || offs_lea) { - am_flav |= ia32_O; - } - if (! be_is_NoReg(cg, base)) { - am_flav |= ia32_B; - } - if (! be_is_NoReg(cg, index)) { - am_flav |= ia32_I; - } - if (scale > 0) { - am_flav |= ia32_S; +/** + * Removes node from schedule if it is not used anymore. If irn is a mode_T node + * all it's Projs are removed as well. + * @param irn The irn to be removed from schedule + */ +static INLINE void try_kill(ir_node *node) +{ + if(get_irn_mode(node) == mode_T) { + const ir_edge_t *edge, *next; + foreach_out_edge_safe(node, edge, next) { + ir_node *proj = get_edge_src_irn(edge); + try_kill(proj); } - set_ia32_am_flavour(res, am_flav); + } - set_ia32_op_type(res, ia32_AddrModeS); + if(get_irn_n_edges(node) != 0) + return; - DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res))); + if (sched_is_scheduled(node)) { + sched_remove(node); + } - /* get the result Proj of the Add/Sub */ - irn = get_res_proj(irn); + be_kill_node(node); +} - assert(irn && "Couldn't find result proj"); +static void optimize_conv_store(ir_node *node) +{ + ir_node *pred; + ir_node *pred_proj; + ir_mode *conv_mode; + ir_mode *store_mode; - /* exchange the old op with the new LEA */ - exchange(irn, res); + if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node)) + return; + + assert(n_ia32_Store_val == n_ia32_Store8Bit_val); + pred_proj = get_irn_n(node, n_ia32_Store_val); + if(is_Proj(pred_proj)) { + pred = get_Proj_pred(pred_proj); + } else { + pred = pred_proj; } + if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) + return; + if(get_ia32_op_type(pred) != ia32_Normal) + return; - return res; + /* the store only stores the lower bits, so we only need the conv + * it it shrinks the mode */ + conv_mode = get_ia32_ls_mode(pred); + store_mode = get_ia32_ls_mode(node); + if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode)) + return; + + set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val)); + if(get_irn_n_edges(pred_proj) == 0) { + be_kill_node(pred_proj); + if(pred != pred_proj) + be_kill_node(pred); + } } -/** - * Optimizes a pattern around irn to address mode if possible. - */ -void ia32_optimize_am(ir_node *irn, void *env) { - ia32_code_gen_t *cg = env; - firm_dbg_module_t *mod = cg->mod; - ir_node *res = irn; - dbg_info *dbg; - ir_mode *mode; - ir_node *block, *noreg_gp, *noreg_fp; - ir_node *left, *right, *temp; - ir_node *store, *load, *mem_proj; - ir_node *succ, *addr_b, *addr_i; - int check_am_src = 0; - - if (! is_ia32_irn(irn)) +static void optimize_load_conv(ir_node *node) +{ + ir_node *pred, *predpred; + ir_mode *load_mode; + ir_mode *conv_mode; + + if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node)) return; - dbg = get_irn_dbg_info(irn); - mode = get_irn_mode(irn); - block = get_nodes_block(irn); - noreg_gp = ia32_new_NoReg_gp(cg); - noreg_fp = ia32_new_NoReg_fp(cg); - - DBG((mod, LEVEL_1, "checking for AM\n")); - - /* 1st part: check for address calculations and transform the into Lea */ - - /* Following cases can occur: */ - /* - Sub (l, imm) -> LEA [base - offset] */ - /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */ - /* - Add (l, imm) -> LEA [base + offset] */ - /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */ - /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */ - /* - Add (l, r) -> LEA [base + index * scale] */ - /* with scale > 1 iff l/r == shl (1,2,3) */ - - if (is_ia32_Sub(irn) || is_ia32_Add(irn)) { - left = get_irn_n(irn, 2); - right = get_irn_n(irn, 3); - - /* Do not try to create a LEA if one of the operands is a Load. */ - /* check is irn is a candidate for address calculation */ - if (is_candidate(block, irn, 1)) { - DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn)); - res = fold_addr(cg, irn, mod, noreg_gp); - - if (res == irn) - DB((mod, LEVEL_1, "transformed into %+F\n", res)); - else - DB((mod, LEVEL_1, "not transformed\n")); - } - } + assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); + pred = get_irn_n(node, n_ia32_Conv_I2I_val); + if(!is_Proj(pred)) + return; + + predpred = get_Proj_pred(pred); + if(!is_ia32_Load(predpred)) + return; - /* 2nd part: fold following patterns: */ - /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */ - /* - Store -> LEA into Store } it might be better to keep the LEA */ - /* - op -> Load into AMop with am_Source */ - /* conditions: */ - /* - op is am_Source capable AND */ - /* - the Load is only used by this op AND */ - /* - the Load is in the same block */ - /* - Store -> op -> Load into AMop with am_Dest */ - /* conditions: */ - /* - op is am_Dest capable AND */ - /* - the Store uses the same address as the Load AND */ - /* - the Load is only used by this op AND */ - /* - the Load and Store are in the same block AND */ - /* - nobody else uses the result of the op */ - - if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) { - /* 1st: check for Load/Store -> LEA */ - if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) { - left = get_irn_n(irn, 0); - - if (is_ia32_Lea(left)) { - DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn)); - - /* get the AM attributes from the LEA */ - add_ia32_am_offs(irn, get_ia32_am_offs(left)); - set_ia32_am_scale(irn, get_ia32_am_scale(left)); - set_ia32_am_flavour(irn, get_ia32_am_flavour(left)); - - set_ia32_am_sc(irn, get_ia32_am_sc(left)); - if (is_ia32_am_sc_sign(left)) - set_ia32_am_sc_sign(irn); - - set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD); - - /* set base and index */ - set_irn_n(irn, 0, get_irn_n(left, 0)); - set_irn_n(irn, 1, get_irn_n(left, 1)); - - /* clear remat flag */ - set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); + /* the load is sign extending the upper bits, so we only need the conv + * if it shrinks the mode */ + load_mode = get_ia32_ls_mode(predpred); + conv_mode = get_ia32_ls_mode(node); + if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode)) + return; + + if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) { + /* change the load if it has only 1 user */ + if(get_irn_n_edges(pred) == 1) { + ir_mode *newmode; + if(get_mode_sign(conv_mode)) { + newmode = find_signed_mode(load_mode); + } else { + newmode = find_unsigned_mode(load_mode); } + assert(newmode != NULL); + set_ia32_ls_mode(predpred, newmode); + } else { + /* otherwise we have to keep the conv */ + return; } - /* check if the node is an address mode candidate */ - else if (is_candidate(block, irn, 0)) { - DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn)); - - left = get_irn_n(irn, 2); - if (get_irn_arity(irn) == 4) { - /* it's an "unary" operation */ - right = left; - } - else { - right = get_irn_n(irn, 3); - } + } - /* normalize commutative ops */ - if (node_is_ia32_comm(irn)) { - /* Assure that right operand is always a Load if there is one */ - /* because non-commutative ops can only use Dest AM if the right */ - /* operand is a load, so we only need to check right operand. */ - if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) - { - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - - temp = left; - left = right; - right = temp; - } - } + /* kill the conv */ + exchange(node, pred); +} - /* check for Store -> op -> Load */ - - /* Store -> op -> Load optimization is only possible if supported by op */ - /* and if right operand is a Load */ - if ((get_ia32_am_support(irn) & ia32_am_Dest) && - pred_is_specific_nodeblock(block, right, is_ia32_Ld)) - { - - /* An address mode capable op always has a result Proj. */ - /* If this Proj is used by more than one other node, we don't need to */ - /* check further, otherwise we check for Store and remember the address, */ - /* the Store points to. */ - - succ = get_res_proj(irn); - assert(succ && "Couldn't find result proj"); - - addr_b = NULL; - addr_i = NULL; - store = NULL; - - /* now check for users and Store */ - if (ia32_get_irn_n_edges(succ) == 1) { - succ = get_edge_src_irn(get_irn_out_edge_first(succ)); - - if (is_ia32_fStore(succ) || is_ia32_Store(succ)) { - store = succ; - addr_b = get_irn_n(store, 0); - - /* Could be that the Store is connected to the address */ - /* calculating LEA while the Load is already transformed. */ - if (is_ia32_Lea(addr_b)) { - succ = addr_b; - addr_b = get_irn_n(succ, 0); - addr_i = get_irn_n(succ, 1); - } - else { - addr_i = noreg_gp; - } - } - } - - if (store) { - /* we found a Store as single user: Now check for Load */ - - /* Extra check for commutative ops with two Loads */ - /* -> put the interesting Load right */ - if (node_is_ia32_comm(irn) && - pred_is_specific_nodeblock(block, left, is_ia32_Ld)) - { - if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) && - (addr_i == get_irn_n(get_Proj_pred(left), 1))) - { - /* We exchange left and right, so it's easier to kill */ - /* the correct Load later and to handle unary operations. */ - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - - temp = left; - left = right; - right = temp; - } - } - - /* skip the Proj for easier access */ - load = get_Proj_pred(right); - - /* Compare Load and Store address */ - if (load_store_addr_is_equal(load, store, addr_b, addr_i)) { - /* Right Load is from same address, so we can */ - /* disconnect the Load and Store here */ - - /* set new base, index and attributes */ - set_irn_n(irn, 0, addr_b); - set_irn_n(irn, 1, addr_i); - add_ia32_am_offs(irn, get_ia32_am_offs(load)); - set_ia32_am_scale(irn, get_ia32_am_scale(load)); - set_ia32_am_flavour(irn, get_ia32_am_flavour(load)); - set_ia32_op_type(irn, ia32_AddrModeD); - set_ia32_frame_ent(irn, get_ia32_frame_ent(load)); - set_ia32_ls_mode(irn, get_ia32_ls_mode(load)); - - set_ia32_am_sc(irn, get_ia32_am_sc(load)); - if (is_ia32_am_sc_sign(load)) - set_ia32_am_sc_sign(irn); - - if (is_ia32_use_frame(load)) - set_ia32_use_frame(irn); - - /* connect to Load memory and disconnect Load */ - if (get_irn_arity(irn) == 5) { - /* binary AMop */ - set_irn_n(irn, 4, get_irn_n(load, 2)); - set_irn_n(irn, 3, noreg_gp); - } - else { - /* unary AMop */ - set_irn_n(irn, 3, get_irn_n(load, 2)); - set_irn_n(irn, 2, noreg_gp); - } - - /* connect the memory Proj of the Store to the op */ - mem_proj = get_mem_proj(store); - set_Proj_pred(mem_proj, irn); - set_Proj_proj(mem_proj, 1); - - /* clear remat flag */ - set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); - - DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store)); - } - } /* if (store) */ - else if (get_ia32_am_support(irn) & ia32_am_Source) { - /* There was no store, check if we still can optimize for source address mode */ - check_am_src = 1; - } - } /* if (support AM Dest) */ - else if (get_ia32_am_support(irn) & ia32_am_Source) { - /* op doesn't support am AM Dest -> check for AM Source */ - check_am_src = 1; - } +static void optimize_conv_conv(ir_node *node) +{ + ir_node *pred_proj, *pred, *result_conv; + ir_mode *pred_mode, *conv_mode; + int conv_mode_bits; + int pred_mode_bits; - /* normalize commutative ops */ - if (node_is_ia32_comm(irn)) { - /* Assure that left operand is always a Load if there is one */ - /* because non-commutative ops can only use Source AM if the */ - /* left operand is a Load, so we only need to check the left */ - /* operand afterwards. */ - if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) { - set_irn_n(irn, 2, right); - set_irn_n(irn, 3, left); - - temp = left; - left = right; - right = temp; - } + if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node)) + return; + + assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val); + pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val); + if(is_Proj(pred_proj)) + pred = get_Proj_pred(pred_proj); + else + pred = pred_proj; + + if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred)) + return; + + /* we know that after a conv, the upper bits are sign extended + * so we only need the 2nd conv if it shrinks the mode */ + conv_mode = get_ia32_ls_mode(node); + conv_mode_bits = get_mode_size_bits(conv_mode); + pred_mode = get_ia32_ls_mode(pred); + pred_mode_bits = get_mode_size_bits(pred_mode); + + if(conv_mode_bits == pred_mode_bits + && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { + result_conv = pred_proj; + } else if(conv_mode_bits <= pred_mode_bits) { + /* if 2nd conv is smaller then first conv, then we can always take the + * 2nd conv */ + if(get_irn_n_edges(pred_proj) == 1) { + result_conv = pred_proj; + set_ia32_ls_mode(pred, conv_mode); + + /* Argh:We must change the opcode to 8bit AND copy the register constraints */ + if (get_mode_size_bits(conv_mode) == 8) { + set_irn_op(pred, op_ia32_Conv_I2I8Bit); + set_ia32_in_req_all(pred, get_ia32_in_req_all(node)); + } + } else { + /* we don't want to end up with 2 loads, so we better do nothing */ + if(get_irn_mode(pred) == mode_T) { + return; } - /* optimize op -> Load iff Load is only used by this op */ - /* and left operand is a Load which only used by this irn */ - if (check_am_src && - pred_is_specific_nodeblock(block, left, is_ia32_Ld) && - (ia32_get_irn_n_edges(left) == 1)) - { - left = get_Proj_pred(left); - - addr_b = get_irn_n(left, 0); - addr_i = get_irn_n(left, 1); - - /* set new base, index and attributes */ - set_irn_n(irn, 0, addr_b); - set_irn_n(irn, 1, addr_i); - add_ia32_am_offs(irn, get_ia32_am_offs(left)); - set_ia32_am_scale(irn, get_ia32_am_scale(left)); - set_ia32_am_flavour(irn, get_ia32_am_flavour(left)); - set_ia32_op_type(irn, ia32_AddrModeS); - set_ia32_frame_ent(irn, get_ia32_frame_ent(left)); - set_ia32_ls_mode(irn, get_ia32_ls_mode(left)); - - set_ia32_am_sc(irn, get_ia32_am_sc(left)); - if (is_ia32_am_sc_sign(left)) - set_ia32_am_sc_sign(irn); - - /* clear remat flag */ - set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable); - - if (is_ia32_use_frame(left)) - set_ia32_use_frame(irn); - - /* connect to Load memory */ - if (get_irn_arity(irn) == 5) { - /* binary AMop */ - set_irn_n(irn, 4, get_irn_n(left, 2)); - } - else { - /* unary AMop */ - set_irn_n(irn, 3, get_irn_n(left, 2)); - } - - /* disconnect from Load */ - set_irn_n(irn, 2, noreg_gp); - - /* If Load has a memory Proj, connect it to the op */ - mem_proj = get_mem_proj(left); - if (mem_proj) { - set_Proj_pred(mem_proj, irn); - set_Proj_proj(mem_proj, 1); - } - - DB((mod, LEVEL_1, "merged with %+F into source AM\n", left)); + result_conv = exact_copy(pred); + set_ia32_ls_mode(result_conv, conv_mode); + + /* Argh:We must change the opcode to 8bit AND copy the register constraints */ + if (get_mode_size_bits(conv_mode) == 8) { + set_irn_op(result_conv, op_ia32_Conv_I2I8Bit); + set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node)); + } + } + } else { + /* if both convs have the same sign, then we can take the smaller one */ + if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) { + result_conv = pred_proj; + } else { + /* no optimisation possible if smaller conv is sign-extend */ + if(mode_is_signed(pred_mode)) { + return; } + /* we can take the smaller conv if it is unsigned */ + result_conv = pred_proj; } } + + /* kill the conv */ + exchange(node, result_conv); + + if(get_irn_n_edges(pred_proj) == 0) { + be_kill_node(pred_proj); + if(pred != pred_proj) + be_kill_node(pred); + } + optimize_conv_conv(result_conv); +} + +static void optimize_node(ir_node *node, void *env) +{ + (void) env; + + optimize_load_conv(node); + optimize_conv_store(node); + optimize_conv_conv(node); +} + +/** + * Performs conv and address mode optimization. + */ +void ia32_optimize_graph(ia32_code_gen_t *cg) +{ + irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg); + + if (cg->dump) + be_dump(cg->irg, "-opt", dump_ir_block_graph_sched); +} + +void ia32_init_optimize(void) +{ + FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize"); }