X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_optimize.c;h=341437cc746e9040403a4f8a540b3aaf17b6021a;hb=2440343b60976b5a7bcc1ef290f7ca693336254b;hp=6760500134a06e0ac7b0a98c3930e8cf5bee4784;hpb=df5a8a477fbf24da76c9f287a7e2115c081b16df;p=libfirm diff --git a/ir/be/ia32/ia32_optimize.c b/ir/be/ia32/ia32_optimize.c index 676050013..341437cc7 100644 --- a/ir/be/ia32/ia32_optimize.c +++ b/ir/be/ia32/ia32_optimize.c @@ -51,6 +51,7 @@ #include "ia32_optimize.h" #include "bearch_ia32_t.h" #include "gen_ia32_regalloc_if.h" +#include "ia32_common_transform.h" #include "ia32_transform.h" #include "ia32_dbg_stat.h" #include "ia32_util.h" @@ -61,98 +62,27 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) static const arch_env_t *arch_env; static ia32_code_gen_t *cg; -static void peephole_IncSP_IncSP(ir_node *node); - -#if 0 -static void peephole_ia32_Store_IncSP_to_push(ir_node *node) -{ - ir_node *base = get_irn_n(node, n_ia32_Store_base); - ir_node *index = get_irn_n(node, n_ia32_Store_index); - ir_node *mem = get_irn_n(node, n_ia32_Store_mem); - ir_node *incsp = base; - ir_node *val; - ir_node *noreg; - ir_graph *irg; - ir_node *block; - dbg_info *dbgi; - ir_mode *mode; - ir_node *push; - ir_node *proj; - int offset; - int node_offset; - - /* nomem inidicates the store doesn't alias with anything else */ - if(!is_NoMem(mem)) - return; - - /* find an IncSP in front of us, we might have to skip barriers for this */ - while(is_Proj(incsp)) { - ir_node *proj_pred = get_Proj_pred(incsp); - if(!be_is_Barrier(proj_pred)) - return; - incsp = get_irn_n(proj_pred, get_Proj_proj(incsp)); - } - if(!be_is_IncSP(incsp)) - return; - - peephole_IncSP_IncSP(incsp); - - /* must be in the same block */ - if(get_nodes_block(incsp) != get_nodes_block(node)) - return; - - if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) { - panic("Invalid storeAM found (%+F)", node); - } - - /* we should be the store to the end of the stackspace */ - offset = be_get_IncSP_offset(incsp); - mode = get_ia32_ls_mode(node); - node_offset = get_ia32_am_offs_int(node); - if(node_offset != offset - get_mode_size_bytes(mode)) - return; - - /* we can use a push instead of the store */ - irg = current_ir_graph; - block = get_nodes_block(node); - dbgi = get_irn_dbg_info(node); - noreg = ia32_new_NoReg_gp(cg); - base = be_get_IncSP_pred(incsp); - val = get_irn_n(node, n_ia32_Store_val); - push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, val, base); - - proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); - - be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode)); - - sched_add_before(node, push); - sched_remove(node); - - be_peephole_before_exchange(node, proj); - exchange(node, proj); - be_peephole_after_exchange(proj); -} - -static void peephole_ia32_Store(ir_node *node) -{ - peephole_ia32_Store_IncSP_to_push(node); -} -#endif - +/** + * Returns non-zero if the given node produces + * a zero flag. + * + * @param node the node to check + * @param pn if >= 0, the projection number of the used result + */ static int produces_zero_flag(ir_node *node, int pn) { ir_node *count; const ia32_immediate_attr_t *imm_attr; - if(!is_ia32_irn(node)) + if (!is_ia32_irn(node)) return 0; - if(pn >= 0) { - if(pn != pn_ia32_res) + if (pn >= 0) { + if (pn != pn_ia32_res) return 0; } - switch(get_ia32_irn_opcode(node)) { + switch (get_ia32_irn_opcode(node)) { case iro_ia32_Add: case iro_ia32_Adc: case iro_ia32_And: @@ -173,20 +103,20 @@ static int produces_zero_flag(ir_node *node, int pn) assert(n_ia32_ShlD_count == n_ia32_ShrD_count); assert(n_ia32_Shl_count == n_ia32_Shr_count && n_ia32_Shl_count == n_ia32_Sar_count); - if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) { + if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) { count = get_irn_n(node, n_ia32_ShlD_count); } else { count = get_irn_n(node, n_ia32_Shl_count); } /* when shift count is zero the flags are not affected, so we can only * do this for constants != 0 */ - if(!is_ia32_Immediate(count)) + if (!is_ia32_Immediate(count)) return 0; imm_attr = get_ia32_immediate_attr_const(count); - if(imm_attr->symconst != NULL) + if (imm_attr->symconst != NULL) return 0; - if((imm_attr->offset & 0x1f) == 0) + if ((imm_attr->offset & 0x1f) == 0) return 0; return 1; @@ -196,6 +126,13 @@ static int produces_zero_flag(ir_node *node, int pn) return 0; } +/** + * If the given node has not mode_T, creates a mode_T version (with a result Proj). + * + * @param node the node to change + * + * @return the new mode_T node (if the mode was changed) or node itself + */ static ir_node *turn_into_mode_t(ir_node *node) { ir_node *block; @@ -218,25 +155,91 @@ static ir_node *turn_into_mode_t(ir_node *node) reg = arch_get_irn_register(arch_env, node); arch_set_irn_register(arch_env, res_proj, reg); - be_peephole_before_exchange(node, res_proj); sched_add_before(node, new_node); - sched_remove(node); - exchange(node, res_proj); - be_peephole_after_exchange(res_proj); - + be_peephole_exchange(node, res_proj); return new_node; } +/** + * Replace Cmp(x, 0) by a Test(x, x) + */ +static void peephole_ia32_Cmp(ir_node *const node) +{ + ir_node *right; + ia32_immediate_attr_t const *imm; + dbg_info *dbgi; + ir_graph *irg; + ir_node *block; + ir_node *noreg; + ir_node *nomem; + ir_node *op; + ia32_attr_t const *attr; + int ins_permuted; + int cmp_unsigned; + ir_node *test; + arch_register_t const *reg; + ir_edge_t const *edge; + ir_edge_t const *tmp; + + if (get_ia32_op_type(node) != ia32_Normal) + return; + + right = get_irn_n(node, n_ia32_Cmp_right); + if (!is_ia32_Immediate(right)) + return; + + imm = get_ia32_immediate_attr_const(right); + if (imm->symconst != NULL || imm->offset != 0) + return; + + dbgi = get_irn_dbg_info(node); + irg = current_ir_graph; + block = get_nodes_block(node); + noreg = ia32_new_NoReg_gp(cg); + nomem = get_irg_no_mem(irg); + op = get_irn_n(node, n_ia32_Cmp_left); + attr = get_irn_generic_attr(node); + ins_permuted = attr->data.ins_permuted; + cmp_unsigned = attr->data.cmp_unsigned; + + if (is_ia32_Cmp(node)) { + test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem, + op, op, ins_permuted, cmp_unsigned); + } else { + test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem, + op, op, ins_permuted, cmp_unsigned); + } + set_ia32_ls_mode(test, get_ia32_ls_mode(node)); + + reg = arch_get_irn_register(arch_env, node); + arch_set_irn_register(arch_env, test, reg); + + foreach_out_edge_safe(node, edge, tmp) { + ir_node *const user = get_edge_src_irn(edge); + + if (is_Proj(user)) + exchange(user, test); + } + + sched_add_before(node, test); + be_peephole_exchange(node, test); +} + +/** + * Peephole optimization for Test instructions. + * We can remove the Test, if a zero flags was produced which is still + * live. + */ static void peephole_ia32_Test(ir_node *node) { - ir_node *left = get_irn_n(node, n_ia32_Test_left); - ir_node *right = get_irn_n(node, n_ia32_Test_right); - ir_node *flags_proj; - ir_node *block; - ir_mode *flags_mode; - int pn = -1; - ir_node *schedpoint; - const ir_edge_t *edge; + ir_node *left = get_irn_n(node, n_ia32_Test_left); + ir_node *right = get_irn_n(node, n_ia32_Test_right); + ir_node *flags_proj; + ir_node *block; + ir_mode *flags_mode; + int pn = -1; + ir_node *schedpoint; + const ir_edge_t *edge; assert(n_ia32_Test_left == n_ia32_Test8Bit_left && n_ia32_Test_right == n_ia32_Test8Bit_right); @@ -291,10 +294,7 @@ static void peephole_ia32_Test(ir_node *node) assert(get_irn_mode(node) != mode_T); - be_peephole_before_exchange(node, flags_proj); - exchange(node, flags_proj); - sched_remove(node); - be_peephole_after_exchange(flags_proj); + be_peephole_exchange(node, flags_proj); } /** @@ -310,20 +310,6 @@ static void peephole_ia32_Return(ir_node *node) { block = get_nodes_block(node); - if (get_Block_n_cfgpreds(block) == 1) { - ir_node *pred = get_Block_cfgpred(block, 0); - - if (is_Jmp(pred)) { - /* The block of the return has only one predecessor, - which jumps directly to this block. - This jump will be encoded as a fall through, so we - ignore it here. - However, the predecessor might be empty, so it must be - ensured that empty blocks are gone away ... */ - return; - } - } - /* check if this return is the first on the block */ sched_foreach_reverse_from(node, irn) { switch (get_irn_opcode(irn)) { @@ -344,109 +330,105 @@ static void peephole_ia32_Return(ir_node *node) { return; } } - /* yep, return is the first real instruction in this block */ -#if 0 - { - /* add an rep prefix to the return */ - ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block); - keep_alive(rep); - sched_add_before(node, rep); - } -#else - /* ensure, that the 3 byte return is generated */ + + /* ensure, that the 3 byte return is generated + * actually the emitter tests again if the block beginning has a label and + * isn't just a fallthrough */ be_Return_set_emit_pop(node, 1); -#endif } /* only optimize up to 48 stores behind IncSPs */ #define MAXPUSH_OPTIMIZE 48 /** - * Tries to create pushs from IncSP,Store combinations. + * Tries to create Push's from IncSP, Store combinations. * The Stores are replaced by Push's, the IncSP is modified * (possibly into IncSP 0, but not removed). */ static void peephole_IncSP_Store_to_push(ir_node *irn) { - int i; - int offset; - ir_node *node; - ir_node *stores[MAXPUSH_OPTIMIZE]; - ir_node *block = get_nodes_block(irn); - ir_graph *irg = cg->irg; - ir_node *curr_sp; - ir_mode *spmode = get_irn_mode(irn); + int i, maxslot, inc_ofs; + ir_node *node; + ir_node *stores[MAXPUSH_OPTIMIZE]; + ir_node *block; + ir_graph *irg; + ir_node *curr_sp; + ir_mode *spmode; memset(stores, 0, sizeof(stores)); assert(be_is_IncSP(irn)); - offset = be_get_IncSP_offset(irn); - if (offset < 4) + inc_ofs = be_get_IncSP_offset(irn); + if (inc_ofs < 4) return; /* * We first walk the schedule after the IncSP node as long as we find - * suitable stores that could be transformed to a push. + * suitable Stores that could be transformed to a Push. * We save them into the stores array which is sorted by the frame offset/4 * attached to the node */ - for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) { + maxslot = -1; + for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) { ir_node *mem; int offset; int storeslot; - // it has to be a store - if(!is_ia32_Store(node)) + /* it has to be a Store */ + if (!is_ia32_Store(node)) break; - // it has to use our sp value - if(get_irn_n(node, n_ia32_base) != irn) + /* it has to use our sp value */ + if (get_irn_n(node, n_ia32_base) != irn) continue; - // store has to be attached to NoMem + /* Store has to be attached to NoMem */ mem = get_irn_n(node, n_ia32_mem); - if(!is_NoMem(mem)) { + if (!is_NoMem(mem)) continue; - } /* unfortunately we can't support the full AMs possible for push at the * moment. TODO: fix this */ - if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index))) + if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index))) break; offset = get_ia32_am_offs_int(node); + /* we should NEVER access uninitialized stack BELOW the current SP */ + assert(offset >= 0); - storeslot = offset / 4; - if(storeslot >= MAXPUSH_OPTIMIZE) - continue; + offset = inc_ofs - 4 - offset; - // storing into the same slot twice is bad (and shouldn't happen...) - if(stores[storeslot] != NULL) + /* storing at half-slots is bad */ + if ((offset & 3) != 0) break; - // storing at half-slots is bad - if(offset % 4 != 0) + if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4) + continue; + storeslot = offset >> 2; + + /* storing into the same slot twice is bad (and shouldn't happen...) */ + if (stores[storeslot] != NULL) break; stores[storeslot] = node; + if (storeslot > maxslot) + maxslot = storeslot; } curr_sp = be_get_IncSP_pred(irn); - // walk the stores in inverse order and create pushs for them - i = (offset / 4) - 1; - if(i >= MAXPUSH_OPTIMIZE) { - i = MAXPUSH_OPTIMIZE - 1; - } - - for( ; i >= 0; --i) { + /* walk through the Stores and create Pushs for them */ + block = get_nodes_block(irn); + spmode = get_irn_mode(irn); + irg = cg->irg; + for (i = 0; i <= maxslot; ++i) { const arch_register_t *spreg; ir_node *push; ir_node *val, *mem, *mem_proj; ir_node *store = stores[i]; ir_node *noreg = ia32_new_NoReg_gp(cg); - if(store == NULL || is_Bad(store)) + if (store == NULL) break; val = get_irn_n(store, n_ia32_unary_op); @@ -457,78 +439,202 @@ static void peephole_IncSP_Store_to_push(ir_node *irn) sched_add_before(irn, push); - // create stackpointer proj + /* create stackpointer Proj */ curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack); arch_set_irn_register(cg->arch_env, curr_sp, spreg); - // create memory proj + /* create memory Proj */ mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M); - // use the memproj now - exchange(store, mem_proj); + /* use the memproj now */ + be_peephole_exchange(store, mem_proj); - // we can remove the store now - sched_remove(store); - - offset -= 4; + inc_ofs -= 4; } - be_set_IncSP_offset(irn, offset); + be_set_IncSP_offset(irn, inc_ofs); be_set_IncSP_pred(irn, curr_sp); } /** - * Tries to optimize two following IncSP. + * Return true if a mode can be stored in the GP register set + */ +static INLINE int mode_needs_gp_reg(ir_mode *mode) { + if (mode == mode_fpcw) + return 0; + if (get_mode_size_bits(mode) > 32) + return 0; + return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b; +} + +/** + * Tries to create Pops from Load, IncSP combinations. + * The Loads are replaced by Pops, the IncSP is modified + * (possibly into IncSP 0, but not removed). */ -static void peephole_IncSP_IncSP(ir_node *node) +static void peephole_Load_IncSP_to_pop(ir_node *irn) { - int pred_offs; - int curr_offs; - int offs; - ir_node *pred = be_get_IncSP_pred(node); - ir_node *predpred; + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + int i, maxslot, inc_ofs, ofs; + ir_node *node, *pred_sp, *block; + ir_node *loads[MAXPUSH_OPTIMIZE]; + ir_graph *irg; + unsigned regmask = 0; + unsigned copymask = ~0; - if(!be_is_IncSP(pred)) - return; + memset(loads, 0, sizeof(loads)); + assert(be_is_IncSP(irn)); - if(get_irn_n_edges(pred) > 1) + inc_ofs = -be_get_IncSP_offset(irn); + if (inc_ofs < 4) return; - pred_offs = be_get_IncSP_offset(pred); - curr_offs = be_get_IncSP_offset(node); + /* + * We first walk the schedule before the IncSP node as long as we find + * suitable Loads that could be transformed to a Pop. + * We save them into the stores array which is sorted by the frame offset/4 + * attached to the node + */ + maxslot = -1; + pred_sp = be_get_IncSP_pred(irn); + for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) { + ir_node *mem; + int offset; + int loadslot; + const arch_register_t *sreg, *dreg; + + /* it has to be a Load */ + if (!is_ia32_Load(node)) { + if (be_is_Copy(node)) { + if (!mode_needs_gp_reg(get_irn_mode(node))) { + /* not a GP copy, ignore */ + continue; + } + dreg = arch_get_irn_register(arch_env, node); + sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node)); + if (regmask & copymask & (1 << sreg->index)) { + break; + } + if (regmask & copymask & (1 << dreg->index)) { + break; + } + /* we CAN skip Copies if neither the destination nor the source + * is not in our regmask, ie none of our future Pop will overwrite it */ + regmask |= (1 << dreg->index) | (1 << sreg->index); + copymask &= ~((1 << dreg->index) | (1 << sreg->index)); + continue; + } + break; + } - if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) { - if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) { - return; + /* we can handle only GP loads */ + if (!mode_needs_gp_reg(get_ia32_ls_mode(node))) + continue; + + /* it has to use our predecessor sp value */ + if (get_irn_n(node, n_ia32_base) != pred_sp) { + /* it would be ok if this load does not use a Pop result, + * but we do not check this */ + break; } - offs = 0; - } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) { - if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) { - return; + /* Load has to be attached to Spill-Mem */ + mem = skip_Proj(get_irn_n(node, n_ia32_mem)); + if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem)) + break; + + /* should have NO index */ + if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index))) + break; + + offset = get_ia32_am_offs_int(node); + /* we should NEVER access uninitialized stack BELOW the current SP */ + assert(offset >= 0); + + /* storing at half-slots is bad */ + if ((offset & 3) != 0) + break; + + if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4) + continue; + /* ignore those outside the possible windows */ + if (offset > inc_ofs - 4) + continue; + loadslot = offset >> 2; + + /* loading from the same slot twice is bad (and shouldn't happen...) */ + if (loads[loadslot] != NULL) + break; + + dreg = arch_get_irn_register(arch_env, node); + if (regmask & (1 << dreg->index)) { + /* this register is already used */ + break; } - offs = 0; - } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND - || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) { + regmask |= 1 << dreg->index; + + loads[loadslot] = node; + if (loadslot > maxslot) + maxslot = loadslot; + } + + if (maxslot < 0) return; - } else { - offs = curr_offs + pred_offs; + + /* find the first slot */ + for (i = maxslot; i >= 0; --i) { + ir_node *load = loads[i]; + + if (load == NULL) + break; + } + + ofs = inc_ofs - (maxslot + 1) * 4; + inc_ofs = (i+1) * 4; + + /* create a new IncSP if needed */ + block = get_nodes_block(irn); + irg = cg->irg; + if (inc_ofs > 0) { + pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn)); + sched_add_before(irn, pred_sp); } - /* add pred offset to ours and remove pred IncSP */ - be_set_IncSP_offset(node, offs); + /* walk through the Loads and create Pops for them */ + for (++i; i <= maxslot; ++i) { + ir_node *load = loads[i]; + ir_node *mem, *pop; + const ir_edge_t *edge, *tmp; + const arch_register_t *reg; - predpred = be_get_IncSP_pred(pred); - be_peephole_before_exchange(pred, predpred); + mem = get_irn_n(load, n_ia32_mem); + reg = arch_get_irn_register(arch_env, load); - /* rewire dependency edges */ - edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph); - be_set_IncSP_pred(node, predpred); - sched_remove(pred); - be_kill_node(pred); + pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp); + arch_set_irn_register(arch_env, pop, reg); - be_peephole_after_exchange(predpred); + /* create stackpointer Proj */ + pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); + arch_set_irn_register(arch_env, pred_sp, esp); + + sched_add_before(irn, pop); + + /* rewire now */ + foreach_out_edge_safe(load, edge, tmp) { + ir_node *proj = get_edge_src_irn(edge); + + set_Proj_pred(proj, pop); + } + + /* we can remove the Load now */ + sched_remove(load); + kill_node(load); + } + + be_set_IncSP_offset(irn, -ofs); + be_set_IncSP_pred(irn, pred_sp); } + /** * Find a free GP register if possible, else return NULL. */ @@ -548,9 +654,21 @@ static const arch_register_t *get_free_gp_reg(void) return NULL; } +/** + * Creates a Pop instruction before the given schedule point. + * + * @param dbgi debug info + * @param irg the graph + * @param block the block + * @param stack the previous stack value + * @param schedpoint the new node is added before this node + * @param reg the register to pop + * + * @return the new stack value + */ static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *stack, ir_node *schedpoint, - const arch_register_t *free_reg) + const arch_register_t *reg) { const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; ir_node *pop; @@ -563,7 +681,7 @@ static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack); arch_set_irn_register(arch_env, stack, esp); val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res); - arch_set_irn_register(arch_env, val, free_reg); + arch_set_irn_register(arch_env, val, reg); sched_add_before(schedpoint, pop); @@ -574,6 +692,38 @@ static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block, return stack; } +/** + * Creates a Push instruction before the given schedule point. + * + * @param dbgi debug info + * @param irg the graph + * @param block the block + * @param stack the previous stack value + * @param schedpoint the new node is added before this node + * @param reg the register to pop + * + * @return the new stack value + */ +static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block, + ir_node *stack, ir_node *schedpoint) +{ + const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; + + ir_node *val = ia32_new_Unknown_gp(cg); + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *nomem = get_irg_no_mem(irg); + ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack); + sched_add_before(schedpoint, push); + + stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack); + arch_set_irn_register(arch_env, stack, esp); + + return stack; +} + +/** + * Optimize an IncSp by replacing it with Push/Pop. + */ static void peephole_be_IncSP(ir_node *node) { const arch_register_t *esp = &ia32_gp_regs[REG_ESP]; @@ -585,11 +735,14 @@ static void peephole_be_IncSP(ir_node *node) int offset; /* first optimize incsp->incsp combinations */ - peephole_IncSP_IncSP(node); + node = be_peephole_IncSP_IncSP(node); /* transform IncSP->Store combinations to Push where possible */ peephole_IncSP_Store_to_push(node); + /* transform Load->IncSP combinations to Pop where possible */ + peephole_Load_IncSP_to_pop(node); + if (arch_get_irn_register(arch_env, node) != esp) return; @@ -604,7 +757,7 @@ static void peephole_be_IncSP(ir_node *node) if (offset < 0) { /* we need a free register for pop */ reg = get_free_gp_reg(); - if(reg == NULL) + if (reg == NULL) return; dbgi = get_irn_dbg_info(node); @@ -617,14 +770,17 @@ static void peephole_be_IncSP(ir_node *node) stack = create_pop(dbgi, irg, block, stack, node, reg); } } else { - /* NIY: create pushs */ - return; + dbgi = get_irn_dbg_info(node); + block = get_nodes_block(node); + stack = be_get_IncSP_pred(node); + stack = create_push(dbgi, irg, block, stack, node); + + if (offset == +8) { + stack = create_push(dbgi, irg, block, stack, node); + } } - be_peephole_before_exchange(node, stack); - sched_remove(node); - exchange(node, stack); - be_peephole_after_exchange(stack); + be_peephole_exchange(node, stack); } /** @@ -667,10 +823,7 @@ static void peephole_ia32_Const(ir_node *node) sched_add_before(node, produceval); sched_add_before(node, xor); - be_peephole_before_exchange(node, xor); - exchange(node, xor); - sched_remove(node); - be_peephole_after_exchange(xor); + be_peephole_exchange(node, xor); } static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node) @@ -875,11 +1028,8 @@ exchange: DBG_OPT_LEA2ADD(node, res); /* exchange the Add and the LEA */ - be_peephole_before_exchange(node, res); sched_add_before(node, res); - sched_remove(node); - exchange(node, res); - be_peephole_after_exchange(res); + be_peephole_exchange(node, res); } /** @@ -930,7 +1080,7 @@ static void peephole_ia32_Imul_split(ir_node *imul) { res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); arch_set_irn_register(arch_env, res, reg); - be_peephole_after_exchange(res); + be_peephole_new_node(res); set_irn_n(imul, n_ia32_IMul_mem, mem); noreg = get_irn_n(imul, n_ia32_IMul_left); @@ -961,13 +1111,14 @@ void ia32_peephole_optimization(ia32_code_gen_t *new_cg) /* register peephole optimisations */ clear_irp_opcodes_generic_func(); - register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); - //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store); - register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP); - register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea); - register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test); + register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const); + register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP); + register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea); + register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp); + register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp); + register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test); register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test); - register_peephole_optimisation(op_be_Return, peephole_ia32_Return); + register_peephole_optimisation(op_be_Return, peephole_ia32_Return); if (! ia32_cg_config.use_imul_mem_imm32) register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split); if (ia32_cg_config.use_pxor) @@ -998,7 +1149,7 @@ static INLINE void try_kill(ir_node *node) sched_remove(node); } - be_kill_node(node); + kill_node(node); } static void optimize_conv_store(ir_node *node) @@ -1032,9 +1183,9 @@ static void optimize_conv_store(ir_node *node) set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val)); if(get_irn_n_edges(pred_proj) == 0) { - be_kill_node(pred_proj); + kill_node(pred_proj); if(pred != pred_proj) - be_kill_node(pred); + kill_node(pred); } } @@ -1159,9 +1310,9 @@ static void optimize_conv_conv(ir_node *node) exchange(node, result_conv); if(get_irn_n_edges(pred_proj) == 0) { - be_kill_node(pred_proj); + kill_node(pred_proj); if(pred != pred_proj) - be_kill_node(pred); + kill_node(pred); } optimize_conv_conv(result_conv); }