X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_nodes_attr.h;h=9dcf9ad3c2208a0ff3ba0196a16b91385e880052;hb=fef8dc3eff6468d7d65485af8e1ac9884c504e1a;hp=1e8844e8e1cb3dda3ebe619c371a3f249756d295;hpb=01e23d45af0fae4eb29b0909294728eefbfd5f41;p=libfirm diff --git a/ir/be/ia32/ia32_nodes_attr.h b/ir/be/ia32/ia32_nodes_attr.h index 1e8844e8e..9dcf9ad3c 100644 --- a/ir/be/ia32/ia32_nodes_attr.h +++ b/ir/be/ia32/ia32_nodes_attr.h @@ -21,14 +21,12 @@ * @file * @brief Type definitions for ia32 node attributes. * @author Christian Wuerdig - * @version $Id$ */ #ifndef FIRM_BE_IA32_IA32_NODES_ATTR_H #define FIRM_BE_IA32_IA32_NODES_ATTR_H #include "firm_types.h" #include "bearch.h" -#include "bemachine.h" #include "irnode_t.h" /** ia32 condition codes (the numbers correspond to the real encoding order) */ @@ -133,19 +131,26 @@ typedef enum { match_8bit_am = 1 << 3, /**< node supports 8bit source AM */ match_16bit_am = 1 << 4, /**< node supports 16bit source AM */ match_immediate = 1 << 5, /**< node supports immediates */ - match_mode_neutral = 1 << 6, /**< 16 and 8 bit modes can be emulated - by 32 bit operations */ - match_try_am = 1 << 7, /**< only try to produce AM node, don't + /** for 8/16 bit modes, mode_neutral operations can be emulated by their + * 32bit equivalents, they just don't care about the upper bits (they can be + * arbitrary before the insn and are unknown after the instruction). */ + match_mode_neutral = 1 << 6, + /** for 8/16 bit modes, zero_ext operations can be emulated by their + * 32bit equivalents, however the upper bits must be zero extended. */ + match_zero_ext = 1 << 7, + /** for 8/16 bit modes, upconv operations can be emulated by their + * 32bit equivalents, however the upper bits have to sign/zero extended + * based on the operations mode. */ + match_upconv = 1 << 8, + match_try_am = 1 << 9, /**< only try to produce AM node, don't do anything if AM isn't possible */ - match_two_users = 1 << 8, /**< the instruction uses a load two times ... */ - match_upconv_32 = 1 << 9 /**< 8/16 bit insn are processed by doing - an upconv to 32bit */ + match_two_users = 1 << 10,/**< the instruction uses a load two times ... */ } match_flags_t; ENUM_BITSET(match_flags_t) typedef struct ia32_op_attr_t ia32_op_attr_t; struct ia32_op_attr_t { - match_flags_t flags; + //match_flags_t flags; unsigned latency; }; @@ -201,8 +206,6 @@ struct ia32_attr_t { ir_entity *frame_ent; /**< the frame entity attached to this node */ - const be_execution_unit_t ***exec_units; /**< list of units this operation can be executed on */ - ir_label_t exc_label; /**< the exception label iff this instruction can throw an exception */ #ifndef NDEBUG @@ -235,9 +238,9 @@ struct ia32_condcode_attr_t { */ typedef struct ia32_switch_attr_t ia32_switch_attr_t; struct ia32_switch_attr_t { - ia32_attr_t attr; /**< generic attribute */ - long default_pn; - ir_entity *jump_table; + ia32_attr_t attr; /**< generic attribute */ + const ir_switch_table *table; + ir_entity *jump_table; }; /** @@ -266,8 +269,10 @@ struct ia32_immediate_attr_t { */ typedef struct ia32_x87_attr_t ia32_x87_attr_t; struct ia32_x87_attr_t { - ia32_attr_t attr; /**< the generic attribute */ - const arch_register_t *x87[3]; /**< register slots for x87 register */ + ia32_attr_t attr; /**< the generic attribute */ + arch_register_t const *reg; /**< The explicit register operand. */ + bool res_in_reg; /**< True if the result is in the explicit register operand, %st0 otherwise. */ + bool pop; /**< Emit a pop suffix. */ }; typedef struct ia32_asm_reg_t ia32_asm_reg_t; @@ -286,7 +291,7 @@ struct ia32_asm_reg_t { */ typedef struct ia32_asm_attr_t ia32_asm_attr_t; struct ia32_asm_attr_t { - ia32_x87_attr_t x87_attr; + ia32_attr_t attr; /**< the generic attribute */ ident *asm_text; const ia32_asm_reg_t *register_map; };