X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_new_nodes.c;h=fe8656af4ececdcbcfeb614d81692e624c5076dc;hb=6f3d0fd6339e2fce9daca84797eb893af0a3d467;hp=2a986a2199d0be25d8e473fde58d1828442738ce;hpb=fb7af51c8208febc6950d62d12a9c5de82014f8e;p=libfirm

diff --git a/ir/be/ia32/ia32_new_nodes.c b/ir/be/ia32/ia32_new_nodes.c
index 2a986a219..fe8656af4 100644
--- a/ir/be/ia32/ia32_new_nodes.c
+++ b/ir/be/ia32/ia32_new_nodes.c
@@ -35,6 +35,7 @@
 #include "ia32_nodes_attr.h"
 #include "ia32_new_nodes.h"
 #include "gen_ia32_regalloc_if.h"
+#include "gen_ia32_machine.h"
 
 /**
  * Returns the ident of a SymConst.
@@ -69,7 +70,13 @@ static ident *get_sc_ident(ir_node *symc) {
 	return NULL;
 }
 
-
+/**
+ * returns true if a node has x87 registers
+ */
+int ia32_has_x87_register(const ir_node *n) {
+	assert(is_ia32_irn(n) && "Need ia32 node.");
+	return is_irn_machine_user(n, 0);
+}
 
 /***********************************************************************************
  *      _                                   _       _             __
@@ -225,7 +232,15 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
 			slots = get_ia32_slots(n);
 			if (slots && n_res > 0) {
 				for (i = 0; i < n_res; i++) {
-					fprintf(F, "reg #%d = %s\n", i, slots[i] ? slots[i]->name : "n/a");
+					const arch_register_t *reg;
+
+					/* retrieve "real" x87 register */
+					if (ia32_has_x87_register(n))
+						reg = get_ia32_attr(n)->x87[i + 2];
+					else
+						reg = slots[i];
+
+					fprintf(F, "reg #%d = %s\n", i, reg ? arch_register_get_name(reg) : "n/a");
 				}
 				fprintf(F, "\n");
 			}
@@ -544,7 +559,7 @@ char *get_ia32_am_offs(const ir_node *node) {
 	ia32_attr_t *attr = get_ia32_attr(node);
 	static char res[64];
 
-	snprintf(res, sizeof(res), "%+ld", attr->am_offs);
+	snprintf(res, sizeof(res), "%+d", attr->am_offs);
 
 	return res;
 }
@@ -552,7 +567,7 @@ char *get_ia32_am_offs(const ir_node *node) {
 /**
  * Gets the addressmode offset as long.
  */
-long get_ia32_am_offs_long(const ir_node *node) {
+int get_ia32_am_offs_int(const ir_node *node) {
 	ia32_attr_t *attr = get_ia32_attr(node);
 	return attr->am_offs;
 }
@@ -564,10 +579,13 @@ static void extend_ia32_am_offs(ir_node *node, char *offset, char op) {
 	ia32_attr_t *attr = get_ia32_attr(node);
 	int res, o;
 
-	if (! offset || strlen(offset) < 1)
+	if (offset == NULL || offset[0] == '\0')
 		return;
 
-	res = sscanf(offset, "%d", &o);
+	if (offset[0] == '-')
+		res = sscanf(offset, "%d", &o);
+	else
+		res = sscanf(offset, "%u", &o);
 	assert(res == 1);
 
 	if (op == '-')
@@ -585,6 +603,11 @@ void add_ia32_am_offs(ir_node *node, const char *offset) {
 	extend_ia32_am_offs(node, (char *)offset, '+');
 }
 
+void add_ia32_am_offs_int(ir_node *node, int offset) {
+	ia32_attr_t *attr = get_ia32_attr(node);
+	attr->am_offs += offset;
+}
+
 /**
  * Sub an offset for addrmode.
  */
@@ -954,7 +977,7 @@ void set_ia32_out_req_all(ir_node *node, const ia32_register_req_t **reqs) {
  */
 const ia32_register_req_t *get_ia32_in_req(const ir_node *node, int pos) {
 	ia32_attr_t *attr = get_ia32_attr(node);
-	return attr->in_req[pos];
+	return attr->in_req != NULL ? attr->in_req[pos] : NULL;
 }
 
 /**
@@ -962,7 +985,7 @@ const ia32_register_req_t *get_ia32_in_req(const ir_node *node, int pos) {
  */
 const ia32_register_req_t *get_ia32_out_req(const ir_node *node, int pos) {
 	ia32_attr_t *attr = get_ia32_attr(node);
-	return attr->out_req[pos];
+	return attr->out_req != NULL ? attr->out_req[pos] : NULL;
 }
 
 /**
@@ -1053,6 +1076,31 @@ void set_ia32_pncode(ir_node *node, long code) {
 	attr->pn_code     = code;
 }
 
+/**
+ * Sets the flags for the n'th out.
+ */
+void set_ia32_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) {
+	ia32_attr_t *attr = get_ia32_attr(node);
+	assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
+	attr->out_flags[pos] = flags;
+}
+
+/**
+ * Gets the flags for the n'th out.
+ */
+arch_irn_flags_t get_ia32_out_flags(const ir_node *node, int pos) {
+	ia32_attr_t *attr = get_ia32_attr(node);
+	return pos < (int)attr->data.n_res ? attr->out_flags[pos] : arch_irn_flags_none;
+}
+
+/**
+ * Get the list of available execution units.
+ */
+const be_execution_unit_t ***get_ia32_exec_units(const ir_node *node) {
+	ia32_attr_t *attr = get_ia32_attr(node);
+	return attr->exec_units;
+}
+
 #ifndef NDEBUG
 
 /**
@@ -1240,21 +1288,24 @@ int is_ia32_AddrModeD(const ir_node *node) {
  * Checks if node is a Load or xLoad/vfLoad.
  */
 int is_ia32_Ld(const ir_node *node) {
-	return is_ia32_Load(node) || is_ia32_xLoad(node) || is_ia32_vfld(node) || is_ia32_fld(node);
+	int op = get_ia32_irn_opcode(node);
+	return op == iro_ia32_Load || op == iro_ia32_xLoad || op == iro_ia32_vfld || op == iro_ia32_fld;
 }
 
 /**
  * Checks if node is a Store or xStore/vfStore.
  */
 int is_ia32_St(const ir_node *node) {
-	return is_ia32_Store(node) || is_ia32_xStore(node) || is_ia32_vfst(node) || is_ia32_fst(node) || is_ia32_fstp(node);
+	int op = get_ia32_irn_opcode(node);
+	return op == iro_ia32_Store || op == iro_ia32_xStore || op == iro_ia32_vfst || op == iro_ia32_fst || op == iro_ia32_fstp;
 }
 
 /**
  * Checks if node is a Const or xConst/vfConst.
  */
 int is_ia32_Cnst(const ir_node *node) {
-	return is_ia32_Const(node) || is_ia32_xConst(node) || is_ia32_vfConst(node);
+	int op = get_ia32_irn_opcode(node);
+	return op == iro_ia32_Const || op == iro_ia32_xConst || op == iro_ia32_vfConst;
 }
 
 /**
@@ -1263,7 +1314,6 @@ int is_ia32_Cnst(const ir_node *node) {
 const char *get_ia32_out_reg_name(const ir_node *node, int pos) {
 	ia32_attr_t *attr = get_ia32_attr(node);
 
-	assert(is_ia32_irn(node) && "Not an ia32 node.");
 	assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
 	assert(attr->slots[pos]  && "No register assigned");
 
@@ -1276,7 +1326,6 @@ const char *get_ia32_out_reg_name(const ir_node *node, int pos) {
 int get_ia32_out_regnr(const ir_node *node, int pos) {
 	ia32_attr_t *attr = get_ia32_attr(node);
 
-	assert(is_ia32_irn(node) && "Not an ia32 node.");
 	assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
 	assert(attr->slots[pos]  && "No register assigned");
 
@@ -1289,7 +1338,6 @@ int get_ia32_out_regnr(const ir_node *node, int pos) {
 const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) {
 	ia32_attr_t *attr = get_ia32_attr(node);
 
-	assert(is_ia32_irn(node) && "Not an ia32 node.");
 	assert(pos < (int) attr->data.n_res && "Invalid OUT position.");
 	assert(attr->slots[pos]  && "No register assigned");
 
@@ -1300,15 +1348,22 @@ const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) {
  * Initializes the nodes attributes.
  */
 void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const ia32_register_req_t **in_reqs,
-						  const ia32_register_req_t **out_reqs, int n_res, unsigned latency)
+						  const ia32_register_req_t **out_reqs, const be_execution_unit_t ***execution_units,
+						  int n_res, unsigned latency)
 {
 	ia32_attr_t *attr = get_ia32_attr(node);
+
 	set_ia32_flags(node, flags);
 	set_ia32_in_req_all(node, in_reqs);
 	set_ia32_out_req_all(node, out_reqs);
 	set_ia32_latency(node, latency);
+	set_ia32_n_res(node, n_res);
+
+	attr->exec_units = execution_units;
+
+	attr->out_flags = NEW_ARR_D(int, get_irg_obstack(get_irn_irg(node)), n_res);
+	memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0]));
 
-	attr->data.n_res = n_res;
 	memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));
 }