X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_new_nodes.c;h=e509b2179dec110ed5b3eeff196c04c3c46e57eb;hb=a1a465eb2b3f54027b29f829423fffd0396937f4;hp=62b768459c1b816de6c16cc2aae764acb316a3db;hpb=0b549402871c767d671de5c9736b8463c8c5f9a9;p=libfirm diff --git a/ir/be/ia32/ia32_new_nodes.c b/ir/be/ia32/ia32_new_nodes.c index 62b768459..e509b2179 100644 --- a/ir/be/ia32/ia32_new_nodes.c +++ b/ir/be/ia32/ia32_new_nodes.c @@ -42,14 +42,25 @@ * @return The ident of the SymConst */ static ident *get_sc_ident(ir_node *symc) { - assert(get_irn_opcode(symc) == iro_SymConst && "need symconst to get ident"); + entity *ent; + ir_type *owner; + ident *id; switch (get_SymConst_kind(symc)) { case symconst_addr_name: return get_SymConst_name(symc); case symconst_addr_ent: - return get_entity_ld_ident(get_SymConst_entity(symc)); + ent = get_SymConst_entity(symc); + owner = get_entity_owner(ent); + id = get_entity_ld_ident(ent); + if (owner == get_tls_type()) { + if (get_entity_visibility(ent) == visibility_external_allocated) + id = mangle(id, new_id_from_chars("@INDNTPOFF", 10)); + else + id = mangle(id, new_id_from_chars("@NTPOFF", 7)); + } + return id; default: assert(0 && "Unsupported SymConst"); @@ -58,7 +69,13 @@ static ident *get_sc_ident(ir_node *symc) { return NULL; } - +/** + * returns true if a node has x87 registers + */ +int ia32_has_x87_register(const ir_node *n) { + assert(is_ia32_irn(n) && "Need ia32 node."); + return is_irn_machine_user(n, 0); +} /*********************************************************************************** * _ _ _ __ @@ -214,7 +231,15 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { slots = get_ia32_slots(n); if (slots && n_res > 0) { for (i = 0; i < n_res; i++) { - fprintf(F, "reg #%d = %s\n", i, slots[i] ? slots[i]->name : "n/a"); + const arch_register_t *reg; + + /* retrieve "real" x87 register */ + if (ia32_has_x87_register(n)) + reg = get_ia32_attr(n)->x87[i + 2]; + else + reg = slots[i]; + + fprintf(F, "reg #%d = %s\n", i, reg ? arch_register_get_name(reg) : "n/a"); } fprintf(F, "\n"); } @@ -243,6 +268,23 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { } fprintf(F, "\n"); + /* dump immop type */ + fprintf(F, "immediate = "); + switch (get_ia32_immop_type(n)) { + case ia32_ImmNone: + fprintf(F, "None"); + break; + case ia32_ImmConst: + fprintf(F, "Const"); + break; + case ia32_ImmSymConst: + fprintf(F, "SymConst"); + break; + default: + fprintf(F, "unknown (%d)", get_ia32_immop_type(n)); + break; + } + fprintf(F, "\n"); /* dump supported am */ fprintf(F, "AM support = "); @@ -312,6 +354,18 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { /* commutative */ fprintf(F, "commutative = %d\n", is_ia32_commutative(n)); + /* emit cl */ + fprintf(F, "emit cl instead of ecx = %d\n", is_ia32_emit_cl(n)); + + /* got lea */ + fprintf(F, "got loea = %d\n", is_ia32_got_lea(n)); + + /* got reload */ + fprintf(F, "got reload = %d\n", is_ia32_got_reload(n)); + + /* dump latency */ + fprintf(F, "latency = %d\n", get_ia32_latency(n)); + /* dump flags */ fprintf(F, "flags ="); flags = get_ia32_flags(n); @@ -328,6 +382,9 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { if (flags & arch_irn_flags_ignore) { fprintf(F, " ignore"); } + if (flags & arch_irn_flags_modify_sp) { + fprintf(F, " modify_sp"); + } } fprintf(F, " (%d)\n", flags); @@ -341,6 +398,43 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { } fprintf(F, "\n"); + /* dump modes */ + fprintf(F, "ls_mode = "); + if (get_ia32_ls_mode(n)) { + ir_fprintf(F, "%+F", get_ia32_ls_mode(n)); + } + else { + fprintf(F, "n/a"); + } + fprintf(F, "\n"); + + fprintf(F, "res_mode = "); + if (get_ia32_res_mode(n)) { + ir_fprintf(F, "%+F", get_ia32_res_mode(n)); + } + else { + fprintf(F, "n/a"); + } + fprintf(F, "\n"); + + fprintf(F, "src_mode = "); + if (get_ia32_src_mode(n)) { + ir_fprintf(F, "%+F", get_ia32_src_mode(n)); + } + else { + fprintf(F, "n/a"); + } + fprintf(F, "\n"); + + fprintf(F, "tgt_mode = "); + if (get_ia32_tgt_mode(n)) { + ir_fprintf(F, "%+F", get_ia32_tgt_mode(n)); + } + else { + fprintf(F, "n/a"); + } + fprintf(F, "\n"); + #ifndef NDEBUG /* dump original ir node name */ fprintf(F, "orig node = "); @@ -462,64 +556,43 @@ void set_ia32_am_flavour(ir_node *node, ia32_am_flavour_t am_flavour) { */ char *get_ia32_am_offs(const ir_node *node) { ia32_attr_t *attr = get_ia32_attr(node); - char *res = NULL; - int size; - - if (! attr->am_offs) { - return NULL; - } - - if (! attr->plain_offs) - attr->plain_offs = (struct obstack *)_new_arr_d(get_irg_obstack(get_irn_irg(node)), 1, sizeof(*(attr->plain_offs))); - else - obstack_free(attr->plain_offs, NULL); + static char res[64]; - obstack_init(attr->plain_offs); - - size = obstack_object_size(attr->am_offs); - if (size > 0) { - res = obstack_alloc(attr->plain_offs, size + 2); - res[0] = attr->data.offs_sign ? '-' : '+'; - memcpy(&res[1], obstack_base(attr->am_offs), size); - res[size + 1] = '\0'; - } + snprintf(res, sizeof(res), "%+d", attr->am_offs); return res; } +/** + * Gets the addressmode offset as long. + */ +int get_ia32_am_offs_int(const ir_node *node) { + ia32_attr_t *attr = get_ia32_attr(node); + return attr->am_offs; +} + /** * Add an offset for addrmode. */ static void extend_ia32_am_offs(ir_node *node, char *offset, char op) { ia32_attr_t *attr = get_ia32_attr(node); + int res, o; - if (! offset || strlen(offset) < 1) + if (offset == NULL || offset[0] == '\0') return; - /* offset could already have an explicit sign */ - /* -> supersede op if necessary */ - if (offset[0] == '-' || offset[0] == '+') { - if (offset[0] == '-') { - op = (op == '-') ? '+' : '-'; - } - - /* skip explicit sign */ - offset++; - } - - if (! attr->am_offs) { - /* obstack is not initialized */ - attr->am_offs = (struct obstack *)_new_arr_d(get_irg_obstack(get_irn_irg(node)), 1, sizeof(*(attr->am_offs))); - obstack_init(attr->am_offs); - - attr->data.offs_sign = (op == '-') ? 1 : 0; - } - else { - /* If obstack is initialized, connect the new offset with op */ - obstack_printf(attr->am_offs, "%c", op); - } + if (offset[0] == '-') + res = sscanf(offset, "%d", &o); + else + res = sscanf(offset, "%u", &o); + assert(res == 1); - obstack_printf(attr->am_offs, "%s", offset); + if (op == '-') + attr->am_offs -= o; + else if (op == '+') + attr->am_offs += o; + else + assert(0); } /** @@ -529,6 +602,11 @@ void add_ia32_am_offs(ir_node *node, const char *offset) { extend_ia32_am_offs(node, (char *)offset, '+'); } +void add_ia32_am_offs_int(ir_node *node, int offset) { + ia32_attr_t *attr = get_ia32_attr(node); + attr->am_offs += offset; +} + /** * Sub an offset for addrmode. */ @@ -609,23 +687,6 @@ void set_ia32_Immop_tarval(ir_node *node, tarval *tv) { attr->cnst = get_ident_for_tv(tv); } -/** - * Return the sc attribute. - */ -ident *get_ia32_sc(const ir_node *node) { - ia32_attr_t *attr = get_ia32_attr(node); - return attr->cnst_val.sc; -} - -/** - * Sets the sc attribute. - */ -void set_ia32_sc(ir_node *node, ident *sc) { - ia32_attr_t *attr = get_ia32_attr(node); - attr->cnst_val.sc = sc; - attr->cnst = attr->cnst_val.sc; -} - /** * Gets the string representation of the internal const (tv or symconst) */ @@ -639,7 +700,7 @@ const char *get_ia32_cnst(const ir_node *node) { /** * Sets the string representation of the internal const. */ -void set_ia32_cnst(ir_node *node, char *cnst) { +void set_ia32_cnst(ir_node *node, const char *cnst) { ia32_attr_t *attr = get_ia32_attr(node); attr->cnst = new_id_from_str(cnst); } @@ -861,6 +922,23 @@ void set_ia32_frame_ent(ir_node *node, entity *ent) { set_ia32_use_frame(node); } + +/** + * Gets the instruction latency. + */ +unsigned get_ia32_latency(const ir_node *node) { + ia32_attr_t *attr = get_ia32_attr(node); + return attr->latency; +} + +/** +* Sets the instruction latency. +*/ +void set_ia32_latency(ir_node *node, unsigned latency) { + ia32_attr_t *attr = get_ia32_attr(node); + attr->latency = latency; +} + /** * Returns the argument register requirements of an ia32 node. */ @@ -898,7 +976,7 @@ void set_ia32_out_req_all(ir_node *node, const ia32_register_req_t **reqs) { */ const ia32_register_req_t *get_ia32_in_req(const ir_node *node, int pos) { ia32_attr_t *attr = get_ia32_attr(node); - return attr->in_req[pos]; + return attr->in_req != NULL ? attr->in_req[pos] : NULL; } /** @@ -906,7 +984,7 @@ const ia32_register_req_t *get_ia32_in_req(const ir_node *node, int pos) { */ const ia32_register_req_t *get_ia32_out_req(const ir_node *node, int pos) { ia32_attr_t *attr = get_ia32_attr(node); - return attr->out_req[pos]; + return attr->out_req != NULL ? attr->out_req[pos] : NULL; } /** @@ -997,6 +1075,23 @@ void set_ia32_pncode(ir_node *node, long code) { attr->pn_code = code; } +/** + * Sets the flags for the n'th out. + */ +void set_ia32_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) { + ia32_attr_t *attr = get_ia32_attr(node); + assert(pos < (int) attr->data.n_res && "Invalid OUT position."); + attr->out_flags[pos] = flags; +} + +/** + * Gets the flags for the n'th out. + */ +arch_irn_flags_t get_ia32_out_flags(const ir_node *node, int pos) { + ia32_attr_t *attr = get_ia32_attr(node); + return pos < (int)attr->data.n_res ? attr->out_flags[pos] : arch_irn_flags_none; +} + #ifndef NDEBUG /** @@ -1098,7 +1193,7 @@ void copy_ia32_Immop_attr(ir_node *dst, ir_node *src) { } /** - * Copy the attributes from a Firm Const to an ia32_Const + * Copy the attributes from a Firm Const/SymConst to an ia32_Const */ void set_ia32_Const_attr(ir_node *ia32_cnst, ir_node *cnst) { ia32_attr_t *attr = get_ia32_attr(ia32_cnst); @@ -1112,8 +1207,9 @@ void set_ia32_Const_attr(ir_node *ia32_cnst, ir_node *cnst) { attr->cnst_val.tv = get_Const_tarval(cnst); mode = get_tarval_mode(attr->cnst_val.tv); if (mode_is_reference(mode) && - get_mode_null(mode) == attr->cnst_val.tv) - attr->cnst_val.tv = get_mode_null(mode_Is); + get_mode_null(mode) == attr->cnst_val.tv) { + attr->cnst_val.tv = get_mode_null(mode_Iu); + } attr->cnst = get_ident_for_tv(attr->cnst_val.tv); break; case iro_SymConst: @@ -1183,21 +1279,24 @@ int is_ia32_AddrModeD(const ir_node *node) { * Checks if node is a Load or xLoad/vfLoad. */ int is_ia32_Ld(const ir_node *node) { - return is_ia32_Load(node) || is_ia32_xLoad(node) || is_ia32_vfld(node) || is_ia32_fld(node); + int op = get_ia32_irn_opcode(node); + return op == iro_ia32_Load || op == iro_ia32_xLoad || op == iro_ia32_vfld || op == iro_ia32_fld; } /** * Checks if node is a Store or xStore/vfStore. */ int is_ia32_St(const ir_node *node) { - return is_ia32_Store(node) || is_ia32_xStore(node) || is_ia32_vfst(node) || is_ia32_fst(node) || is_ia32_fstp(node); + int op = get_ia32_irn_opcode(node); + return op == iro_ia32_Store || op == iro_ia32_xStore || op == iro_ia32_vfst || op == iro_ia32_fst || op == iro_ia32_fstp; } /** * Checks if node is a Const or xConst/vfConst. */ int is_ia32_Cnst(const ir_node *node) { - return is_ia32_Const(node) || is_ia32_xConst(node) || is_ia32_vfConst(node); + int op = get_ia32_irn_opcode(node); + return op == iro_ia32_Const || op == iro_ia32_xConst || op == iro_ia32_vfConst; } /** @@ -1206,7 +1305,6 @@ int is_ia32_Cnst(const ir_node *node) { const char *get_ia32_out_reg_name(const ir_node *node, int pos) { ia32_attr_t *attr = get_ia32_attr(node); - assert(is_ia32_irn(node) && "Not an ia32 node."); assert(pos < (int) attr->data.n_res && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); @@ -1219,7 +1317,6 @@ const char *get_ia32_out_reg_name(const ir_node *node, int pos) { int get_ia32_out_regnr(const ir_node *node, int pos) { ia32_attr_t *attr = get_ia32_attr(node); - assert(is_ia32_irn(node) && "Not an ia32 node."); assert(pos < (int) attr->data.n_res && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); @@ -1232,7 +1329,6 @@ int get_ia32_out_regnr(const ir_node *node, int pos) { const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) { ia32_attr_t *attr = get_ia32_attr(node); - assert(is_ia32_irn(node) && "Not an ia32 node."); assert(pos < (int) attr->data.n_res && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); @@ -1243,12 +1339,16 @@ const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) { * Initializes the nodes attributes. */ void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const ia32_register_req_t **in_reqs, - const ia32_register_req_t **out_reqs, int n_res) + const ia32_register_req_t **out_reqs, int n_res, unsigned latency) { ia32_attr_t *attr = get_ia32_attr(node); set_ia32_flags(node, flags); set_ia32_in_req_all(node, in_reqs); set_ia32_out_req_all(node, out_reqs); + set_ia32_latency(node, latency); + + attr->out_flags = NEW_ARR_D(int, get_irg_obstack(get_irn_irg(node)), n_res); + memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0])); attr->data.n_res = n_res; memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0])); @@ -1288,5 +1388,30 @@ int ia32_compare_conv_attr(ia32_attr_t *a, ia32_attr_t *b) { return !equ; } +/* Copy attribute function not needed any more, but might be of use later. */ +#if 0 +/* copies the ia32 attributes */ +static void ia32_copy_attr(const ir_node *old_node, ir_node *new_node) { + ia32_attr_t *attr_old = get_ia32_attr(old_node); + ia32_attr_t *attr_new = get_ia32_attr(new_node); + int n_res = get_ia32_n_res(old_node); + + /* copy the attributes */ + memcpy(attr_new, attr_old, sizeof(*attr_new)); +} + +/** + * Registers the ia32_copy_attr function for all ia32 opcodes. + */ +void ia32_register_copy_attr_func(void) { + unsigned i, f = get_ia32_opcode_first(), l = get_ia32_opcode_last(); + + for (i = f; i < l; i++) { + ir_op *op = get_irp_opcode(i); + op->ops.copy_attr = ia32_copy_attr; + } +} +#endif + /* Include the generated constructor functions */ #include "gen_ia32_new_nodes.c.inl"