X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_new_nodes.c;h=d077b3ad1ed2c71c10f018452c36db5d8ff7ab55;hb=eee248543bd61ec5c3f6aaaa23b9b0cff042fb71;hp=c07081c4c6941bfbc5f93c02db9e43c59a370dca;hpb=72ae1ac93c6cc7988db8cfa919ae147e10f98e82;p=libfirm diff --git a/ir/be/ia32/ia32_new_nodes.c b/ir/be/ia32/ia32_new_nodes.c index c07081c4c..d077b3ad1 100644 --- a/ir/be/ia32/ia32_new_nodes.c +++ b/ir/be/ia32/ia32_new_nodes.c @@ -243,6 +243,23 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { } fprintf(F, "\n"); + /* dump immop type */ + fprintf(F, "immediate = "); + switch (get_ia32_immop_type(n)) { + case ia32_ImmNone: + fprintf(F, "None"); + break; + case ia32_ImmConst: + fprintf(F, "Const"); + break; + case ia32_ImmSymConst: + fprintf(F, "SymConst"); + break; + default: + fprintf(F, "unknown (%d)", get_ia32_immop_type(n)); + break; + } + fprintf(F, "\n"); /* dump supported am */ fprintf(F, "AM support = "); @@ -312,6 +329,18 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { /* commutative */ fprintf(F, "commutative = %d\n", is_ia32_commutative(n)); + /* emit cl */ + fprintf(F, "emit cl instead of ecx = %d\n", is_ia32_emit_cl(n)); + + /* got lea */ + fprintf(F, "got loea = %d\n", is_ia32_got_lea(n)); + + /* got reload */ + fprintf(F, "got reload = %d\n", is_ia32_got_reload(n)); + + /* dump latency */ + fprintf(F, "latency = %d\n", get_ia32_latency(n)); + /* dump flags */ fprintf(F, "flags ="); flags = get_ia32_flags(n); @@ -328,6 +357,9 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { if (flags & arch_irn_flags_ignore) { fprintf(F, " ignore"); } + if (flags & arch_irn_flags_modify_sp) { + fprintf(F, " modify_sp"); + } } fprintf(F, " (%d)\n", flags); @@ -341,6 +373,43 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { } fprintf(F, "\n"); + /* dump modes */ + fprintf(F, "ls_mode = "); + if (get_ia32_ls_mode(n)) { + ir_fprintf(F, "%+F", get_ia32_ls_mode(n)); + } + else { + fprintf(F, "n/a"); + } + fprintf(F, "\n"); + + fprintf(F, "res_mode = "); + if (get_ia32_res_mode(n)) { + ir_fprintf(F, "%+F", get_ia32_res_mode(n)); + } + else { + fprintf(F, "n/a"); + } + fprintf(F, "\n"); + + fprintf(F, "src_mode = "); + if (get_ia32_src_mode(n)) { + ir_fprintf(F, "%+F", get_ia32_src_mode(n)); + } + else { + fprintf(F, "n/a"); + } + fprintf(F, "\n"); + + fprintf(F, "tgt_mode = "); + if (get_ia32_tgt_mode(n)) { + ir_fprintf(F, "%+F", get_ia32_tgt_mode(n)); + } + else { + fprintf(F, "n/a"); + } + fprintf(F, "\n"); + #ifndef NDEBUG /* dump original ir node name */ fprintf(F, "orig node = "); @@ -379,8 +448,8 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) { */ static ident *get_ident_for_tv(tarval *tv) { char buf[1024]; - - assert(tarval_snprintf(buf, sizeof(buf), tv)); + int len = tarval_snprintf(buf, sizeof(buf), tv); + assert(len); return new_id_from_str(buf); } @@ -482,7 +551,6 @@ char *get_ia32_am_offs(const ir_node *node) { res[0] = attr->data.offs_sign ? '-' : '+'; memcpy(&res[1], obstack_base(attr->am_offs), size); res[size + 1] = '\0'; - res = obstack_finish(attr->plain_offs); } return res; @@ -757,6 +825,30 @@ int is_ia32_got_lea(const ir_node *node) { return attr->data.got_lea; } +/** + * Sets node got_reload. + */ +void set_ia32_got_reload(ir_node *node) { + ia32_attr_t *attr = get_ia32_attr(node); + attr->data.got_reload = 1; +} + +/** + * Clears node got_reload. + */ +void clear_ia32_got_reload(ir_node *node) { + ia32_attr_t *attr = get_ia32_attr(node); + attr->data.got_reload = 0; +} + +/** + * Checks if node got reload. + */ +int is_ia32_got_reload(const ir_node *node) { + ia32_attr_t *attr = get_ia32_attr(node); + return attr->data.got_reload; +} + /** * Gets the mode of the stored/loaded value (only set for Store/Load) */ @@ -822,7 +914,7 @@ void set_ia32_tgt_mode(ir_node *node, ir_mode *mode) { } /** - * Gets the frame entity assigned to this node; + * Gets the frame entity assigned to this node. */ entity *get_ia32_frame_ent(const ir_node *node) { ia32_attr_t *attr = get_ia32_attr(node); @@ -830,11 +922,29 @@ entity *get_ia32_frame_ent(const ir_node *node) { } /** - * Sets the frame entity for this node; + * Sets the frame entity for this node. */ void set_ia32_frame_ent(ir_node *node, entity *ent) { ia32_attr_t *attr = get_ia32_attr(node); attr->frame_ent = ent; + set_ia32_use_frame(node); +} + + +/** + * Gets the instruction latency. + */ +unsigned get_ia32_latency(const ir_node *node) { + ia32_attr_t *attr = get_ia32_attr(node); + return attr->latency; +} + +/** +* Sets the instruction latency. +*/ +void set_ia32_latency(ir_node *node, unsigned latency) { + ia32_attr_t *attr = get_ia32_attr(node); + attr->latency = latency; } /** @@ -1078,6 +1188,7 @@ void copy_ia32_Immop_attr(ir_node *dst, ir_node *src) { */ void set_ia32_Const_attr(ir_node *ia32_cnst, ir_node *cnst) { ia32_attr_t *attr = get_ia32_attr(ia32_cnst); + ir_mode *mode; assert(is_ia32_Cnst(ia32_cnst) && "Need ia32_Const to set Const attr"); @@ -1085,6 +1196,10 @@ void set_ia32_Const_attr(ir_node *ia32_cnst, ir_node *cnst) { case iro_Const: attr->data.tp = ia32_Const; attr->cnst_val.tv = get_Const_tarval(cnst); + mode = get_tarval_mode(attr->cnst_val.tv); + if (mode_is_reference(mode) && + get_mode_null(mode) == attr->cnst_val.tv) + attr->cnst_val.tv = get_mode_null(mode_Is); attr->cnst = get_ident_for_tv(attr->cnst_val.tv); break; case iro_SymConst: @@ -1178,7 +1293,7 @@ const char *get_ia32_out_reg_name(const ir_node *node, int pos) { ia32_attr_t *attr = get_ia32_attr(node); assert(is_ia32_irn(node) && "Not an ia32 node."); - assert(pos < attr->data.n_res && "Invalid OUT position."); + assert(pos < (int) attr->data.n_res && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); return arch_register_get_name(attr->slots[pos]); @@ -1191,7 +1306,7 @@ int get_ia32_out_regnr(const ir_node *node, int pos) { ia32_attr_t *attr = get_ia32_attr(node); assert(is_ia32_irn(node) && "Not an ia32 node."); - assert(pos < attr->data.n_res && "Invalid OUT position."); + assert(pos < (int) attr->data.n_res && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); return arch_register_get_index(attr->slots[pos]); @@ -1204,7 +1319,7 @@ const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) { ia32_attr_t *attr = get_ia32_attr(node); assert(is_ia32_irn(node) && "Not an ia32 node."); - assert(pos < attr->data.n_res && "Invalid OUT position."); + assert(pos < (int) attr->data.n_res && "Invalid OUT position."); assert(attr->slots[pos] && "No register assigned"); return attr->slots[pos]; @@ -1214,12 +1329,13 @@ const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) { * Initializes the nodes attributes. */ void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags, const ia32_register_req_t **in_reqs, - const ia32_register_req_t **out_reqs, int n_res) + const ia32_register_req_t **out_reqs, int n_res, unsigned latency) { ia32_attr_t *attr = get_ia32_attr(node); set_ia32_flags(node, flags); set_ia32_in_req_all(node, in_reqs); set_ia32_out_req_all(node, out_reqs); + set_ia32_latency(node, latency); attr->data.n_res = n_res; memset((void *)attr->slots, 0, n_res * sizeof(attr->slots[0]));