X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_fpu.c;h=b6bafb5af2c35adb8498ef0104fe3b7418a56bca;hb=491bf92f36819d268c3535f72899219cdbb2a985;hp=0642c0d88f0012be1f45783d23f6c8a9e239e33d;hpb=ad9464a5db0b98cb926aae609abe84db70b74291;p=libfirm diff --git a/ir/be/ia32/ia32_fpu.c b/ir/be/ia32/ia32_fpu.c index 0642c0d88..b6bafb5af 100644 --- a/ir/be/ia32/ia32_fpu.c +++ b/ir/be/ia32/ia32_fpu.c @@ -61,7 +61,7 @@ static ir_entity *create_ent(int value, const char *name) ir_graph *cnst_irg; ir_entity *ent; ir_node *cnst; - tarval *tv; + ir_tarval *tv; set_type_alignment_bytes(type, 4); @@ -87,7 +87,6 @@ static void create_fpcw_entities(void) static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force, ir_node *after) { - ir_node *spill = NULL; (void) env; /* we don't spill the fpcw in unsafe mode */ @@ -105,25 +104,26 @@ static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force, ir_graph *irg = get_irn_irg(state); ir_node *block = get_nodes_block(state); ir_node *noreg = ia32_new_NoReg_gp(irg); - ir_node *nomem = new_NoMem(); + ir_node *nomem = get_irg_no_mem(irg); ir_node *frame = get_irg_frame(irg); - - spill = new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem, state); + ir_node *spill + = new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem, state); set_ia32_op_type(spill, ia32_AddrModeD); /* use mode_Iu, as movl has a shorter opcode than movw */ set_ia32_ls_mode(spill, mode_Iu); set_ia32_use_frame(spill); sched_add_after(skip_Proj(after), spill); + return spill; } - return spill; + return NULL; } static ir_node *create_fldcw_ent(ir_node *block, ir_entity *entity) { ir_graph *irg = get_irn_irg(block); - ir_node *nomem = new_NoMem(); + ir_node *nomem = get_irg_no_mem(irg); ir_node *noreg = ia32_new_NoReg_gp(irg); ir_node *reload; @@ -132,7 +132,7 @@ static ir_node *create_fldcw_ent(ir_node *block, ir_entity *entity) set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode); set_ia32_am_sc(reload, entity); set_ia32_use_frame(reload); - arch_set_irn_register(reload, &ia32_fp_cw_regs[REG_FPCW]); + arch_set_irn_register(reload, &ia32_registers[REG_FPCW]); return reload; } @@ -166,13 +166,14 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state, set_ia32_op_type(reload, ia32_AddrModeS); set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode); set_ia32_use_frame(reload); - arch_set_irn_register(reload, &ia32_fp_cw_regs[REG_FPCW]); + arch_set_irn_register(reload, &ia32_registers[REG_FPCW]); sched_add_before(before, reload); } else { ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode; - ir_node *nomem = new_NoMem(); - ir_node *cwstore, *load, *load_res, *or, *store, *fldcw; + ir_node *nomem = get_irg_no_mem(irg); + ir_node *cwstore, *load, *load_res, *orn, *store, *fldcw; + ir_node *store_proj; ir_node *or_const; assert(last_state != NULL); @@ -194,23 +195,24 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state, /* TODO: make the actual mode configurable in ChangeCW... */ or_const = new_bd_ia32_Immediate(NULL, get_irg_start_block(irg), NULL, 0, 0, 3072); - arch_set_irn_register(or_const, &ia32_gp_regs[REG_GP_NOREG]); - or = new_bd_ia32_Or(NULL, block, noreg, noreg, nomem, load_res, + arch_set_irn_register(or_const, &ia32_registers[REG_GP_NOREG]); + orn = new_bd_ia32_Or(NULL, block, noreg, noreg, nomem, load_res, or_const); - sched_add_before(before, or); + sched_add_before(before, orn); - store = new_bd_ia32_Store(NULL, block, frame, noreg, nomem, or); + store = new_bd_ia32_Store(NULL, block, frame, noreg, nomem, orn); set_ia32_op_type(store, ia32_AddrModeD); /* use mode_Iu, as movl has a shorter opcode than movw */ set_ia32_ls_mode(store, mode_Iu); set_ia32_use_frame(store); + store_proj = new_r_Proj(store, mode_M, pn_ia32_Store_M); sched_add_before(before, store); - fldcw = new_bd_ia32_FldCW(NULL, block, frame, noreg, store); + fldcw = new_bd_ia32_FldCW(NULL, block, frame, noreg, store_proj); set_ia32_op_type(fldcw, ia32_AddrModeS); set_ia32_ls_mode(fldcw, lsmode); set_ia32_use_frame(fldcw); - arch_set_irn_register(fldcw, &ia32_fp_cw_regs[REG_FPCW]); + arch_set_irn_register(fldcw, &ia32_registers[REG_FPCW]); sched_add_before(before, fldcw); reload = fldcw; @@ -225,14 +227,14 @@ typedef struct collect_fpu_mode_nodes_env_t { static void collect_fpu_mode_nodes_walker(ir_node *node, void *data) { - collect_fpu_mode_nodes_env_t *env = data; + collect_fpu_mode_nodes_env_t *env = (collect_fpu_mode_nodes_env_t*)data; const arch_register_t *reg; if (!mode_is_data(get_irn_mode(node))) return; reg = arch_get_irn_register(node); - if (reg == &ia32_fp_cw_regs[REG_FPCW] && !is_ia32_ChangeCW(node)) { + if (reg == &ia32_registers[REG_FPCW] && !is_ia32_ChangeCW(node)) { ARR_APP1(ir_node*, env->state_nodes, node); } } @@ -241,18 +243,16 @@ static void rewire_fpu_mode_nodes(ir_graph *irg) { collect_fpu_mode_nodes_env_t env; be_ssa_construction_env_t senv; - const arch_register_t *reg = &ia32_fp_cw_regs[REG_FPCW]; + const arch_register_t *reg = &ia32_registers[REG_FPCW]; ir_node *initial_value; ir_node **phis; be_lv_t *lv = be_get_irg_liveness(irg); - int i, len; + size_t i, len; /* do ssa construction for the fpu modes */ env.state_nodes = NEW_ARR_F(ir_node*, 0); irg_walk_graph(irg, collect_fpu_mode_nodes_walker, NULL, &env); - initial_value = be_abi_get_ignore_irn(be_get_irg_abi(irg), reg); - /* nothing needs to be done, in fact we must not continue as for endless * loops noone is using the initial_value and it will point to a bad node * now @@ -262,6 +262,7 @@ static void rewire_fpu_mode_nodes(ir_graph *irg) return; } + initial_value = be_get_initial_reg_value(irg, reg); be_ssa_construction_init(&senv, irg); be_ssa_construction_add_copies(&senv, env.state_nodes, ARR_LEN(env.state_nodes)); @@ -297,6 +298,6 @@ void ia32_setup_fpu_mode(ir_graph *irg) rewire_fpu_mode_nodes(irg); /* ensure correct fpu mode for operations */ - be_assure_state(irg, &ia32_fp_cw_regs[REG_FPCW], + be_assure_state(irg, &ia32_registers[REG_FPCW], NULL, create_fpu_mode_spill, create_fpu_mode_reload); }