X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_finish.c;h=b7d3268702b4da1c33b52a95565ee6c6d2c0f618;hb=f2edb6301aa7affb0673e76436d9b4dbaef6b9e1;hp=848e40d401560865608978c6c0dc0dc93fdd5544;hpb=839487dfb4a714fa7e66063495ade6a3726040ef;p=libfirm diff --git a/ir/be/ia32/ia32_finish.c b/ir/be/ia32/ia32_finish.c index 848e40d40..b7d326870 100644 --- a/ir/be/ia32/ia32_finish.c +++ b/ir/be/ia32/ia32_finish.c @@ -1,16 +1,42 @@ +/* + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. + */ + /** - * This file implements functions to finalize the irg for emit. - * @author Christian Wuerdig - * $Id$ + * @file + * @brief This file implements functions to finalize the irg for emit. + * @author Christian Wuerdig + * @version $Id$ */ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif #include "irnode.h" #include "ircons.h" #include "irgmod.h" #include "irgwalk.h" +#include "iredges.h" +#include "irprintf.h" #include "pdeq.h" +#include "error.h" -#include "../bearch.h" +#include "../bearch_t.h" #include "../besched_t.h" #include "../benode_t.h" @@ -18,211 +44,206 @@ #include "ia32_finish.h" #include "ia32_new_nodes.h" #include "ia32_map_regs.h" +#include "ia32_common_transform.h" #include "ia32_transform.h" #include "ia32_dbg_stat.h" #include "ia32_optimize.h" #include "gen_ia32_regalloc_if.h" +DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) + /** * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG. * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION. */ -static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { - ia32_transform_env_t tenv; +static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) +{ + ir_graph *irg; ir_node *in1, *in2, *noreg, *nomem, *res; - const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots; + ir_node *noreg_fp, *block; + dbg_info *dbg; + const arch_register_t *in1_reg, *in2_reg, *out_reg; - /* Return if AM node or not a Sub or xSub */ - if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal) + /* fix_am will solve this for AddressMode variants */ + if (get_ia32_op_type(irn) != ia32_Normal) return; - noreg = ia32_new_NoReg_gp(cg); - nomem = new_rd_NoMem(cg->irg); - in1 = get_irn_n(irn, 2); - in2 = get_irn_n(irn, 3); - in1_reg = arch_get_irn_register(cg->arch_env, in1); - in2_reg = arch_get_irn_register(cg->arch_env, in2); - out_reg = get_ia32_out_reg(irn, 0); - - tenv.block = get_nodes_block(irn); - tenv.dbg = get_irn_dbg_info(irn); - tenv.irg = cg->irg; - tenv.irn = irn; - tenv.mode = get_ia32_res_mode(irn); - tenv.cg = cg; - DEBUG_ONLY(tenv.mod = cg->mod;) + noreg = ia32_new_NoReg_gp(cg); + noreg_fp = ia32_new_NoReg_xmm(cg); + nomem = new_rd_NoMem(cg->irg); + in1 = get_irn_n(irn, n_ia32_binary_left); + in2 = get_irn_n(irn, n_ia32_binary_right); + in1_reg = arch_get_irn_register(cg->arch_env, in1); + in2_reg = arch_get_irn_register(cg->arch_env, in2); + out_reg = get_ia32_out_reg(irn, 0); + + irg = cg->irg; + block = get_nodes_block(irn); /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */ - if (REGS_ARE_EQUAL(out_reg, in2_reg)) { - /* generate the neg src2 */ - res = gen_Minus_ex(&tenv, in2); - arch_set_irn_register(cg->arch_env, res, in2_reg); + if (out_reg != in2_reg) + return; - /* add to schedule */ - sched_add_before(irn, get_Proj_pred(res)); - sched_add_before(irn, res); + dbg = get_irn_dbg_info(irn); - /* generate the add */ - if (mode_is_float(tenv.mode)) { - res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem); - set_ia32_am_support(res, ia32_am_Source); - } - else { - res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem); - set_ia32_am_support(res, ia32_am_Full); - set_ia32_commutative(res); - } - set_ia32_res_mode(res, tenv.mode); + /* generate the neg src2 */ + if (is_ia32_xSub(irn)) { + int size; + ir_entity *entity; + ir_mode *op_mode = get_ia32_ls_mode(irn); - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn)); - /* copy register */ - slots = get_ia32_slots(res); - slots[0] = in2_reg; + assert(get_irn_mode(irn) != mode_T); + + res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp); + size = get_mode_size_bits(op_mode); + entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); + set_ia32_am_sc(res, entity); + set_ia32_op_type(res, ia32_AddrModeS); + set_ia32_ls_mode(res, op_mode); + + arch_set_irn_register(cg->arch_env, res, in2_reg); /* add to schedule */ sched_add_before(irn, res); - /* remove the old sub */ - sched_remove(irn); - - DBG_OPT_SUB2NEGADD(irn, res); + /* generate the add */ + res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1); + set_ia32_ls_mode(res, get_ia32_ls_mode(irn)); /* exchange the add and the sub */ - exchange(irn, res); - } -} + edges_reroute(irn, res, irg); -/** - * Transforms a LEA into an Add if possible - * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION. - */ -static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) { - ia32_am_flavour_t am_flav; - int imm = 0; - ir_node *res = NULL; - ir_node *nomem, *noreg, *base, *index, *op1, *op2; - char *offs; - ia32_transform_env_t tenv; - const arch_register_t *out_reg, *base_reg, *index_reg; - - /* must be a LEA */ - if (! is_ia32_Lea(irn)) - return; + /* add to schedule */ + sched_add_before(irn, res); + } else { + ir_node *res_proj = NULL; + ir_node *flags_proj = NULL; + const ir_edge_t *edge; + + if (get_irn_mode(irn) == mode_T) { + /* collect the Proj uses */ + foreach_out_edge(irn, edge) { + ir_node *proj = get_edge_src_irn(edge); + long pn = get_Proj_proj(proj); + if (pn == pn_ia32_Sub_res) { + assert(res_proj == NULL); + res_proj = proj; + } else { + assert(pn == pn_ia32_Sub_flags); + assert(flags_proj == NULL); + flags_proj = proj; + } + } + } - am_flav = get_ia32_am_flavour(irn); + if (flags_proj == NULL) { + res = new_rd_ia32_Neg(dbg, irg, block, in2); + arch_set_irn_register(cg->arch_env, res, in2_reg); - if (get_ia32_am_sc(irn)) - return; + /* add to schedule */ + sched_add_before(irn, res); - /* only some LEAs can be transformed to an Add */ - if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI) - return; + /* generate the add */ + res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1); + arch_set_irn_register(cg->arch_env, res, out_reg); + set_ia32_commutative(res); - noreg = ia32_new_NoReg_gp(cg); - nomem = new_rd_NoMem(cg->irg); - op1 = noreg; - op2 = noreg; - base = get_irn_n(irn, 0); - index = get_irn_n(irn,1); - - offs = get_ia32_am_offs(irn); - - /* offset has a explicit sign -> we need to skip + */ - if (offs && offs[0] == '+') - offs++; - - out_reg = arch_get_irn_register(cg->arch_env, irn); - base_reg = arch_get_irn_register(cg->arch_env, base); - index_reg = arch_get_irn_register(cg->arch_env, index); - - tenv.block = get_nodes_block(irn); - tenv.dbg = get_irn_dbg_info(irn); - tenv.irg = cg->irg; - tenv.irn = irn; - DEBUG_ONLY(tenv.mod = cg->mod;) - tenv.mode = get_irn_mode(irn); - tenv.cg = cg; - - switch(get_ia32_am_flavour(irn)) { - case ia32_am_B: - /* out register must be same as base register */ - if (! REGS_ARE_EQUAL(out_reg, base_reg)) - return; - - op1 = base; - break; - case ia32_am_OB: - /* out register must be same as base register */ - if (! REGS_ARE_EQUAL(out_reg, base_reg)) - return; + /* exchange the add and the sub */ + edges_reroute(irn, res, irg); - op1 = base; - imm = 1; - break; - case ia32_am_OI: - /* out register must be same as index register */ - if (! REGS_ARE_EQUAL(out_reg, index_reg)) - return; + /* add to schedule */ + sched_add_before(irn, res); + } else { + ir_node *stc, *cmc, *not, *adc; + ir_node *adc_flags; - op1 = index; - imm = 1; - break; - case ia32_am_BI: - /* out register must be same as one in register */ - if (REGS_ARE_EQUAL(out_reg, base_reg)) { - op1 = base; - op2 = index; - } - else if (REGS_ARE_EQUAL(out_reg, index_reg)) { - op1 = index; - op2 = base; - } - else { - /* in registers a different from out -> no Add possible */ - return; + /* + * ARG, the above technique does NOT set the flags right. + * So, we must produce the following code: + * t1 = ~b + * t2 = a + ~b + Carry + * Complement Carry + * + * a + -b = a + (~b + 1) would set the carry flag IF a == b ... + */ + not = new_rd_ia32_Not(dbg, irg, block, in2); + arch_set_irn_register(cg->arch_env, not, in2_reg); + sched_add_before(irn, not); + + stc = new_rd_ia32_Stc(dbg, irg, block); + arch_set_irn_register(cg->arch_env, stc, + &ia32_flags_regs[REG_EFLAGS]); + sched_add_before(irn, stc); + + adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not, + in1, stc); + arch_set_irn_register(cg->arch_env, adc, out_reg); + sched_add_before(irn, adc); + + set_irn_mode(adc, mode_T); + adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags); + arch_set_irn_register(cg->arch_env, adc_flags, + &ia32_flags_regs[REG_EFLAGS]); + + cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags); + arch_set_irn_register(cg->arch_env, cmc, + &ia32_flags_regs[REG_EFLAGS]); + sched_add_before(irn, cmc); + + exchange(flags_proj, cmc); + if (res_proj != NULL) { + set_Proj_pred(res_proj, adc); + set_Proj_proj(res_proj, pn_ia32_Adc_res); } - default: - break; - } - res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem); - arch_set_irn_register(cg->arch_env, res, out_reg); - set_ia32_op_type(res, ia32_Normal); - set_ia32_commutative(res); - set_ia32_res_mode(res, tenv.mode); - - if (imm) { - set_ia32_cnst(res, offs); - set_ia32_immop_type(res, ia32_ImmConst); + res = adc; + } } SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn)); - /* add Add to schedule */ - sched_add_before(irn, res); - - DBG_OPT_LEA2ADD(irn, res); + /* remove the old sub */ + sched_remove(irn); + kill_node(irn); - res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res); + DBG_OPT_SUB2NEGADD(irn, res); +} - /* add result Proj to schedule */ - sched_add_before(irn, res); +static INLINE int need_constraint_copy(ir_node *irn) +{ + /* TODO this should be determined from the node specification */ + switch (get_ia32_irn_opcode(irn)) { + case iro_ia32_IMul: { + /* the 3 operand form of IMul needs no constraint copy */ + ir_node *right = get_irn_n(irn, n_ia32_IMul_right); + return !is_ia32_Immediate(right); + } - /* remove the old LEA */ - sched_remove(irn); + case iro_ia32_Lea: + case iro_ia32_Conv_I2I: + case iro_ia32_Conv_I2I8Bit: + case iro_ia32_CMov: + return 0; - /* exchange the Add and the LEA */ - exchange(irn, res); + default: + return 1; + } } -static INLINE int need_constraint_copy(ir_node *irn) { - return \ - ! is_ia32_Lea(irn) && \ - ! is_ia32_Conv_I2I(irn) && \ - ! is_ia32_Conv_I2I8Bit(irn) && \ - ! is_ia32_CmpCMov(irn) && \ - ! is_ia32_PsiCondCMov(irn) && \ - ! is_ia32_CmpSet(irn); +/** + * Returns the index of the "same" register. + * On the x86, we should have only one. + */ +static int get_first_same(const arch_register_req_t* req) +{ + const unsigned other = req->other_same; + int i; + + for (i = 0; i < 32; ++i) { + if (other & (1U << i)) return i; + } + assert(! "same position not found"); + return 32; } /** @@ -230,143 +251,176 @@ static INLINE int need_constraint_copy(ir_node *irn) { * is not fulfilled. * Transform Sub into Neg -- Add if IN2 == OUT */ -static void ia32_finish_node(ir_node *irn, void *env) { - ia32_code_gen_t *cg = env; - const ia32_register_req_t **reqs; - const arch_register_t *out_reg, *in_reg, *in2_reg; +static void assure_should_be_same_requirements(ia32_code_gen_t *cg, + ir_node *node) +{ + ir_graph *irg = cg->irg; + const arch_env_t *arch_env = cg->arch_env; + const arch_register_req_t **reqs; + const arch_register_t *out_reg, *in_reg; int n_res, i; - ir_node *copy, *in_node, *block, *in2_node; - ia32_op_type_t op_tp; - - if (is_ia32_irn(irn)) { - /* AM Dest nodes don't produce any values */ - op_tp = get_ia32_op_type(irn); - if (op_tp == ia32_AddrModeD) - goto end; - - reqs = get_ia32_out_req_all(irn); - n_res = get_ia32_n_res(irn); - block = get_nodes_block(irn); - - /* check all OUT requirements, if there is a should_be_same */ - if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn)) - { - for (i = 0; i < n_res; i++) { - if (arch_register_req_is(&(reqs[i]->req), should_be_same)) { - /* get in and out register */ - out_reg = get_ia32_out_reg(irn, i); - in_node = get_irn_n(irn, reqs[i]->same_pos); - in_reg = arch_get_irn_register(cg->arch_env, in_node); - - /* don't copy ignore nodes */ - if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node)) - continue; - - /* check if in and out register are equal */ - if (! REGS_ARE_EQUAL(out_reg, in_reg)) { - /* in case of a commutative op: just exchange the in's */ - /* beware: the current op could be everything, so test for ia32 */ - /* commutativity first before getting the second in */ - if (is_ia32_commutative(irn)) { - in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1); - in2_reg = arch_get_irn_register(cg->arch_env, in2_node); - - if (REGS_ARE_EQUAL(out_reg, in2_reg)) { - set_irn_n(irn, reqs[i]->same_pos, in2_node); - set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node); - } - else - goto insert_copy; - } - else { -insert_copy: - DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos)); - /* create copy from in register */ - copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node); - - DBG_OPT_2ADDRCPY(copy); - - /* destination is the out register */ - arch_set_irn_register(cg->arch_env, copy, out_reg); - - /* insert copy before the node into the schedule */ - sched_add_before(irn, copy); - - /* set copy as in */ - set_irn_n(irn, reqs[i]->same_pos, copy); - } - } - } + ir_node *in_node, *block; + + reqs = get_ia32_out_req_all(node); + n_res = get_ia32_n_res(node); + block = get_nodes_block(node); + + /* check all OUT requirements, if there is a should_be_same */ + for (i = 0; i < n_res; i++) { + int i2, arity; + int same_pos; + ir_node *perm; + ir_node *in[2]; + ir_node *perm_proj0; + ir_node *perm_proj1; + ir_node *uses_out_reg; + const arch_register_req_t *req = reqs[i]; + const arch_register_class_t *cls; + int uses_out_reg_pos; + + if (!arch_register_req_is(req, should_be_same)) + continue; + + same_pos = get_first_same(req); + + /* get in and out register */ + out_reg = get_ia32_out_reg(node, i); + in_node = get_irn_n(node, same_pos); + in_reg = arch_get_irn_register(arch_env, in_node); + + /* requirement already fulfilled? */ + if (in_reg == out_reg) + continue; + /* unknowns can be changed to any register we want on emitting */ + if (is_unknown_reg(in_reg)) + continue; + cls = arch_register_get_class(in_reg); + assert(cls == arch_register_get_class(out_reg)); + + /* check if any other input operands uses the out register */ + arity = get_irn_arity(node); + uses_out_reg = NULL; + uses_out_reg_pos = -1; + for (i2 = 0; i2 < arity; ++i2) { + ir_node *in = get_irn_n(node, i2); + const arch_register_t *in_reg; + + if (!mode_is_data(get_irn_mode(in))) + continue; + + in_reg = arch_get_irn_register(arch_env, in); + + if (in_reg != out_reg) + continue; + + if (uses_out_reg != NULL && in != uses_out_reg) { + panic("invalid register allocation"); } + uses_out_reg = in; + if (uses_out_reg_pos >= 0) + uses_out_reg_pos = -1; /* multiple inputs... */ + else + uses_out_reg_pos = i2; } - /* check xCmp: try to avoid unordered cmp */ - if ((is_ia32_xCmp(irn) || is_ia32_xCmpCMov(irn) || is_ia32_xCmpSet(irn)) && - op_tp == ia32_Normal && - ! is_ia32_ImmConst(irn) && ! is_ia32_ImmSymConst(irn)) - { - long pnc = get_ia32_pncode(irn); + /* no-one else is using the out reg, we can simply copy it + * (the register can't be live since the operation will override it + * anyway) */ + if (uses_out_reg == NULL) { + ir_node *copy = be_new_Copy(cls, irg, block, in_node); + DBG_OPT_2ADDRCPY(copy); - if (pnc & pn_Cmp_Uo) { - ir_node *tmp; - int idx1 = 2, idx2 = 3; + /* destination is the out register */ + arch_set_irn_register(arch_env, copy, out_reg); - if (is_ia32_xCmpCMov(irn)) { - idx1 = 0; - idx2 = 1; - } + /* insert copy before the node into the schedule */ + sched_add_before(node, copy); - tmp = get_irn_n(irn, idx1); - set_irn_n(irn, idx1, get_irn_n(irn, idx2)); - set_irn_n(irn, idx2, tmp); + /* set copy as in */ + set_irn_n(node, same_pos, copy); - set_ia32_pncode(irn, get_negated_pnc(pnc, mode_D)); - } + DBG((dbg, LEVEL_1, + "created copy %+F for should be same argument at input %d of %+F\n", + copy, same_pos, node)); + continue; } - /* - If we have a CondJmp/CmpSet/xCmpSet with immediate, - we need to check if it's the right operand, otherwise - we have to change it, as CMP doesn't support immediate - as left operands. - */ -#if 0 - if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) && - (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && - op_tp == ia32_AddrModeS) - { - set_ia32_op_type(irn, ia32_AddrModeD); - set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn))); + /* for commutative nodes we can simply swap the left/right */ + if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) { + ia32_swap_left_right(node); + DBG((dbg, LEVEL_1, + "swapped left/right input of %+F to resolve should be same constraint\n", + node)); + continue; } + +#ifdef DEBUG_libfirm + ir_fprintf(stderr, "Note: need perm to resolve should_be_same constraint at %+F (this is unsafe and should not happen in theory...)\n", node); #endif + /* the out reg is used as node input: we need to permutate our input + * and the other (this is allowed, since the other node can't be live + * after! the operation as we will override the register. */ + in[0] = in_node; + in[1] = uses_out_reg; + perm = be_new_Perm(cls, irg, block, 2, in); + + perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0); + perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1); + + arch_set_irn_register(arch_env, perm_proj0, out_reg); + arch_set_irn_register(arch_env, perm_proj1, in_reg); + + sched_add_before(node, perm); + + DBG((dbg, LEVEL_1, + "created perm %+F for should be same argument at input %d of %+F (need permutate with %+F)\n", + perm, same_pos, node, uses_out_reg)); + + /* use the perm results */ + for (i2 = 0; i2 < arity; ++i2) { + ir_node *in = get_irn_n(node, i2); + + if (in == in_node) { + set_irn_n(node, i2, perm_proj0); + } else if (in == uses_out_reg) { + set_irn_n(node, i2, perm_proj1); + } + } } -end: ; } /** * Following Problem: * We have a source address mode node with base or index register equal to - * result register. The constraint handler will insert a copy from the - * remaining input operand to the result register -> base or index is - * broken then. + * result register and unfulfilled should_be_same requirement. The constraint + * handler will insert a copy from the remaining input operand to the result + * register -> base or index is broken then. * Solution: Turn back this address mode into explicit Load + Operation. */ -static void fix_am_source(ir_node *irn, void *env) { - ia32_code_gen_t *cg = env; - ir_node *base, *index, *noreg; - const arch_register_t *reg_base, *reg_index; - const ia32_register_req_t **reqs; - int n_res, i; +static void fix_am_source(ir_node *irn, void *env) +{ + ia32_code_gen_t *cg = env; + const arch_env_t *arch_env = cg->arch_env; + ir_node *base; + ir_node *index; + ir_node *noreg; + const arch_register_t *reg_base; + const arch_register_t *reg_index; + const arch_register_req_t **reqs; + int n_res, i; /* check only ia32 nodes with source address mode */ if (! is_ia32_irn(irn) || get_ia32_op_type(irn) != ia32_AddrModeS) return; + /* only need to fix binary operations */ + if (get_ia32_am_support(irn) != ia32_am_binary) + return; - base = get_irn_n(irn, 0); - index = get_irn_n(irn, 1); + base = get_irn_n(irn, n_ia32_base); + index = get_irn_n(irn, n_ia32_index); - reg_base = arch_get_irn_register(cg->arch_env, base); - reg_index = arch_get_irn_register(cg->arch_env, index); + reg_base = arch_get_irn_register(arch_env, base); + reg_index = arch_get_irn_register(arch_env, index); reqs = get_ia32_out_req_all(irn); noreg = ia32_new_NoReg_gp(cg); @@ -374,76 +428,85 @@ static void fix_am_source(ir_node *irn, void *env) { n_res = get_ia32_n_res(irn); for (i = 0; i < n_res; i++) { - if (arch_register_req_is(&(reqs[i]->req), should_be_same)) { + if (arch_register_req_is(reqs[i], should_be_same)) { /* get in and out register */ - const arch_register_t *out_reg = get_ia32_out_reg(irn, i); - - /* - there is a constraint for the remaining operand - and the result register is equal to base or index register - */ - if (reqs[i]->same_pos == 2 && - (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index))) - { - /* turn back address mode */ - ir_node *in_node = get_irn_n(irn, 2); - const arch_register_t *in_reg = arch_get_irn_register(cg->arch_env, in_node); - ir_node *block = get_nodes_block(irn); - ir_mode *ls_mode = get_ia32_ls_mode(irn); - ir_node *load; - int pnres; - - if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_gp]) { - load = new_rd_ia32_Load(NULL, cg->irg, block, base, index, get_irn_n(irn, 4)); - pnres = pn_ia32_Load_res; - } - else if (arch_register_get_class(in_reg) == &ia32_reg_classes[CLASS_ia32_xmm]) { - load = new_rd_ia32_xLoad(NULL, cg->irg, block, base, index, get_irn_n(irn, 4)); - pnres = pn_ia32_xLoad_res; - } - else { - assert(0 && "cannot turn back address mode for this register class"); + const arch_register_t *out_reg = get_ia32_out_reg(irn, i); + int same_pos = get_first_same(reqs[i]); + ir_node *same_node = get_irn_n(irn, same_pos); + const arch_register_t *same_reg + = arch_get_irn_register(arch_env, same_node); + ir_graph *irg = cg->irg; + dbg_info *dbgi = get_irn_dbg_info(irn); + ir_node *block = get_nodes_block(irn); + ir_node *load; + ir_node *load_res; + ir_node *mem; + + /* should_be same constraint is fullfilled, nothing to do */ + if (out_reg == same_reg) + continue; + + /* we only need to do something if the out reg is the same as base + or index register */ + if (out_reg != reg_base && out_reg != reg_index) + continue; + + /* turn back address mode */ + mem = get_irn_n(irn, n_ia32_mem); + assert(get_irn_mode(mem) == mode_M); + load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); + + /* copy address mode information to load */ + set_ia32_op_type(load, ia32_AddrModeS); + ia32_copy_am_attrs(load, irn); + if (is_ia32_is_reload(irn)) + set_ia32_is_reload(load); + + /* insert the load into schedule */ + sched_add_before(irn, load); + + DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load)); + + load_res = new_r_Proj(cg->irg, block, load, mode_Iu, pn_ia32_Load_res); + arch_set_irn_register(cg->arch_env, load_res, out_reg); + + /* set the new input operand */ + if (is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) + set_irn_n(irn, n_ia32_binary_left, load_res); + else + set_irn_n(irn, n_ia32_binary_right, load_res); + if (get_irn_mode(irn) == mode_T) { + const ir_edge_t *edge, *next; + foreach_out_edge_safe(irn, edge, next) { + ir_node *node = get_edge_src_irn(edge); + int pn = get_Proj_proj(node); + if (pn == pn_ia32_res) { + exchange(node, irn); + } else if (pn == pn_ia32_mem) { + set_Proj_pred(node, load); + set_Proj_proj(node, pn_ia32_Load_M); + } else { + panic("Unexpected Proj"); + } } - - /* copy address mode information to load */ - set_ia32_ls_mode(load, ls_mode); - set_ia32_am_flavour(load, get_ia32_am_flavour(irn)); - set_ia32_op_type(load, ia32_AddrModeS); - set_ia32_am_support(load, ia32_am_Source); - set_ia32_am_scale(load, get_ia32_am_scale(irn)); - set_ia32_am_sc(load, get_ia32_am_sc(irn)); - add_ia32_am_offs(load, get_ia32_am_offs(irn)); - set_ia32_frame_ent(load, get_ia32_frame_ent(irn)); - - if (is_ia32_use_frame(irn)) - set_ia32_use_frame(load); - - /* insert the load into schedule */ - sched_add_before(irn, load); - - DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load)); - - load = new_r_Proj(cg->irg, block, load, ls_mode, pnres); - arch_set_irn_register(cg->arch_env, load, out_reg); - - /* insert the load result proj into schedule */ - sched_add_before(irn, load); - - /* set the new input operand */ - set_irn_n(irn, 3, load); - - /* this is a normal node now */ - set_irn_n(irn, 0, noreg); - set_irn_n(irn, 1, noreg); - set_ia32_op_type(irn, ia32_Normal); - - break; + set_irn_mode(irn, mode_Iu); } + + /* this is a normal node now */ + set_irn_n(irn, n_ia32_base, noreg); + set_irn_n(irn, n_ia32_index, noreg); + set_ia32_op_type(irn, ia32_Normal); + break; } } } -static void ia32_finish_irg_walker(ir_node *block, void *env) { +/** + * Block walker: finishes a block + */ +static void ia32_finish_irg_walker(ir_node *block, void *env) +{ + ia32_code_gen_t *cg = env; ir_node *irn, *next; /* first: turn back AM source if necessary */ @@ -458,20 +521,28 @@ static void ia32_finish_irg_walker(ir_node *block, void *env) { next = sched_next(irn); /* check if there is a sub which need to be transformed */ - ia32_transform_sub_to_neg_add(irn, cg); - - /* transform a LEA into an Add if possible */ - ia32_transform_lea_to_add(irn, cg); + if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) { + ia32_transform_sub_to_neg_add(irn, cg); + } } /* second: insert copies and finish irg */ for (irn = sched_first(block); ! sched_is_end(irn); irn = next) { next = sched_next(irn); - ia32_finish_node(irn, env); + if (is_ia32_irn(irn)) { + /* some nodes are just a bit less efficient, but need no fixing if the + * should be same requirement is not fulfilled */ + if (need_constraint_copy(irn)) + assure_should_be_same_requirements(cg, irn); + } } } -static void ia32_push_on_queue_walker(ir_node *block, void *env) { +/** + * Block walker: pushes all blocks on a wait queue + */ +static void ia32_push_on_queue_walker(ir_node *block, void *env) +{ waitq *wq = env; waitq_put(wq, block); } @@ -480,7 +551,8 @@ static void ia32_push_on_queue_walker(ir_node *block, void *env) { /** * Add Copy nodes for not fulfilled should_be_equal constraints */ -void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) { +void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) +{ waitq *wq = new_waitq(); /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */ @@ -492,3 +564,8 @@ void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) { } del_waitq(wq); } + +void ia32_init_finish(void) +{ + FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish"); +}