X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_finish.c;h=804202b8b633d5a0c414b0d8ea86197031ac271c;hb=4d66883acde3a424b3523610582e7391ed09a4dd;hp=0eb6d1ddaa1b930a31381b394311c5e2a0c47f51;hpb=3c80f7a89f47a90db39bb261f573f34cb244556f;p=libfirm diff --git a/ir/be/ia32/ia32_finish.c b/ir/be/ia32/ia32_finish.c index 0eb6d1dda..804202b8b 100644 --- a/ir/be/ia32/ia32_finish.c +++ b/ir/be/ia32/ia32_finish.c @@ -1,9 +1,9 @@ /** - * This file implements functions to finalize the irg for emit. - * @author Christian Wuerdig - * $Id$ + * @file + * @brief This file implements functions to finalize the irg for emit. + * @author Christian Wuerdig + * @version $Id$ */ - #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -14,6 +14,7 @@ #include "irgwalk.h" #include "iredges.h" #include "pdeq.h" +#include "error.h" #include "../bearch.h" #include "../besched_t.h" @@ -28,6 +29,8 @@ #include "ia32_optimize.h" #include "gen_ia32_regalloc_if.h" +DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) + /** * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG. * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION. @@ -64,12 +67,12 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { /* generate the neg src2 */ if(mode_is_float(mode)) { int size; - ident *name; + ir_entity *entity; res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, in2, noreg_fp, nomem); size = get_mode_size_bits(mode); - name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); - set_ia32_am_sc(res, name); + entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); + set_ia32_am_sc(res, entity); set_ia32_op_type(res, ia32_AddrModeS); set_ia32_ls_mode(res, get_ia32_ls_mode(irn)); } else { @@ -135,7 +138,7 @@ static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) { am_flav = get_ia32_am_flavour(irn); /* mustn't have a symconst */ - if (get_ia32_am_sc(irn)) + if (get_ia32_am_sc(irn) != NULL || get_ia32_frame_ent(irn) != NULL) return; /* only some LEAs can be transformed to an Add */ @@ -243,7 +246,7 @@ static INLINE int need_constraint_copy(ir_node *irn) { */ static void ia32_finish_node(ir_node *irn, void *env) { ia32_code_gen_t *cg = env; - const ia32_register_req_t **reqs; + const arch_register_req_t **reqs; const arch_register_t *out_reg, *in_reg, *in2_reg; int n_res, i; ir_node *copy, *in_node, *block, *in2_node; @@ -263,10 +266,12 @@ static void ia32_finish_node(ir_node *irn, void *env) { if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn)) { for (i = 0; i < n_res; i++) { - if (arch_register_req_is(&(reqs[i]->req), should_be_same)) { + if (arch_register_req_is(reqs[i], should_be_same)) { + int same_pos = reqs[i]->other_same; + /* get in and out register */ out_reg = get_ia32_out_reg(irn, i); - in_node = get_irn_n(irn, reqs[i]->same_pos); + in_node = get_irn_n(irn, same_pos); in_reg = arch_get_irn_register(cg->arch_env, in_node); /* don't copy ignore nodes */ @@ -279,19 +284,19 @@ static void ia32_finish_node(ir_node *irn, void *env) { /* beware: the current op could be everything, so test for ia32 */ /* commutativity first before getting the second in */ if (is_ia32_commutative(irn)) { - in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1); + in2_node = get_irn_n(irn, same_pos ^ 1); in2_reg = arch_get_irn_register(cg->arch_env, in2_node); if (REGS_ARE_EQUAL(out_reg, in2_reg)) { - set_irn_n(irn, reqs[i]->same_pos, in2_node); - set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node); + set_irn_n(irn, same_pos, in2_node); + set_irn_n(irn, same_pos ^ 1, in_node); } else goto insert_copy; } else { insert_copy: - DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos)); + DBG((dbg, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, same_pos)); /* create copy from in register */ copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node); @@ -304,7 +309,7 @@ insert_copy: sched_add_before(irn, copy); /* set copy as in */ - set_irn_n(irn, reqs[i]->same_pos, copy); + set_irn_n(irn, same_pos, copy); } } } @@ -334,22 +339,6 @@ insert_copy: set_ia32_pncode(irn, get_negated_pnc(pnc, mode_E)); } } - - /* - If we have a CondJmp/CmpSet/xCmpSet with immediate, - we need to check if it's the right operand, otherwise - we have to change it, as CMP doesn't support immediate - as left operands. - */ -#if 0 - if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) && - (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && - op_tp == ia32_AddrModeS) - { - set_ia32_op_type(irn, ia32_AddrModeD); - set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn))); - } -#endif } end: ; } @@ -366,7 +355,7 @@ static void fix_am_source(ir_node *irn, void *env) { ia32_code_gen_t *cg = env; ir_node *base, *index, *noreg; const arch_register_t *reg_base, *reg_index; - const ia32_register_req_t **reqs; + const arch_register_req_t **reqs; int n_res, i; /* check only ia32 nodes with source address mode */ @@ -388,15 +377,16 @@ static void fix_am_source(ir_node *irn, void *env) { n_res = get_ia32_n_res(irn); for (i = 0; i < n_res; i++) { - if (arch_register_req_is(&(reqs[i]->req), should_be_same)) { + if (arch_register_req_is(reqs[i], should_be_same)) { /* get in and out register */ const arch_register_t *out_reg = get_ia32_out_reg(irn, i); + int same_pos = reqs[i]->other_same; /* there is a constraint for the remaining operand and the result register is equal to base or index register */ - if (reqs[i]->same_pos == 2 && + if (same_pos == 2 && (REGS_ARE_EQUAL(out_reg, reg_base) || REGS_ARE_EQUAL(out_reg, reg_index))) { /* turn back address mode */ @@ -416,7 +406,7 @@ static void fix_am_source(ir_node *irn, void *env) { pnres = pn_ia32_xLoad_res; } else { - assert(0 && "cannot turn back address mode for this register class"); + panic("cannot turn back address mode for this register class"); } /* copy address mode information to load */ @@ -435,7 +425,7 @@ static void fix_am_source(ir_node *irn, void *env) { /* insert the load into schedule */ sched_add_before(irn, load); - DBG((cg->mod, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load)); + DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", cg->irg, irn, load)); load = new_r_Proj(cg->irg, block, load, ls_mode, pnres); arch_set_irn_register(cg->arch_env, load, out_reg); @@ -506,3 +496,8 @@ void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) { } del_waitq(wq); } + +void ia32_init_finish(void) +{ + FIRM_DBG_REGISTER(dbg, "firm.be.ia32.finish"); +}