X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_finish.c;h=6ef76ccb2637f8b666a330f89388671aca5b413d;hb=eb593ca265a302849042866b57a3cf7a6e9495ab;hp=e0b23a851318c9c29a719136c73ca07ca016f895;hpb=590df14827a8ff5a5b53c506ac654876107bd8c9;p=libfirm diff --git a/ir/be/ia32/ia32_finish.c b/ir/be/ia32/ia32_finish.c index e0b23a851..6ef76ccb2 100644 --- a/ir/be/ia32/ia32_finish.c +++ b/ir/be/ia32/ia32_finish.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -44,6 +44,7 @@ #include "ia32_finish.h" #include "ia32_new_nodes.h" #include "ia32_map_regs.h" +#include "ia32_common_transform.h" #include "ia32_transform.h" #include "ia32_dbg_stat.h" #include "ia32_optimize.h" @@ -59,28 +60,21 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { ir_graph *irg; ir_node *in1, *in2, *noreg, *nomem, *res; ir_node *noreg_fp, *block; - ir_mode *mode = get_irn_mode(irn); - dbg_info *dbg = get_irn_dbg_info(irn); - const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots; - int i, arity; + dbg_info *dbg; + const arch_register_t *in1_reg, *in2_reg, *out_reg; - /* Return if not a Sub or xSub */ - if (!is_ia32_Sub(irn) && !is_ia32_xSub(irn)) - return; /* fix_am will solve this for AddressMode variants */ - if(get_ia32_op_type(irn) != ia32_Normal) + if (get_ia32_op_type(irn) != ia32_Normal) return; - noreg = ia32_new_NoReg_gp(cg); - noreg_fp = ia32_new_NoReg_fp(cg); - nomem = new_rd_NoMem(cg->irg); - in1 = get_irn_n(irn, n_ia32_binary_left); - in2 = get_irn_n(irn, n_ia32_binary_right); - in1_reg = arch_get_irn_register(cg->arch_env, in1); - in2_reg = arch_get_irn_register(cg->arch_env, in2); - out_reg = get_ia32_out_reg(irn, 0); - - assert(get_irn_mode(irn) != mode_T); + noreg = ia32_new_NoReg_gp(cg); + noreg_fp = ia32_new_NoReg_xmm(cg); + nomem = new_rd_NoMem(cg->irg); + in1 = get_irn_n(irn, n_ia32_binary_left); + in2 = get_irn_n(irn, n_ia32_binary_right); + in1_reg = arch_get_irn_register(cg->arch_env, in1); + in2_reg = arch_get_irn_register(cg->arch_env, in2); + out_reg = get_ia32_out_reg(irn, 0); irg = cg->irg; block = get_nodes_block(irn); @@ -89,54 +83,127 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { if (out_reg != in2_reg) return; + dbg = get_irn_dbg_info(irn); + /* generate the neg src2 */ - if(mode_is_float(mode)) { + if (is_ia32_xSub(irn)) { int size; ir_entity *entity; ir_mode *op_mode = get_ia32_ls_mode(irn); + assert(get_irn_mode(irn) != mode_T); + res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp); size = get_mode_size_bits(op_mode); entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); set_ia32_am_sc(res, entity); set_ia32_op_type(res, ia32_AddrModeS); set_ia32_ls_mode(res, op_mode); - } else { - res = new_rd_ia32_Neg(dbg, irg, block, in2); - } - arch_set_irn_register(cg->arch_env, res, in2_reg); - /* add to schedule */ - sched_add_before(irn, res); + arch_set_irn_register(cg->arch_env, res, in2_reg); - /* generate the add */ - if (mode_is_float(mode)) { + /* add to schedule */ + sched_add_before(irn, res); + + /* generate the add */ res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1); - set_ia32_am_support(res, ia32_am_Source, ia32_am_binary); set_ia32_ls_mode(res, get_ia32_ls_mode(irn)); + + /* exchange the add and the sub */ + edges_reroute(irn, res, irg); + + /* add to schedule */ + sched_add_before(irn, res); } else { - res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1); - set_ia32_am_support(res, ia32_am_Full, ia32_am_binary); - set_ia32_commutative(res); - } + ir_node *res_proj = NULL; + ir_node *flags_proj = NULL; + const ir_edge_t *edge; + + if (get_irn_mode(irn) == mode_T) { + /* collect the Proj uses */ + foreach_out_edge(irn, edge) { + ir_node *proj = get_edge_src_irn(edge); + long pn = get_Proj_proj(proj); + if(pn == pn_ia32_Sub_res) { + assert(res_proj == NULL); + res_proj = proj; + } else { + assert(pn == pn_ia32_Sub_flags); + assert(flags_proj == NULL); + flags_proj = proj; + } + } + } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn)); - /* copy register */ - slots = get_ia32_slots(res); - slots[0] = in2_reg; + if (flags_proj == NULL) { + res = new_rd_ia32_Neg(dbg, irg, block, in2); + arch_set_irn_register(cg->arch_env, res, in2_reg); + + /* add to schedule */ + sched_add_before(irn, res); + + /* generate the add */ + res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1); + arch_set_irn_register(cg->arch_env, res, out_reg); + set_ia32_commutative(res); + + /* exchange the add and the sub */ + edges_reroute(irn, res, irg); + + /* add to schedule */ + sched_add_before(irn, res); + } else { + ir_node *stc, *cmc, *not, *adc; + ir_node *adc_flags; + + /* + * ARG, the above technique does NOT set the flags right. + * So, we must produce the following code: + * t1 = ~b + * t2 = a + ~b + Carry + * Complement Carry + * + * a + -b = a + (~b + 1) would set the carry flag IF a == b ... + */ + not = new_rd_ia32_Not(dbg, irg, block, in2); + arch_set_irn_register(cg->arch_env, not, in2_reg); + sched_add_before(irn, not); + + stc = new_rd_ia32_Stc(dbg, irg, block); + arch_set_irn_register(cg->arch_env, stc, + &ia32_flags_regs[REG_EFLAGS]); + sched_add_before(irn, stc); + + adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not, + in1, stc); + arch_set_irn_register(cg->arch_env, adc, out_reg); + sched_add_before(irn, adc); + + set_irn_mode(adc, mode_T); + adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags); + arch_set_irn_register(cg->arch_env, adc_flags, + &ia32_flags_regs[REG_EFLAGS]); + + cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags); + arch_set_irn_register(cg->arch_env, cmc, + &ia32_flags_regs[REG_EFLAGS]); + sched_add_before(irn, cmc); + + exchange(flags_proj, cmc); + if (res_proj != NULL) { + set_Proj_pred(res_proj, adc); + set_Proj_proj(res_proj, pn_ia32_Adc_res); + } - /* exchange the add and the sub */ - edges_reroute(irn, res, irg); + res = adc; + } + } - /* add to schedule */ - sched_add_before(irn, res); + SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn)); /* remove the old sub */ sched_remove(irn); - arity = get_irn_arity(irn); - for(i = 0; i < arity; ++i) { - set_irn_n(irn, i, new_Bad()); - } + kill_node(irn); DBG_OPT_SUB2NEGADD(irn, res); } @@ -155,14 +222,20 @@ static INLINE int need_constraint_copy(ir_node *irn) { ! is_ia32_CMov(irn); } +/** + * Returns the index of the "same" register. + * On the x86, we should have only one. + */ static int get_first_same(const arch_register_req_t* req) { const unsigned other = req->other_same; int i; - for (i = 0;; ++i) { + for (i = 0; i < 32; ++i) { if (other & (1U << i)) return i; } + assert(! "same position not found"); + return 32; } /** @@ -179,17 +252,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, const arch_register_t *out_reg, *in_reg; int n_res, i; ir_node *in_node, *block; - ia32_op_type_t op_tp; - - if(!is_ia32_irn(node)) - return; - /* some nodes are just a bit less efficient, but need no fixing if the - * should be same requirement is not fulfilled */ - if(!need_constraint_copy(node)) - return; - - op_tp = get_ia32_op_type(node); reqs = get_ia32_out_req_all(node); n_res = get_ia32_n_res(node); block = get_nodes_block(node); @@ -204,7 +267,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, ir_node *perm_proj1; ir_node *uses_out_reg; const arch_register_req_t *req = reqs[i]; - const arch_register_class_t *class; + const arch_register_class_t *cls; int uses_out_reg_pos; if (!arch_register_req_is(req, should_be_same)) @@ -223,8 +286,8 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, /* unknowns can be changed to any register we want on emitting */ if (is_unknown_reg(in_reg)) continue; - class = arch_register_get_class(in_reg); - assert(class == arch_register_get_class(out_reg)); + cls = arch_register_get_class(in_reg); + assert(cls == arch_register_get_class(out_reg)); /* check if any other input operands uses the out register */ arity = get_irn_arity(node); @@ -256,7 +319,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, * (the register can't be live since the operation will override it * anyway) */ if(uses_out_reg == NULL) { - ir_node *copy = be_new_Copy(class, irg, block, in_node); + ir_node *copy = be_new_Copy(cls, irg, block, in_node); DBG_OPT_2ADDRCPY(copy); /* destination is the out register */ @@ -274,7 +337,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, } /* for commutative nodes we can simply swap the left/right */ - if(is_ia32_commutative(node) && uses_out_reg_pos == n_ia32_binary_right) { + if (uses_out_reg_pos == n_ia32_binary_right && is_ia32_commutative(node)) { ia32_swap_left_right(node); DBG((dbg, LEVEL_1, "swapped left/right input of %+F to resolve " "should be same constraint\n", node)); @@ -289,7 +352,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, * after! the operation as we will override the register. */ in[0] = in_node; in[1] = uses_out_reg; - perm = be_new_Perm(class, irg, block, 2, in); + perm = be_new_Perm(cls, irg, block, 2, in); perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0); perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1); @@ -324,7 +387,8 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, * register -> base or index is broken then. * Solution: Turn back this address mode into explicit Load + Operation. */ -static void fix_am_source(ir_node *irn, void *env) { +static void fix_am_source(ir_node *irn, void *env) +{ ia32_code_gen_t *cg = env; const arch_env_t *arch_env = cg->arch_env; ir_node *base; @@ -342,8 +406,8 @@ static void fix_am_source(ir_node *irn, void *env) { if (get_ia32_am_arity(irn) != ia32_am_binary) return; - base = get_irn_n(irn, 0); - index = get_irn_n(irn, 1); + base = get_irn_n(irn, n_ia32_base); + index = get_irn_n(irn, n_ia32_index); reg_base = arch_get_irn_register(arch_env, base); reg_index = arch_get_irn_register(arch_env, index); @@ -370,6 +434,7 @@ static void fix_am_source(ir_node *irn, void *env) { ir_node *load_res; ir_node *mem; int pnres; + int pnmem; /* should_be same constraint is fullfilled, nothing to do */ if(out_reg == same_reg) @@ -387,11 +452,13 @@ static void fix_am_source(ir_node *irn, void *env) { if (same_cls == &ia32_reg_classes[CLASS_ia32_gp]) { load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); pnres = pn_ia32_Load_res; + pnmem = pn_ia32_Load_M; proj_mode = mode_Iu; } else if (same_cls == &ia32_reg_classes[CLASS_ia32_xmm]) { load = new_rd_ia32_xLoad(dbgi, irg, block, base, index, mem, get_ia32_ls_mode(irn)); pnres = pn_ia32_xLoad_res; + pnmem = pn_ia32_xLoad_M; proj_mode = mode_E; } else { panic("cannot turn back address mode for this register class"); @@ -400,6 +467,8 @@ static void fix_am_source(ir_node *irn, void *env) { /* copy address mode information to load */ set_ia32_op_type(load, ia32_AddrModeS); ia32_copy_am_attrs(load, irn); + if (is_ia32_is_reload(irn)) + set_ia32_is_reload(load); /* insert the load into schedule */ sched_add_before(irn, load); @@ -416,11 +485,13 @@ static void fix_am_source(ir_node *irn, void *env) { foreach_out_edge_safe(irn, edge, next) { ir_node *node = get_edge_src_irn(edge); int pn = get_Proj_proj(node); - if(pn == 0) { + if (pn == pn_ia32_res) { exchange(node, irn); - } else { - assert(pn == 1); + } else if (pn == pn_ia32_mem) { set_Proj_pred(node, load); + set_Proj_proj(node, pnmem); + } else { + panic("Unexpected Proj"); } } set_irn_mode(irn, mode_Iu); @@ -454,13 +525,20 @@ static void ia32_finish_irg_walker(ir_node *block, void *env) { next = sched_next(irn); /* check if there is a sub which need to be transformed */ - ia32_transform_sub_to_neg_add(irn, cg); + if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) { + ia32_transform_sub_to_neg_add(irn, cg); + } } /* second: insert copies and finish irg */ for (irn = sched_first(block); ! sched_is_end(irn); irn = next) { next = sched_next(irn); - assure_should_be_same_requirements(cg, irn); + if (is_ia32_irn(irn)) { + /* some nodes are just a bit less efficient, but need no fixing if the + * should be same requirement is not fulfilled */ + if (need_constraint_copy(irn)) + assure_should_be_same_requirements(cg, irn); + } } }