X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_finish.c;h=4984cb987cffe579ed4291688de8c2d71f884094;hb=deb677e11e06072b06af6e259402917b8bad3a35;hp=e1665561d7839955fefed51a34946df5a2d09881;hpb=b81fa67fd220d57b24df4d380c6511cacb44e7c1;p=libfirm diff --git a/ir/be/ia32/ia32_finish.c b/ir/be/ia32/ia32_finish.c index e1665561d..4984cb987 100644 --- a/ir/be/ia32/ia32_finish.c +++ b/ir/be/ia32/ia32_finish.c @@ -63,7 +63,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { const arch_register_t *in1_reg, *in2_reg, *out_reg; /* fix_am will solve this for AddressMode variants */ - if(get_ia32_op_type(irn) != ia32_Normal) + if (get_ia32_op_type(irn) != ia32_Normal) return; noreg = ia32_new_NoReg_gp(cg); @@ -85,7 +85,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { dbg = get_irn_dbg_info(irn); /* generate the neg src2 */ - if(is_ia32_xSub(irn)) { + if (is_ia32_xSub(irn)) { int size; ir_entity *entity; ir_mode *op_mode = get_ia32_ls_mode(irn); @@ -106,7 +106,6 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { /* generate the add */ res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1); - set_ia32_am_support(res, ia32_am_Source, ia32_am_binary); set_ia32_ls_mode(res, get_ia32_ls_mode(irn)); /* exchange the add and the sub */ @@ -119,7 +118,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { ir_node *flags_proj = NULL; const ir_edge_t *edge; - if(get_irn_mode(irn) == mode_T) { + if (get_irn_mode(irn) == mode_T) { /* collect the Proj uses */ foreach_out_edge(irn, edge) { ir_node *proj = get_edge_src_irn(edge); @@ -145,7 +144,6 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { /* generate the add */ res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1); arch_set_irn_register(cg->arch_env, res, out_reg); - set_ia32_am_support(res, ia32_am_Full, ia32_am_binary); set_ia32_commutative(res); /* exchange the add and the sub */ @@ -164,7 +162,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { * t2 = a + ~b + Carry * Complement Carry * - * a + -b = a + (~b + 1) would sat the carry flag IF a == b ... + * a + -b = a + (~b + 1) would set the carry flag IF a == b ... */ not = new_rd_ia32_Not(dbg, irg, block, in2); arch_set_irn_register(cg->arch_env, not, in2_reg); @@ -173,19 +171,25 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) { stc = new_rd_ia32_Stc(dbg, irg, block); arch_set_irn_register(cg->arch_env, stc, &ia32_flags_regs[REG_EFLAGS]); + sched_add_before(irn, stc); adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not, in1, stc); arch_set_irn_register(cg->arch_env, adc, out_reg); sched_add_before(irn, adc); + set_irn_mode(adc, mode_T); adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags); + arch_set_irn_register(cg->arch_env, adc_flags, + &ia32_flags_regs[REG_EFLAGS]); cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags); + arch_set_irn_register(cg->arch_env, cmc, + &ia32_flags_regs[REG_EFLAGS]); sched_add_before(irn, cmc); exchange(flags_proj, cmc); - if(res_proj != NULL) { + if (res_proj != NULL) { set_Proj_pred(res_proj, adc); set_Proj_proj(res_proj, pn_ia32_Adc_res); } @@ -262,7 +266,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, ir_node *perm_proj1; ir_node *uses_out_reg; const arch_register_req_t *req = reqs[i]; - const arch_register_class_t *class; + const arch_register_class_t *cls; int uses_out_reg_pos; if (!arch_register_req_is(req, should_be_same)) @@ -281,8 +285,8 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, /* unknowns can be changed to any register we want on emitting */ if (is_unknown_reg(in_reg)) continue; - class = arch_register_get_class(in_reg); - assert(class == arch_register_get_class(out_reg)); + cls = arch_register_get_class(in_reg); + assert(cls == arch_register_get_class(out_reg)); /* check if any other input operands uses the out register */ arity = get_irn_arity(node); @@ -314,7 +318,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, * (the register can't be live since the operation will override it * anyway) */ if(uses_out_reg == NULL) { - ir_node *copy = be_new_Copy(class, irg, block, in_node); + ir_node *copy = be_new_Copy(cls, irg, block, in_node); DBG_OPT_2ADDRCPY(copy); /* destination is the out register */ @@ -347,7 +351,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, * after! the operation as we will override the register. */ in[0] = in_node; in[1] = uses_out_reg; - perm = be_new_Perm(class, irg, block, 2, in); + perm = be_new_Perm(cls, irg, block, 2, in); perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0); perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1); @@ -428,6 +432,7 @@ static void fix_am_source(ir_node *irn, void *env) { ir_node *load_res; ir_node *mem; int pnres; + int pnmem; /* should_be same constraint is fullfilled, nothing to do */ if(out_reg == same_reg) @@ -445,11 +450,13 @@ static void fix_am_source(ir_node *irn, void *env) { if (same_cls == &ia32_reg_classes[CLASS_ia32_gp]) { load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); pnres = pn_ia32_Load_res; + pnmem = pn_ia32_Load_M; proj_mode = mode_Iu; } else if (same_cls == &ia32_reg_classes[CLASS_ia32_xmm]) { load = new_rd_ia32_xLoad(dbgi, irg, block, base, index, mem, get_ia32_ls_mode(irn)); pnres = pn_ia32_xLoad_res; + pnmem = pn_ia32_xLoad_M; proj_mode = mode_E; } else { panic("cannot turn back address mode for this register class"); @@ -476,9 +483,9 @@ static void fix_am_source(ir_node *irn, void *env) { int pn = get_Proj_proj(node); if(pn == 0) { exchange(node, irn); - } else { - assert(pn == 1); + } else if(pn == pn_ia32_mem) { set_Proj_pred(node, load); + set_Proj_proj(node, pnmem); } } set_irn_mode(irn, mode_Iu);