X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_finish.c;h=2e3519ceeda43ecaa4cc83f5f3e089260e976da3;hb=5427ad0b567409445284277a9c48d652179755ea;hp=11e10a717be071be7e6eb34a26d1cd63790b0a80;hpb=d60b3db8acfd4b02e615645575e89766a19ec9fc;p=libfirm diff --git a/ir/be/ia32/ia32_finish.c b/ir/be/ia32/ia32_finish.c index 11e10a717..2e3519cee 100644 --- a/ir/be/ia32/ia32_finish.c +++ b/ir/be/ia32/ia32_finish.c @@ -23,9 +23,7 @@ * @author Christian Wuerdig * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include "irnode.h" #include "ircons.h" @@ -36,14 +34,13 @@ #include "pdeq.h" #include "error.h" -#include "../bearch_t.h" -#include "../besched_t.h" -#include "../benode_t.h" +#include "../bearch.h" +#include "../besched.h" +#include "../benode.h" #include "bearch_ia32_t.h" #include "ia32_finish.h" #include "ia32_new_nodes.h" -#include "ia32_map_regs.h" #include "ia32_common_transform.h" #include "ia32_transform.h" #include "ia32_dbg_stat.h" @@ -53,10 +50,10 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) /** - * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG. + * Transforms a Sub or xSub into Neg--Add iff OUT_REG != SRC1_REG && OUT_REG == SRC2_REG. * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION. */ -static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) +static void ia32_transform_sub_to_neg_add(ir_node *irn) { ir_graph *irg; ir_node *in1, *in2, *noreg, *nomem, *res; @@ -68,23 +65,25 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) if (get_ia32_op_type(irn) != ia32_Normal) return; - noreg = ia32_new_NoReg_gp(cg); - noreg_fp = ia32_new_NoReg_xmm(cg); - nomem = new_rd_NoMem(cg->irg); + irg = get_irn_irg(irn); + noreg = ia32_new_NoReg_gp(irg); + noreg_fp = ia32_new_NoReg_xmm(irg); + nomem = new_r_NoMem(irg); in1 = get_irn_n(irn, n_ia32_binary_left); in2 = get_irn_n(irn, n_ia32_binary_right); - in1_reg = arch_get_irn_register(cg->arch_env, in1); - in2_reg = arch_get_irn_register(cg->arch_env, in2); - out_reg = get_ia32_out_reg(irn, 0); + in1_reg = arch_get_irn_register(in1); + in2_reg = arch_get_irn_register(in2); + out_reg = arch_irn_get_register(irn, 0); - irg = cg->irg; - block = get_nodes_block(irn); + if (out_reg == in1_reg) + return; /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */ if (out_reg != in2_reg) return; - dbg = get_irn_dbg_info(irn); + block = get_nodes_block(irn); + dbg = get_irn_dbg_info(irn); /* generate the neg src2 */ if (is_ia32_xSub(irn)) { @@ -94,24 +93,24 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) assert(get_irn_mode(irn) != mode_T); - res = new_rd_ia32_xXor(dbg, irg, block, noreg, noreg, nomem, in2, noreg_fp); + res = new_bd_ia32_xXor(dbg, block, noreg, noreg, nomem, in2, noreg_fp); size = get_mode_size_bits(op_mode); entity = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN); set_ia32_am_sc(res, entity); set_ia32_op_type(res, ia32_AddrModeS); set_ia32_ls_mode(res, op_mode); - arch_set_irn_register(cg->arch_env, res, in2_reg); + arch_set_irn_register(res, in2_reg); /* add to schedule */ sched_add_before(irn, res); /* generate the add */ - res = new_rd_ia32_xAdd(dbg, irg, block, noreg, noreg, nomem, res, in1); + res = new_bd_ia32_xAdd(dbg, block, noreg, noreg, nomem, res, in1); set_ia32_ls_mode(res, get_ia32_ls_mode(irn)); /* exchange the add and the sub */ - edges_reroute(irn, res, irg); + edges_reroute(irn, res); /* add to schedule */ sched_add_before(irn, res); @@ -137,24 +136,24 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) } if (flags_proj == NULL) { - res = new_rd_ia32_Neg(dbg, irg, block, in2); - arch_set_irn_register(cg->arch_env, res, in2_reg); + res = new_bd_ia32_Neg(dbg, block, in2); + arch_set_irn_register(res, in2_reg); /* add to schedule */ sched_add_before(irn, res); /* generate the add */ - res = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, res, in1); - arch_set_irn_register(cg->arch_env, res, out_reg); + res = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, res, in1); + arch_set_irn_register(res, out_reg); set_ia32_commutative(res); /* exchange the add and the sub */ - edges_reroute(irn, res, irg); + edges_reroute(irn, res); /* add to schedule */ sched_add_before(irn, res); } else { - ir_node *stc, *cmc, *not, *adc; + ir_node *stc, *cmc, *nnot, *adc; ir_node *adc_flags; /* @@ -166,28 +165,24 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) * * a + -b = a + (~b + 1) would set the carry flag IF a == b ... */ - not = new_rd_ia32_Not(dbg, irg, block, in2); - arch_set_irn_register(cg->arch_env, not, in2_reg); - sched_add_before(irn, not); + nnot = new_bd_ia32_Not(dbg, block, in2); + arch_set_irn_register(nnot, in2_reg); + sched_add_before(irn, nnot); - stc = new_rd_ia32_Stc(dbg, irg, block); - arch_set_irn_register(cg->arch_env, stc, - &ia32_flags_regs[REG_EFLAGS]); + stc = new_bd_ia32_Stc(dbg, block); + arch_set_irn_register(stc, &ia32_registers[REG_EFLAGS]); sched_add_before(irn, stc); - adc = new_rd_ia32_Adc(dbg, irg, block, noreg, noreg, nomem, not, - in1, stc); - arch_set_irn_register(cg->arch_env, adc, out_reg); + adc = new_bd_ia32_Adc(dbg, block, noreg, noreg, nomem, nnot, in1, stc); + arch_set_irn_register(adc, out_reg); sched_add_before(irn, adc); set_irn_mode(adc, mode_T); - adc_flags = new_r_Proj(irg, block, adc, mode_Iu, pn_ia32_Adc_flags); - arch_set_irn_register(cg->arch_env, adc_flags, - &ia32_flags_regs[REG_EFLAGS]); + adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags); + arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]); - cmc = new_rd_ia32_Cmc(dbg, irg, block, adc_flags); - arch_set_irn_register(cg->arch_env, cmc, - &ia32_flags_regs[REG_EFLAGS]); + cmc = new_bd_ia32_Cmc(dbg, block, adc_flags); + arch_set_irn_register(cmc, &ia32_registers[REG_EFLAGS]); sched_add_before(irn, cmc); exchange(flags_proj, cmc); @@ -200,7 +195,9 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) } } - SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn)); + set_irn_mode(res, get_irn_mode(irn)); + + SET_IA32_ORIG_NODE(res, irn); /* remove the old sub */ sched_remove(irn); @@ -209,7 +206,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) DBG_OPT_SUB2NEGADD(irn, res); } -static INLINE int need_constraint_copy(ir_node *irn) +static inline int need_constraint_copy(ir_node *irn) { /* TODO this should be determined from the node specification */ switch (get_ia32_irn_opcode(irn)) { @@ -222,7 +219,7 @@ static INLINE int need_constraint_copy(ir_node *irn) case iro_ia32_Lea: case iro_ia32_Conv_I2I: case iro_ia32_Conv_I2I8Bit: - case iro_ia32_CMov: + case iro_ia32_CMovcc: return 0; default: @@ -242,8 +239,7 @@ static int get_first_same(const arch_register_req_t* req) for (i = 0; i < 32; ++i) { if (other & (1U << i)) return i; } - assert(! "same position not found"); - return 32; + panic("same position not found"); } /** @@ -251,18 +247,13 @@ static int get_first_same(const arch_register_req_t* req) * is not fulfilled. * Transform Sub into Neg -- Add if IN2 == OUT */ -static void assure_should_be_same_requirements(ia32_code_gen_t *cg, - ir_node *node) +static void assure_should_be_same_requirements(ir_node *node) { - ir_graph *irg = cg->irg; - const arch_env_t *arch_env = cg->arch_env; - const arch_register_req_t **reqs; const arch_register_t *out_reg, *in_reg; int n_res, i; ir_node *in_node, *block; - reqs = get_ia32_out_req_all(node); - n_res = get_ia32_n_res(node); + n_res = arch_irn_get_n_outs(node); block = get_nodes_block(node); /* check all OUT requirements, if there is a should_be_same */ @@ -274,7 +265,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, ir_node *perm_proj0; ir_node *perm_proj1; ir_node *uses_out_reg; - const arch_register_req_t *req = reqs[i]; + const arch_register_req_t *req = arch_get_out_register_req(node, i); const arch_register_class_t *cls; int uses_out_reg_pos; @@ -284,16 +275,13 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, same_pos = get_first_same(req); /* get in and out register */ - out_reg = get_ia32_out_reg(node, i); - in_node = get_irn_n(node, same_pos); - in_reg = arch_get_irn_register(arch_env, in_node); + out_reg = arch_irn_get_register(node, i); + in_node = get_irn_n(node, same_pos); + in_reg = arch_get_irn_register(in_node); /* requirement already fulfilled? */ if (in_reg == out_reg) continue; - /* unknowns can be changed to any register we want on emitting */ - if (is_unknown_reg(in_reg)) - continue; cls = arch_register_get_class(in_reg); assert(cls == arch_register_get_class(out_reg)); @@ -308,7 +296,7 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, if (!mode_is_data(get_irn_mode(in))) continue; - in_reg = arch_get_irn_register(arch_env, in); + in_reg = arch_get_irn_register(in); if (in_reg != out_reg) continue; @@ -327,11 +315,11 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, * (the register can't be live since the operation will override it * anyway) */ if (uses_out_reg == NULL) { - ir_node *copy = be_new_Copy(cls, irg, block, in_node); + ir_node *copy = be_new_Copy(cls, block, in_node); DBG_OPT_2ADDRCPY(copy); /* destination is the out register */ - arch_set_irn_register(arch_env, copy, out_reg); + arch_set_irn_register(copy, out_reg); /* insert copy before the node into the schedule */ sched_add_before(node, copy); @@ -362,13 +350,13 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, * after! the operation as we will override the register. */ in[0] = in_node; in[1] = uses_out_reg; - perm = be_new_Perm(cls, irg, block, 2, in); + perm = be_new_Perm(cls, block, 2, in); - perm_proj0 = new_r_Proj(irg, block, perm, get_irn_mode(in[0]), 0); - perm_proj1 = new_r_Proj(irg, block, perm, get_irn_mode(in[1]), 1); + perm_proj0 = new_r_Proj(perm, get_irn_mode(in[0]), 0); + perm_proj1 = new_r_Proj(perm, get_irn_mode(in[1]), 1); - arch_set_irn_register(arch_env, perm_proj0, out_reg); - arch_set_irn_register(arch_env, perm_proj1, in_reg); + arch_set_irn_register(perm_proj0, out_reg); + arch_set_irn_register(perm_proj1, in_reg); sched_add_before(node, perm); @@ -397,11 +385,8 @@ static void assure_should_be_same_requirements(ia32_code_gen_t *cg, * register -> base or index is broken then. * Solution: Turn back this address mode into explicit Load + Operation. */ -static void fix_am_source(ir_node *irn, void *env) +static void fix_am_source(ir_node *irn) { - ia32_code_gen_t *cg = env; - const arch_env_t *arch_env = cg->arch_env; - const arch_register_req_t **reqs; int n_res, i; /* check only ia32 nodes with source address mode */ @@ -411,24 +396,24 @@ static void fix_am_source(ir_node *irn, void *env) if (get_ia32_am_support(irn) != ia32_am_binary) return; - reqs = get_ia32_out_req_all(irn); - n_res = get_ia32_n_res(irn); + n_res = arch_irn_get_n_outs(irn); for (i = 0; i < n_res; i++) { - const arch_register_t *out_reg; - int same_pos; - ir_node *same_node; - const arch_register_t *same_reg; - ir_node *load_res; + const arch_register_req_t *req = arch_get_out_register_req(irn, i); + const arch_register_t *out_reg; + int same_pos; + ir_node *same_node; + const arch_register_t *same_reg; + ir_node *load_res; - if (!arch_register_req_is(reqs[i], should_be_same)) + if (!arch_register_req_is(req, should_be_same)) continue; /* get in and out register */ - out_reg = get_ia32_out_reg(irn, i); - same_pos = get_first_same(reqs[i]); + out_reg = arch_irn_get_register(irn, i); + same_pos = get_first_same(req); same_node = get_irn_n(irn, same_pos); - same_reg = arch_get_irn_register(arch_env, same_node); + same_reg = arch_get_irn_register(same_node); /* should_be same constraint is fullfilled, nothing to do */ if (out_reg == same_reg) @@ -436,16 +421,16 @@ static void fix_am_source(ir_node *irn, void *env) /* we only need to do something if the out reg is the same as base or index register */ - if (out_reg != arch_get_irn_register(arch_env, get_irn_n(irn, n_ia32_base)) && - out_reg != arch_get_irn_register(arch_env, get_irn_n(irn, n_ia32_index))) + if (out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_base)) && + out_reg != arch_get_irn_register(get_irn_n(irn, n_ia32_index))) continue; - load_res = turn_back_am(irn); - arch_set_irn_register(cg->arch_env, load_res, out_reg); + load_res = ia32_turn_back_am(irn); + arch_set_irn_register(load_res, out_reg); DBG((dbg, LEVEL_3, "irg %+F: build back AM source for node %+F, inserted load %+F\n", - cg->irg, irn, get_Proj_pred(load_res))); + get_irn_irg(irn), irn, get_Proj_pred(load_res))); break; } } @@ -455,23 +440,21 @@ static void fix_am_source(ir_node *irn, void *env) */ static void ia32_finish_irg_walker(ir_node *block, void *env) { - ia32_code_gen_t *cg = env; ir_node *irn, *next; + (void) env; /* first: turn back AM source if necessary */ for (irn = sched_first(block); ! sched_is_end(irn); irn = next) { next = sched_next(irn); - fix_am_source(irn, env); + fix_am_source(irn); } for (irn = sched_first(block); ! sched_is_end(irn); irn = next) { - ia32_code_gen_t *cg = env; - next = sched_next(irn); /* check if there is a sub which need to be transformed */ if (is_ia32_Sub(irn) || is_ia32_xSub(irn)) { - ia32_transform_sub_to_neg_add(irn, cg); + ia32_transform_sub_to_neg_add(irn); } } @@ -482,7 +465,7 @@ static void ia32_finish_irg_walker(ir_node *block, void *env) /* some nodes are just a bit less efficient, but need no fixing if the * should be same requirement is not fulfilled */ if (need_constraint_copy(irn)) - assure_should_be_same_requirements(cg, irn); + assure_should_be_same_requirements(irn); } } } @@ -492,7 +475,7 @@ static void ia32_finish_irg_walker(ir_node *block, void *env) */ static void ia32_push_on_queue_walker(ir_node *block, void *env) { - waitq *wq = env; + waitq *wq = (waitq*)env; waitq_put(wq, block); } @@ -500,7 +483,7 @@ static void ia32_push_on_queue_walker(ir_node *block, void *env) /** * Add Copy nodes for not fulfilled should_be_equal constraints */ -void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) +void ia32_finish_irg(ir_graph *irg) { waitq *wq = new_waitq(); @@ -508,8 +491,8 @@ void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq); while (! waitq_empty(wq)) { - ir_node *block = waitq_get(wq); - ia32_finish_irg_walker(block, cg); + ir_node *block = (ir_node*)waitq_get(wq); + ia32_finish_irg_walker(block, NULL); } del_waitq(wq); }