X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_emitter.c;h=dc8b1b99d676922568859a032323d7300720b99c;hb=41dc42afc8d00e0f364711ed0c919e4e29cb20e4;hp=0bbc29ca090538904e297495e71183779e2825d8;hpb=6fad1812031f0457c843aa36bc9f90f252e0b269;p=libfirm diff --git a/ir/be/ia32/ia32_emitter.c b/ir/be/ia32/ia32_emitter.c index 0bbc29ca0..045ea1bc4 100644 --- a/ir/be/ia32/ia32_emitter.c +++ b/ir/be/ia32/ia32_emitter.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -22,6 +22,24 @@ * @brief This file implements the ia32 node emitter. * @author Christian Wuerdig, Matthias Braun * @version $Id$ + * + * Summary table for x86 floatingpoint compares: + * (remember effect of unordered on x86: ZF=1, PF=1, CF=1) + * + * pnc_Eq => !P && E + * pnc_Lt => !P && B + * pnc_Le => !P && BE + * pnc_Gt => A + * pnc_Ge => AE + * pnc_Lg => NE + * pnc_Leg => NP (ordered) + * pnc_Uo => P + * pnc_Ue => E + * pnc_Ul => B + * pnc_Ule => BE + * pnc_Ug => P || A + * pnc_Uge => P || AE + * pnc_Ne => P || NE */ #include "config.h" @@ -54,22 +72,19 @@ #include "../be_dbgout.h" #include "ia32_emitter.h" +#include "ia32_common_transform.h" #include "gen_ia32_emitter.h" #include "gen_ia32_regalloc_if.h" #include "ia32_nodes_attr.h" #include "ia32_new_nodes.h" -#include "ia32_map_regs.h" #include "ia32_architecture.h" #include "bearch_ia32_t.h" DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -#define BLOCK_PREFIX ".L" - #define SNPRINTF_BUF_LEN 128 static const ia32_isa_t *isa; -static ia32_code_gen_t *cg; static char pic_base_label[128]; static ir_label_t exc_label_id; static int mark_spill_reload = 0; @@ -78,7 +93,7 @@ static int do_pic; /** Return the next block in Block schedule */ static ir_node *get_prev_block_sched(const ir_node *block) { - return get_irn_link(block); + return (ir_node*)get_irn_link(block); } /** Checks if the current block is a fall-through target. */ @@ -122,109 +137,27 @@ static int block_needs_label(const ir_node *block) return need_label; } -/** - * Returns the register at in position pos. - */ -static const arch_register_t *get_in_reg(const ir_node *irn, int pos) -{ - ir_node *op; - const arch_register_t *reg = NULL; - - assert(get_irn_arity(irn) > pos && "Invalid IN position"); - - /* The out register of the operator at position pos is the - in register we need. */ - op = get_irn_n(irn, pos); - - reg = arch_get_irn_register(op); - - assert(reg && "no in register found"); - - if (reg == &ia32_gp_regs[REG_GP_NOREG]) - panic("trying to emit noreg for %+F input %d", irn, pos); - - /* in case of unknown register: just return a valid register */ - if (reg == &ia32_gp_regs[REG_GP_UKNWN]) { - const arch_register_req_t *req = arch_get_register_req(irn, pos); - - if (arch_register_req_is(req, limited)) { - /* in case of limited requirements: get the first allowed register */ - unsigned idx = rbitset_next(req->limited, 0, 1); - reg = arch_register_for_index(req->cls, idx); - } else { - /* otherwise get first register in class */ - reg = arch_register_for_index(req->cls, 0); - } - } - - return reg; -} - -/** - * Returns the register at out position pos. - */ -static const arch_register_t *get_out_reg(const ir_node *irn, int pos) -{ - ir_node *proj; - const arch_register_t *reg = NULL; - - /* 1st case: irn is not of mode_T, so it has only */ - /* one OUT register -> good */ - /* 2nd case: irn is of mode_T -> collect all Projs and ask the */ - /* Proj with the corresponding projnum for the register */ - - if (get_irn_mode(irn) != mode_T) { - assert(pos == 0); - reg = arch_get_irn_register(irn); - } else if (is_ia32_irn(irn)) { - reg = arch_irn_get_register(irn, pos); - } else { - const ir_edge_t *edge; - - foreach_out_edge(irn, edge) { - proj = get_edge_src_irn(edge); - assert(is_Proj(proj) && "non-Proj from mode_T node"); - if (get_Proj_proj(proj) == pos) { - reg = arch_get_irn_register(proj); - break; - } - } - } - - assert(reg && "no out register found"); - return reg; -} - /** * Add a number to a prefix. This number will not be used a second time. */ static char *get_unique_label(char *buf, size_t buflen, const char *prefix) { static unsigned long id = 0; - snprintf(buf, buflen, "%s%lu", prefix, ++id); + snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id); return buf; } -/************************************************************* - * _ _ __ _ _ - * (_) | | / _| | | | | - * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __ - * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__| - * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ | - * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_| - * | | | | - * |_| |_| - *************************************************************/ - /** * Emit the name of the 8bit low register */ static void emit_8bit_register(const arch_register_t *reg) { const char *reg_name = arch_register_get_name(reg); + assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX + || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX); be_emit_char('%'); - be_emit_char(reg_name[1]); + be_emit_char(reg_name[1]); /* get the basic name of the register */ be_emit_char('l'); } @@ -234,18 +167,20 @@ static void emit_8bit_register(const arch_register_t *reg) static void emit_8bit_register_high(const arch_register_t *reg) { const char *reg_name = arch_register_get_name(reg); + assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX + || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX); be_emit_char('%'); - be_emit_char(reg_name[1]); + be_emit_char(reg_name[1]); /* get the basic name of the register */ be_emit_char('h'); } static void emit_16bit_register(const arch_register_t *reg) { - const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg); + const char *reg_name = arch_register_get_name(reg); be_emit_char('%'); - be_emit_string(reg_name); + be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */ } /** @@ -275,18 +210,17 @@ static void emit_register(const arch_register_t *reg, const ir_mode *mode) void ia32_emit_source_register(const ir_node *node, int pos) { - const arch_register_t *reg = get_in_reg(node, pos); + const arch_register_t *reg = arch_get_irn_register_in(node, pos); emit_register(reg, NULL); } static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust) { - set_entity_backend_marked(entity, 1); be_gas_emit_entity(entity); if (get_entity_owner(entity) == get_tls_type()) { - if (get_entity_visibility(entity) == visibility_external_allocated) { + if (get_entity_visibility(entity) == ir_visibility_external) { be_emit_cstring("@INDNTPOFF"); } else { be_emit_cstring("@NTPOFF"); @@ -332,13 +266,13 @@ void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos) return; } - reg = get_in_reg(node, pos); + reg = arch_get_irn_register_in(node, pos); emit_8bit_register(reg); } void ia32_emit_8bit_high_source_register(const ir_node *node, int pos) { - const arch_register_t *reg = get_in_reg(node, pos); + const arch_register_t *reg = arch_get_irn_register_in(node, pos); emit_8bit_register_high(reg); } @@ -351,27 +285,27 @@ void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos) return; } - reg = get_in_reg(node, pos); + reg = arch_get_irn_register_in(node, pos); emit_16bit_register(reg); } void ia32_emit_dest_register(const ir_node *node, int pos) { - const arch_register_t *reg = get_out_reg(node, pos); + const arch_register_t *reg = arch_get_irn_register_out(node, pos); emit_register(reg, NULL); } void ia32_emit_dest_register_size(const ir_node *node, int pos) { - const arch_register_t *reg = get_out_reg(node, pos); + const arch_register_t *reg = arch_get_irn_register_out(node, pos); emit_register(reg, get_ia32_ls_mode(node)); } void ia32_emit_8bit_dest_register(const ir_node *node, int pos) { - const arch_register_t *reg = get_out_reg(node, pos); + const arch_register_t *reg = arch_get_irn_register_out(node, pos); emit_register(reg, mode_Bu); } @@ -421,13 +355,16 @@ void ia32_emit_x87_mode_suffix(const ir_node *node) if (mode_is_float(mode)) { switch (get_mode_size_bits(mode)) { - case 32: be_emit_char('s'); return; - case 64: be_emit_char('l'); return; - case 80: - case 96: be_emit_char('t'); return; + case 32: be_emit_char('s'); return; + case 64: be_emit_char('l'); return; + /* long doubles have different sizes due to alignment on different + * platforms. */ + case 80: + case 96: + case 128: be_emit_char('t'); return; } } else { - assert(mode_is_int(mode)); + assert(mode_is_int(mode) || mode_is_reference(mode)); switch (get_mode_size_bits(mode)) { case 16: be_emit_char('s'); return; case 32: be_emit_char('l'); return; @@ -442,7 +379,7 @@ void ia32_emit_x87_mode_suffix(const ir_node *node) static char get_xmm_mode_suffix(ir_mode *mode) { assert(mode_is_float(mode)); - switch(get_mode_size_bits(mode)) { + switch (get_mode_size_bits(mode)) { case 32: return 's'; case 64: return 'd'; default: panic("Invalid XMM mode"); @@ -480,7 +417,7 @@ void ia32_emit_source_register_or_immediate(const ir_node *node, int pos) emit_ia32_Immediate(in); } else { const ir_mode *mode = get_ia32_ls_mode(node); - const arch_register_t *reg = get_in_reg(node, pos); + const arch_register_t *reg = arch_get_irn_register_in(node, pos); emit_register(reg, mode); } } @@ -491,21 +428,7 @@ void ia32_emit_source_register_or_immediate(const ir_node *node, int pos) static ir_node *get_cfop_target_block(const ir_node *irn) { assert(get_irn_mode(irn) == mode_X); - return get_irn_link(irn); -} - -/** - * Emits a block label for the given block. - */ -static void ia32_emit_block_name(const ir_node *block) -{ - if (has_Block_entity(block)) { - ir_entity *entity = get_Block_entity(block); - be_gas_emit_entity(entity); - } else { - be_emit_cstring(BLOCK_PREFIX); - be_emit_irprintf("%ld", get_irn_node_nr(block)); - } + return (ir_node*)get_irn_link(irn); } /** @@ -514,62 +437,57 @@ static void ia32_emit_block_name(const ir_node *block) static void ia32_emit_cfop_target(const ir_node *node) { ir_node *block = get_cfop_target_block(node); - ia32_emit_block_name(block); + be_gas_emit_block_name(block); } -/* - * positive conditions for signed compares - */ -static const char *const cmp2condition_s[] = { - NULL, /* always false */ - "e", /* == */ - "l", /* < */ - "le", /* <= */ - "g", /* > */ - "ge", /* >= */ - "ne", /* != */ - NULL /* always true */ -}; - -/* - * positive conditions for unsigned compares - */ -static const char *const cmp2condition_u[] = { - NULL, /* always false */ - "e", /* == */ - "b", /* < */ - "be", /* <= */ - "a", /* > */ - "ae", /* >= */ - "ne", /* != */ - NULL /* always true */ -}; - /** * Emit the suffix for a compare instruction. */ -static void ia32_emit_cmp_suffix(int pnc) -{ - const char *str; - - if (pnc == ia32_pn_Cmp_parity) { - be_emit_char('p'); - return; - } - if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) { - str = cmp2condition_u[pnc & 7]; - } else { - str = cmp2condition_s[pnc & 7]; +static void ia32_emit_condition_code(ia32_condition_code_t cc) +{ + switch (cc) { + case ia32_cc_overflow: be_emit_cstring("o"); return; + case ia32_cc_not_overflow: be_emit_cstring("no"); return; + case ia32_cc_float_below: + case ia32_cc_float_unordered_below: + case ia32_cc_below: be_emit_cstring("b"); return; + case ia32_cc_float_above_equal: + case ia32_cc_float_unordered_above_equal: + case ia32_cc_above_equal: be_emit_cstring("ae"); return; + case ia32_cc_float_equal: + case ia32_cc_equal: be_emit_cstring("e"); return; + case ia32_cc_float_not_equal: + case ia32_cc_not_equal: be_emit_cstring("ne"); return; + case ia32_cc_float_below_equal: + case ia32_cc_float_unordered_below_equal: + case ia32_cc_below_equal: be_emit_cstring("be"); return; + case ia32_cc_float_above: + case ia32_cc_float_unordered_above: + case ia32_cc_above: be_emit_cstring("a"); return; + case ia32_cc_sign: be_emit_cstring("s"); return; + case ia32_cc_not_sign: be_emit_cstring("ns"); return; + case ia32_cc_parity: be_emit_cstring("p"); return; + case ia32_cc_not_parity: be_emit_cstring("np"); return; + case ia32_cc_less: be_emit_cstring("l"); return; + case ia32_cc_greater_equal: be_emit_cstring("ge"); return; + case ia32_cc_less_equal: be_emit_cstring("le"); return; + case ia32_cc_greater: be_emit_cstring("g"); return; + case ia32_cc_float_parity_cases: + case ia32_cc_additional_float_cases: + break; } - - be_emit_string(str); + panic("Invalid ia32 condition code"); } typedef enum ia32_emit_mod_t { + EMIT_NONE = 0, EMIT_RESPECT_LS = 1U << 0, EMIT_ALTERNATE_AM = 1U << 1, - EMIT_LONG = 1U << 2 + EMIT_LONG = 1U << 2, + EMIT_HIGH_REG = 1U << 3, + EMIT_LOW_REG = 1U << 4 } ia32_emit_mod_t; +ENUM_BITSET(ia32_emit_mod_t) /** * Emits address mode. @@ -580,12 +498,15 @@ void ia32_emit_am(const ir_node *node) int offs = get_ia32_am_offs_int(node); ir_node *base = get_irn_n(node, n_ia32_base); int has_base = !is_ia32_NoReg_GP(base); - ir_node *index = get_irn_n(node, n_ia32_index); - int has_index = !is_ia32_NoReg_GP(index); + ir_node *idx = get_irn_n(node, n_ia32_index); + int has_index = !is_ia32_NoReg_GP(idx); /* just to be sure... */ assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL); + if (get_ia32_am_tls_segment(node)) + be_emit_cstring("%gs:"); + /* emit offset */ if (ent != NULL) { const ia32_attr_t *attr = get_ia32_attr_const(node); @@ -608,13 +529,13 @@ void ia32_emit_am(const ir_node *node) /* emit base */ if (has_base) { - const arch_register_t *reg = get_in_reg(node, n_ia32_base); + const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base); emit_register(reg, NULL); } /* emit index + scale */ if (has_index) { - const arch_register_t *reg = get_in_reg(node, n_ia32_index); + const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index); int scale; be_emit_char(','); emit_register(reg, NULL); @@ -647,9 +568,11 @@ void ia32_emit_am(const ir_node *node) * %d signed int signed int * * x starts at 0 - * # modifier for %ASx, %D and %S uses ls mode of node to alter register width + * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width * * modifier does not prefix immediates with $, but AM with * * l modifier for %lu and %ld + * > modifier to output high 8bit register (ah, bh) + * < modifier to output low 8bit register (al, bl) */ static void ia32_emitf(const ir_node *node, const char *fmt, ...) { @@ -658,7 +581,7 @@ static void ia32_emitf(const ir_node *node, const char *fmt, ...) for (;;) { const char *start = fmt; - ia32_emit_mod_t mod = 0; + ia32_emit_mod_t mod = EMIT_NONE; while (*fmt != '%' && *fmt != '\n' && *fmt != '\0') ++fmt; @@ -678,127 +601,116 @@ static void ia32_emitf(const ir_node *node, const char *fmt, ...) break; ++fmt; - if (*fmt == '*') { - mod |= EMIT_ALTERNATE_AM; - ++fmt; - } - - if (*fmt == '#') { - mod |= EMIT_RESPECT_LS; - ++fmt; - } - - if (*fmt == 'l') { - mod |= EMIT_LONG; + for (;;) { + switch (*fmt) { + case '*': mod |= EMIT_ALTERNATE_AM; break; + case '#': mod |= EMIT_RESPECT_LS; break; + case 'l': mod |= EMIT_LONG; break; + case '>': mod |= EMIT_HIGH_REG; break; + case '<': mod |= EMIT_LOW_REG; break; + default: + goto end_of_mods; + } ++fmt; } +end_of_mods: switch (*fmt++) { + arch_register_t const *reg; + ir_node const *imm; + case '%': be_emit_char('%'); break; case 'A': { switch (*fmt++) { +emit_AM: case 'M': if (mod & EMIT_ALTERNATE_AM) be_emit_char('*'); - ia32_emit_am(node); break; - case 'R': { - const arch_register_t *reg = va_arg(ap, const arch_register_t*); - if (mod & EMIT_ALTERNATE_AM) - be_emit_char('*'); + case 'R': + reg = va_arg(ap, const arch_register_t*); if (get_ia32_op_type(node) == ia32_AddrModeS) { - ia32_emit_am(node); + goto emit_AM; } else { - emit_register(reg, NULL); + goto emit_R; } - break; - } case 'S': if (get_ia32_op_type(node) == ia32_AddrModeS) { - if (mod & EMIT_ALTERNATE_AM) - be_emit_char('*'); - ia32_emit_am(node); ++fmt; + goto emit_AM; } else { assert(get_ia32_op_type(node) == ia32_Normal); goto emit_S; } - break; default: goto unknown; } break; } - case 'D': { - unsigned pos; - const arch_register_t *reg; - + case 'D': if (*fmt < '0' || '9' <= *fmt) goto unknown; - - pos = *fmt++ - '0'; - reg = get_out_reg(node, pos); - emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL); - break; - } + reg = arch_get_irn_register_out(node, *fmt++ - '0'); + goto emit_R; case 'I': + imm = node; +emit_I: if (!(mod & EMIT_ALTERNATE_AM)) be_emit_char('$'); - emit_ia32_Immediate_no_prefix(node); + emit_ia32_Immediate_no_prefix(imm); break; case 'L': ia32_emit_cfop_target(node); break; - case 'M': { + case 'M': ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node)); break; - } case 'P': { - int pnc = va_arg(ap, int); - ia32_emit_cmp_suffix(pnc); + ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t); + ia32_emit_condition_code(cc); break; } - case 'R': { - const arch_register_t *reg = va_arg(ap, const arch_register_t*); - emit_register(reg, NULL); + case 'R': + reg = va_arg(ap, const arch_register_t*); +emit_R: + if (mod & EMIT_ALTERNATE_AM) + be_emit_char('*'); + if (mod & EMIT_HIGH_REG) { + emit_8bit_register_high(reg); + } else if (mod & EMIT_LOW_REG) { + emit_8bit_register(reg); + } else { + emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL); + } break; - } emit_S: case 'S': { - unsigned pos; - const ir_node *in; + unsigned pos; if (*fmt < '0' || '9' <= *fmt) goto unknown; pos = *fmt++ - '0'; - in = get_irn_n(node, pos); - if (is_ia32_Immediate(in)) { - if (!(mod & EMIT_ALTERNATE_AM)) - be_emit_char('$'); - emit_ia32_Immediate_no_prefix(in); + imm = get_irn_n(node, pos); + if (is_ia32_Immediate(imm)) { + goto emit_I; } else { - const arch_register_t *reg; - - if (mod & EMIT_ALTERNATE_AM) - be_emit_char('*'); - reg = get_in_reg(node, pos); - emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL); + reg = arch_get_irn_register_in(node, pos); + goto emit_R; } - break; } case 's': { @@ -853,7 +765,7 @@ void ia32_emit_binop(const ir_node *node) */ void ia32_emit_x87_binop(const ir_node *node) { - switch(get_ia32_op_type(node)) { + switch (get_ia32_op_type(node)) { case ia32_Normal: { const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node); @@ -895,11 +807,11 @@ void ia32_emit_unop(const ir_node *node, int pos) static void emit_ia32_IMul(const ir_node *node) { ir_node *left = get_irn_n(node, n_ia32_IMul_left); - const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res); + const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res); /* do we need the 3-address form? */ if (is_ia32_NoReg_GP(left) || - get_in_reg(node, n_ia32_IMul_left) != out_reg) { + arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) { ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n"); } else { ia32_emitf(node, "\timul%M %#AS4, %#S3\n"); @@ -928,11 +840,11 @@ static ir_node *find_original_value(ir_node *node) return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1)); } else if (is_ia32_Load(pred)) { return find_original_value(get_irn_n(pred, n_ia32_Load_mem)); + } else if (is_ia32_Store(pred)) { + return find_original_value(get_irn_n(pred, n_ia32_Store_val)); } else { return node; } - } else if (is_ia32_Store(node)) { - return find_original_value(get_irn_n(node, n_ia32_Store_val)); } else if (is_Phi(node)) { int i, arity; arity = get_irn_arity(node); @@ -949,8 +861,7 @@ static ir_node *find_original_value(ir_node *node) } } -static int determine_final_pnc(const ir_node *node, int flags_pos, - int pnc) +static int determine_final_cc(const ir_node *node, int flags_pos, int cc) { ir_node *flags = get_irn_n(node, flags_pos); const ia32_attr_t *flags_attr; @@ -968,46 +879,21 @@ static int determine_final_pnc(const ir_node *node, int flags_pos, } flags_attr = get_ia32_attr_const(cmp); - if (flags_attr->data.ins_permuted) - pnc = get_mirrored_pnc(pnc); - pnc |= ia32_pn_Cmp_float; - } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags) - || is_ia32_Fucompi(flags)) { - flags_attr = get_ia32_attr_const(flags); - - if (flags_attr->data.ins_permuted) - pnc = get_mirrored_pnc(pnc); - pnc |= ia32_pn_Cmp_float; } else { flags_attr = get_ia32_attr_const(flags); - - if (flags_attr->data.ins_permuted) - pnc = get_mirrored_pnc(pnc); - if (flags_attr->data.cmp_unsigned) - pnc |= ia32_pn_Cmp_unsigned; } - return pnc; -} - -static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc) -{ - ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu; - return get_negated_pnc(pnc, mode); + if (flags_attr->data.ins_permuted) + cc = ia32_invert_condition_code(cc); + return cc; } -void ia32_emit_cmp_suffix_node(const ir_node *node, - int flags_pos) +void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos) { - const ia32_attr_t *attr = get_ia32_attr_const(node); + ia32_condition_code_t cc = get_ia32_condcode(node); + cc = determine_final_cc(node, flags_pos, cc); - pn_Cmp pnc = get_ia32_condcode(node); - - pnc = determine_final_pnc(node, flags_pos, pnc); - if (attr->data.ins_permuted) - pnc = ia32_get_negated_pnc(pnc); - - ia32_emit_cmp_suffix(pnc); + ia32_emit_condition_code(cc); } /** @@ -1054,13 +940,12 @@ static int can_be_fallthrough(const ir_node *node) */ static void emit_ia32_Jcc(const ir_node *node) { - int need_parity_label = 0; - const ir_node *proj_true; - const ir_node *proj_false; - const ir_node *block; - pn_Cmp pnc = get_ia32_condcode(node); + int need_parity_label = 0; + ia32_condition_code_t cc = get_ia32_condcode(node); + const ir_node *proj_true; + const ir_node *proj_false; - pnc = determine_final_pnc(node, 0, pnc); + cc = determine_final_cc(node, 0, cc); /* get both Projs */ proj_true = get_proj(node, pn_ia32_Jcc_true); @@ -1069,57 +954,32 @@ static void emit_ia32_Jcc(const ir_node *node) proj_false = get_proj(node, pn_ia32_Jcc_false); assert(proj_false && "Jcc without false Proj"); - block = get_nodes_block(node); - if (can_be_fallthrough(proj_true)) { /* exchange both proj's so the second one can be omitted */ const ir_node *t = proj_true; proj_true = proj_false; proj_false = t; - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_negate_condition_code(cc); } - if (pnc & ia32_pn_Cmp_float) { + if (cc & ia32_cc_float_parity_cases) { /* Some floating point comparisons require a test of the parity flag, * which indicates that the result is unordered */ - switch (pnc & 15) { - case pn_Cmp_Uo: { - ia32_emitf(proj_true, "\tjp %L\n"); - break; + if (cc & ia32_cc_negated) { + ia32_emitf(proj_true, "\tjp %L\n"); + } else { + /* we need a local label if the false proj is a fallthrough + * as the falseblock might have no label emitted then */ + if (can_be_fallthrough(proj_false)) { + need_parity_label = 1; + ia32_emitf(proj_false, "\tjp 1f\n"); + } else { + ia32_emitf(proj_false, "\tjp %L\n"); } - - case pn_Cmp_Leg: - ia32_emitf(proj_true, "\tjnp %L\n"); - break; - - case pn_Cmp_Eq: - case pn_Cmp_Lt: - case pn_Cmp_Le: - /* we need a local label if the false proj is a fallthrough - * as the falseblock might have no label emitted then */ - if (can_be_fallthrough(proj_false)) { - need_parity_label = 1; - ia32_emitf(proj_false, "\tjp 1f\n"); - } else { - ia32_emitf(proj_false, "\tjp %L\n"); - } - goto emit_jcc; - - case pn_Cmp_Ug: - case pn_Cmp_Uge: - case pn_Cmp_Ne: - ia32_emitf(proj_true, "\tjp %L\n"); - goto emit_jcc; - - default: - goto emit_jcc; } - } else { -emit_jcc: - ia32_emitf(proj_true, "\tj%P %L\n", pnc); } - + ia32_emitf(proj_true, "\tj%P %L\n", cc); if (need_parity_label) { ia32_emitf(NULL, "1:\n"); } @@ -1132,19 +992,49 @@ emit_jcc: } } -static void emit_ia32_CMov(const ir_node *node) +/** + * Emits an ia32 Setcc. This is mostly easy but some floating point compares + * are tricky. + */ +static void emit_ia32_Setcc(const ir_node *node) { - const ia32_attr_t *attr = get_ia32_attr_const(node); - int ins_permuted = attr->data.ins_permuted; - const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res); - pn_Cmp pnc = get_ia32_condcode(node); + const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res); + + ia32_condition_code_t cc = get_ia32_condcode(node); + cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc); + if (cc & ia32_cc_float_parity_cases) { + if (cc & ia32_cc_negated) { + ia32_emitf(node, "\tset%P %R\n", dreg); + ia32_emitf(node, "\torb %>R, %R\n", dreg); + ia32_emitf(node, "\tandb %>R, %data.ins_permuted) + cc = ia32_negate_condition_code(cc); - in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true)); - in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false)); + in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true)); + in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false)); /* should be same constraint fullfilled? */ if (out == in_false) { @@ -1154,7 +1044,7 @@ static void emit_ia32_CMov(const ir_node *node) assert(get_ia32_op_type(node) == ia32_Normal); - ins_permuted = !ins_permuted; + cc = ia32_negate_condition_code(cc); tmp = in_true; in_true = in_false; @@ -1164,142 +1054,23 @@ static void emit_ia32_CMov(const ir_node *node) ia32_emitf(node, "\tmovl %R, %R\n", in_false, out); } - if (ins_permuted) - pnc = ia32_get_negated_pnc(pnc); - - /* TODO: handling of Nans isn't correct yet */ - - ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out); -} - -/********************************************************* - * _ _ _ - * (_) | (_) - * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___ - * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __| - * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \ - * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/ - * _/ | | | - * |__/ |_| - *********************************************************/ - -/* jump table entry (target and corresponding number) */ -typedef struct _branch_t { - ir_node *target; - int value; -} branch_t; - -/* jump table for switch generation */ -typedef struct _jmp_tbl_t { - ir_node *defProj; /**< default target */ - long min_value; /**< smallest switch case */ - long max_value; /**< largest switch case */ - long num_branches; /**< number of jumps */ - char *label; /**< label of the jump table */ - branch_t *branches; /**< jump array */ -} jmp_tbl_t; - -/** - * Compare two variables of type branch_t. Used to sort all switch cases - */ -static int ia32_cmp_branch_t(const void *a, const void *b) -{ - branch_t *b1 = (branch_t *)a; - branch_t *b2 = (branch_t *)b; + if (cc & ia32_cc_float_parity_cases) { + panic("CMov with floatingpoint compare/parity not supported yet"); + } - if (b1->value <= b2->value) - return -1; - else - return 1; + ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out); } /** - * Emits code for a SwitchJmp (creates a jump table if - * possible otherwise a cmp-jmp cascade). Port from - * cggg ia32 backend + * Emits code for a SwitchJmp */ static void emit_ia32_SwitchJmp(const ir_node *node) { - unsigned long interval; - int last_value, i; - long pnc; - long default_pn; - jmp_tbl_t tbl; - ir_node *proj; - const ir_edge_t *edge; - - /* fill the table structure */ - tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN); - tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_"); - tbl.defProj = NULL; - tbl.num_branches = get_irn_n_edges(node) - 1; - tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches); - tbl.min_value = INT_MAX; - tbl.max_value = INT_MIN; - - default_pn = get_ia32_condcode(node); - i = 0; - /* go over all proj's and collect them */ - foreach_out_edge(node, edge) { - proj = get_edge_src_irn(edge); - assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); - - pnc = get_Proj_proj(proj); - - /* check for default proj */ - if (pnc == default_pn) { - assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp"); - tbl.defProj = proj; - } else { - tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value; - tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value; - - /* create branch entry */ - tbl.branches[i].target = proj; - tbl.branches[i].value = pnc; - ++i; - } - - } - assert(i == tbl.num_branches); - - /* sort the branches by their number */ - qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t); - - /* two-complement's magic make this work without overflow */ - interval = tbl.max_value - tbl.min_value; - - /* emit the table */ - ia32_emitf(node, "\tcmpl $%u, %S0\n", interval); - ia32_emitf(tbl.defProj, "\tja %L\n"); - - if (tbl.num_branches > 1) { - /* create table */ - ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label); - - be_gas_emit_switch_section(GAS_SECTION_RODATA); - ia32_emitf(NULL, "\t.align 4\n"); - ia32_emitf(NULL, "%s:\n", tbl.label); - - last_value = tbl.branches[0].value; - for (i = 0; i != tbl.num_branches; ++i) { - while (last_value != tbl.branches[i].value) { - ia32_emitf(tbl.defProj, ".long %L\n"); - ++last_value; - } - ia32_emitf(tbl.branches[i].target, ".long %L\n"); - ++last_value; - } - be_gas_emit_switch_section(GAS_SECTION_TEXT); - } else { - /* one jump is enough */ - ia32_emitf(tbl.branches[0].target, "\tjmp %L\n"); - } + ir_entity *jump_table = get_ia32_am_sc(node); + long default_pn = get_ia32_default_pn(node); - if (tbl.label) - free(tbl.label); - if (tbl.branches) - free(tbl.branches); + ia32_emitf(node, "\tjmp %*AM\n"); + emit_jump_table(node, default_pn, jump_table, get_cfop_target_block); } /** @@ -1307,11 +1078,6 @@ static void emit_ia32_SwitchJmp(const ir_node *node) */ static void emit_ia32_Jmp(const ir_node *node) { - ir_node *block; - - /* for now, the code works for scheduled and non-schedules blocks */ - block = get_nodes_block(node); - /* we have a block schedule */ if (can_be_fallthrough(node)) { ia32_emitf(node, "\t/* fallthrough to %L */\n"); @@ -1336,17 +1102,16 @@ static const char* emit_asm_operand(const ir_node *node, const char *s) const arch_register_t *reg; const ia32_asm_reg_t *asm_regs = attr->register_map; const ia32_asm_reg_t *asm_reg; - const char *reg_name; char c; char modifier = 0; - int num = -1; + int num; int p; assert(*s == '%'); c = *(++s); /* parse modifiers */ - switch(c) { + switch (c) { case 0: ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node); be_emit_char('%'); @@ -1380,8 +1145,7 @@ static const char* emit_asm_operand(const ir_node *node, const char *s) } /* parse number */ - sscanf(s, "%d%n", &num, &p); - if (num < 0) { + if (sscanf(s, "%d%n", &num, &p) != 1) { ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n", node); return s; @@ -1389,7 +1153,7 @@ static const char* emit_asm_operand(const ir_node *node, const char *s) s += p; } - if (num < 0 || ARR_LEN(asm_regs) <= num) { + if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) { ir_fprintf(stderr, "Error: Custom assembler references invalid input/output (%+F)\n", node); @@ -1400,7 +1164,7 @@ static const char* emit_asm_operand(const ir_node *node, const char *s) /* get register */ if (asm_reg->use_input == 0) { - reg = get_out_reg(node, asm_reg->inout_pos); + reg = arch_get_irn_register_out(node, asm_reg->inout_pos); } else { ir_node *pred = get_irn_n(node, asm_reg->inout_pos); @@ -1409,7 +1173,7 @@ static const char* emit_asm_operand(const ir_node *node, const char *s) emit_ia32_Immediate(pred); return s; } - reg = get_in_reg(node, asm_reg->inout_pos); + reg = arch_get_irn_register_in(node, asm_reg->inout_pos); } if (reg == NULL) { ir_fprintf(stderr, @@ -1424,21 +1188,19 @@ static const char* emit_asm_operand(const ir_node *node, const char *s) /* emit it */ if (modifier != 0) { - be_emit_char('%'); - switch(modifier) { + switch (modifier) { case 'b': - reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg); + emit_8bit_register(reg); break; case 'h': - reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg); + emit_8bit_register_high(reg); break; case 'w': - reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg); + emit_16bit_register(reg); break; default: panic("Invalid asm op modifier"); } - be_emit_string(reg_name); } else { emit_register(reg, asm_reg->mode); } @@ -1466,7 +1228,7 @@ static void emit_ia32_Asm(const ir_node *node) if (s[0] != '\t') be_emit_char('\t'); - while(*s != 0) { + while (*s != 0) { if (*s == '%') { s = emit_asm_operand(node, s); } else { @@ -1477,16 +1239,6 @@ static void emit_ia32_Asm(const ir_node *node) ia32_emitf(NULL, "\n#NO_APP\n"); } -/********************************** - * _____ ____ - * / ____| | _ \ - * | | ___ _ __ _ _| |_) | - * | | / _ \| '_ \| | | | _ < - * | |___| (_) | |_) | |_| | |_) | - * \_____\___/| .__/ \__, |____/ - * | | __/ | - * |_| |___/ - **********************************/ /** * Emit movsb/w instructions to make mov count divideable by 4 @@ -1526,17 +1278,6 @@ static void emit_ia32_CopyB_i(const ir_node *node) } - -/*************************** - * _____ - * / ____| - * | | ___ _ ____ __ - * | | / _ \| '_ \ \ / / - * | |___| (_) | | | \ V / - * \_____\___/|_| |_|\_/ - * - ***************************/ - /** * Emit code for conversions (I, FP), (FP, I) and (FP, FP). */ @@ -1570,8 +1311,8 @@ static void emit_ia32_Conv_FP2FP(const ir_node *node) */ static void emit_ia32_Conv_I2I(const ir_node *node) { - ir_mode *smaller_mode = get_ia32_ls_mode(node); - int signed_mode = mode_is_signed(smaller_mode); + ir_mode *smaller_mode = get_ia32_ls_mode(node); + int signed_mode = mode_is_signed(smaller_mode); const char *sign_suffix; assert(!mode_is_float(smaller_mode)); @@ -1591,16 +1332,6 @@ static void emit_ia32_Call(const ir_node *node) } -/******************************************* - * _ _ - * | | | | - * | |__ ___ _ __ ___ __| | ___ ___ - * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __| - * | |_) | __/ | | | (_) | (_| | __/\__ \ - * |_.__/ \___|_| |_|\___/ \__,_|\___||___/ - * - *******************************************/ - /** * Emits code to increase stack pointer. */ @@ -1618,16 +1349,6 @@ static void emit_be_IncSP(const ir_node *node) } } -static inline bool is_unknown_reg(const arch_register_t *reg) -{ - if(reg == &ia32_gp_regs[REG_GP_UKNWN] - || reg == &ia32_xmm_regs[REG_XMM_UKNWN] - || reg == &ia32_vfp_regs[REG_VFP_UKNWN]) - return true; - - return false; -} - /** * Emits code for Copy/CopyKeep. */ @@ -1639,8 +1360,6 @@ static void Copy_emitter(const ir_node *node, const ir_node *op) if (in == out) { return; } - if (is_unknown_reg(in)) - return; /* copies of vf nodes aren't real... */ if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp]) return; @@ -1701,14 +1420,6 @@ static void emit_ia32_Const(const ir_node *node) ia32_emitf(node, "\tmovl %I, %D0\n"); } -/** - * Emits code to load the TLS base - */ -static void emit_ia32_LdTls(const ir_node *node) -{ - ia32_emitf(node, "\tmovl %%gs:0, %D0\n"); -} - /* helper function for emit_ia32_Minus64Bit */ static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst) { @@ -1747,10 +1458,10 @@ static void emit_zero(const ir_node* node, const arch_register_t *reg) static void emit_ia32_Minus64Bit(const ir_node *node) { - const arch_register_t *in_lo = get_in_reg(node, 0); - const arch_register_t *in_hi = get_in_reg(node, 1); - const arch_register_t *out_lo = get_out_reg(node, 0); - const arch_register_t *out_hi = get_out_reg(node, 1); + const arch_register_t *in_lo = arch_get_irn_register_in(node, 0); + const arch_register_t *in_hi = arch_get_irn_register_in(node, 1); + const arch_register_t *out_lo = arch_get_irn_register_out(node, 0); + const arch_register_t *out_hi = arch_get_irn_register_out(node, 1); if (out_lo == in_lo) { if (out_hi != in_hi) { @@ -1812,10 +1523,14 @@ static void emit_ia32_ClimbFrame(const ir_node *node) ia32_emitf(node, "\tmovl %S0, %D0\n"); ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count); - ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node)); + be_gas_emit_block_name(node); + be_emit_cstring(":\n"); + be_emit_write_line(); ia32_emitf(node, "\tmovl (%D0), %D0\n"); ia32_emitf(node, "\tdec %S1\n"); - ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node)); + be_emit_cstring("\tjnz "); + be_gas_emit_block_name(node); + be_emit_finish_line_gas(node); } static void emit_be_Return(const ir_node *node) @@ -1835,16 +1550,6 @@ static void emit_Nothing(const ir_node *node) } -/*********************************************************************************** - * _ __ _ - * (_) / _| | | - * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __ - * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ / - * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | < - * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\ - * - ***********************************************************************************/ - /** * Enters the emitter functions for handled nodes into the generic * pointer of an opcode. @@ -1854,9 +1559,9 @@ static void ia32_register_emitters(void) #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b #define IA32_EMIT(a) IA32_EMIT2(a,a) #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a -#define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing +#define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a -#define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing +#define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing /* first clear the generic function pointer for all ops */ clear_irp_opcodes_generic_func(); @@ -1867,7 +1572,7 @@ static void ia32_register_emitters(void) /* other ia32 emitter functions */ IA32_EMIT2(Conv_I2I8Bit, Conv_I2I); IA32_EMIT(Asm); - IA32_EMIT(CMov); + IA32_EMIT(CMovcc); IA32_EMIT(Call); IA32_EMIT(Const); IA32_EMIT(Conv_FP2FP); @@ -1879,7 +1584,7 @@ static void ia32_register_emitters(void) IA32_EMIT(GetEIP); IA32_EMIT(IMul); IA32_EMIT(Jcc); - IA32_EMIT(LdTls); + IA32_EMIT(Setcc); IA32_EMIT(Minus64Bit); IA32_EMIT(SwitchJmp); IA32_EMIT(ClimbFrame); @@ -1892,7 +1597,6 @@ static void ia32_register_emitters(void) BE_EMIT(Perm); BE_EMIT(Return); - BE_IGN(Barrier); BE_IGN(Keep); BE_IGN(Start); @@ -1991,7 +1695,8 @@ static void ia32_emit_align_label(void) static int should_align_block(const ir_node *block) { static const double DELTA = .0001; - ir_exec_freq *exec_freq = cg->birg->exec_freq; + ir_graph *irg = get_irn_irg(block); + ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg); ir_node *prev = get_prev_block_sched(block); double block_freq; double prev_freq = 0; /**< execfreq of the fallthrough block */ @@ -2008,7 +1713,7 @@ static int should_align_block(const ir_node *block) return 0; n_cfgpreds = get_Block_n_cfgpreds(block); - for(i = 0; i < n_cfgpreds; ++i) { + for (i = 0; i < n_cfgpreds; ++i) { const ir_node *pred = get_Block_cfgpred_block(block, i); double pred_freq = get_block_execfreq(exec_freq, pred); @@ -2035,10 +1740,10 @@ static int should_align_block(const ir_node *block) */ static void ia32_emit_block_header(ir_node *block) { - ir_graph *irg = current_ir_graph; + ir_graph *irg = current_ir_graph; int need_label = block_needs_label(block); - int i, arity; - ir_exec_freq *exec_freq = cg->birg->exec_freq; + ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg); + int arity; if (block == get_irg_end_block(irg)) return; @@ -2070,14 +1775,14 @@ static void ia32_emit_block_header(ir_node *block) } if (need_label) { - ia32_emit_block_name(block); + be_gas_emit_block_name(block); be_emit_char(':'); be_emit_pad_comment(); be_emit_cstring(" /* "); } else { be_emit_cstring("\t/* "); - ia32_emit_block_name(block); + be_gas_emit_block_name(block); be_emit_cstring(": "); } @@ -2088,6 +1793,7 @@ static void ia32_emit_block_header(ir_node *block) if (arity <= 0) { be_emit_cstring(" none"); } else { + int i; for (i = 0; i < arity; ++i) { ir_node *predblock = get_Block_cfgpred_block(block, i); be_emit_irprintf(" %d", get_irn_node_nr(predblock)); @@ -2130,7 +1836,7 @@ typedef struct exc_entry { */ static void ia32_gen_labels(ir_node *block, void *data) { - exc_entry **exc_list = data; + exc_entry **exc_list = (exc_entry**)data; ir_node *pred; int n; @@ -2155,8 +1861,8 @@ static void ia32_gen_labels(ir_node *block, void *data) */ static int cmp_exc_entry(const void *a, const void *b) { - const exc_entry *ea = a; - const exc_entry *eb = b; + const exc_entry *ea = (const exc_entry*)a; + const exc_entry *eb = (const exc_entry*)b; if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr)) return -1; @@ -2166,21 +1872,25 @@ static int cmp_exc_entry(const void *a, const void *b) /** * Main driver. Emits the code for one routine. */ -void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg) +void ia32_gen_routine(ir_graph *irg) { - ir_entity *entity = get_irg_entity(irg); - exc_entry *exc_list = NEW_ARR_F(exc_entry, 0); + ir_entity *entity = get_irg_entity(irg); + exc_entry *exc_list = NEW_ARR_F(exc_entry, 0); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_irg_data_t *irg_data = ia32_get_irg_data(irg); + ir_node **blk_sched = irg_data->blk_sched; int i, n; - cg = ia32_cg; - isa = cg->isa; - do_pic = cg->birg->main_env->options->pic; + isa = (ia32_isa_t*) arch_env; + do_pic = be_get_irg_options(irg)->pic; + + be_gas_elf_type_char = '@'; ia32_register_emitters(); - get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE"); + get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE"); - be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi)); + be_dbg_method_begin(entity); be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment); /* we use links to point to target blocks */ @@ -2188,16 +1898,16 @@ void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg) irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list); /* initialize next block links */ - n = ARR_LEN(cg->blk_sched); + n = ARR_LEN(blk_sched); for (i = 0; i < n; ++i) { - ir_node *block = cg->blk_sched[i]; - ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL; + ir_node *block = blk_sched[i]; + ir_node *prev = i > 0 ? blk_sched[i-1] : NULL; set_irn_link(block, prev); } for (i = 0; i < n; ++i) { - ir_node *block = cg->blk_sched[i]; + ir_node *block = blk_sched[i]; ia32_gen_block(block); } @@ -2213,14 +1923,14 @@ void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg) Those are ascending with ascending addresses. */ qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry); { - int i; + size_t e; - for (i = 0; i < ARR_LEN(exc_list); ++i) { + for (e = 0; e < ARR_LEN(exc_list); ++e) { be_emit_cstring("\t.long "); - ia32_emit_exc_label(exc_list[i].exc_instr); + ia32_emit_exc_label(exc_list[e].exc_instr); be_emit_char('\n'); be_emit_cstring("\t.long "); - ia32_emit_block_name(exc_list[i].block); + be_gas_emit_block_name(exc_list[e].block); be_emit_char('\n'); } } @@ -2235,38 +1945,26 @@ static const lc_opt_table_entry_t ia32_emitter_options[] = { /* ==== Experimental binary emitter ==== */ static unsigned char reg_gp_map[N_ia32_gp_REGS]; -static unsigned char reg_mmx_map[N_ia32_mmx_REGS]; -static unsigned char reg_sse_map[N_ia32_xmm_REGS]; -static unsigned char pnc_map_signed[8]; -static unsigned char pnc_map_unsigned[8]; +//static unsigned char reg_mmx_map[N_ia32_mmx_REGS]; +//static unsigned char reg_sse_map[N_ia32_xmm_REGS]; static void build_reg_map(void) { - reg_gp_map[REG_EAX] = 0x0; - reg_gp_map[REG_ECX] = 0x1; - reg_gp_map[REG_EDX] = 0x2; - reg_gp_map[REG_EBX] = 0x3; - reg_gp_map[REG_ESP] = 0x4; - reg_gp_map[REG_EBP] = 0x5; - reg_gp_map[REG_ESI] = 0x6; - reg_gp_map[REG_EDI] = 0x7; - - pnc_map_signed[pn_Cmp_Eq] = 0x04; - pnc_map_signed[pn_Cmp_Lt] = 0x0C; - pnc_map_signed[pn_Cmp_Le] = 0x0E; - pnc_map_signed[pn_Cmp_Gt] = 0x0F; - pnc_map_signed[pn_Cmp_Ge] = 0x0D; - pnc_map_signed[pn_Cmp_Ne] = 0x05; - - pnc_map_unsigned[pn_Cmp_Eq] = 0x04; - pnc_map_unsigned[pn_Cmp_Lt] = 0x02; - pnc_map_unsigned[pn_Cmp_Le] = 0x06; - pnc_map_unsigned[pn_Cmp_Gt] = 0x07; - pnc_map_unsigned[pn_Cmp_Ge] = 0x03; - pnc_map_unsigned[pn_Cmp_Ne] = 0x05; + reg_gp_map[REG_GP_EAX] = 0x0; + reg_gp_map[REG_GP_ECX] = 0x1; + reg_gp_map[REG_GP_EDX] = 0x2; + reg_gp_map[REG_GP_EBX] = 0x3; + reg_gp_map[REG_GP_ESP] = 0x4; + reg_gp_map[REG_GP_EBP] = 0x5; + reg_gp_map[REG_GP_ESI] = 0x6; + reg_gp_map[REG_GP_EDI] = 0x7; } -#define GET_MODE(code) ((code) & 0xC0) +/** Returns the encoding for a pnc field. */ +static unsigned char pnc2cc(ia32_condition_code_t cc) +{ + return cc & 0xf; +} /** Sign extension bit values for binops */ enum SignExt { @@ -2287,12 +1985,8 @@ enum Mod { /** create REG encoding for ModR/M */ #define ENC_REG(x) ((x) << 3) -/** create Base encoding for SIB */ -#define ENC_BASE(x) (x) -/** create Index encoding for SIB */ -#define ENC_INDEX(x) ((x) << 3) -/** create Scale encoding for SIB */ -#define ENC_SCALE(x) ((x) << 6) +/** create encoding for a SIB byte */ +#define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base)) /* Node: The following routines are supposed to append bytes, words, dwords to the output stream. @@ -2307,7 +2001,7 @@ static void bemit8(const unsigned char byte) be_emit_write_line(); } -static void bemit16(const unsigned u16) +static void bemit16(const unsigned short u16) { be_emit_irprintf("\t.word 0x%x\n", u16); be_emit_write_line(); @@ -2331,20 +2025,24 @@ static void bemit_entity(ir_entity *entity, bool entity_sign, int offset, return; } - if (is_relative) { - offset -= 4; - } - /* the final version should remember the position in the bytestream and patch it with the correct address at linktime... */ be_emit_cstring("\t.long "); if (entity_sign) be_emit_char('-'); - set_entity_backend_marked(entity, 1); be_gas_emit_entity(entity); + if (get_entity_owner(entity) == get_tls_type()) { + if (get_entity_visibility(entity) == ir_visibility_external) { + be_emit_cstring("@INDNTPOFF"); + } else { + be_emit_cstring("@NTPOFF"); + } + } + if (is_relative) { be_emit_cstring("-."); + offset -= 4; } if (offset != 0) { @@ -2357,13 +2055,19 @@ static void bemit_entity(ir_entity *entity, bool entity_sign, int offset, static void bemit_jmp_destination(const ir_node *dest_block) { be_emit_cstring("\t.long "); - ia32_emit_block_name(dest_block); - be_emit_cstring(" - . - 4"); + be_gas_emit_block_name(dest_block); + be_emit_cstring(" - . - 4\n"); + be_emit_write_line(); } /* end emit routines, all emitters following here should only use the functions above. */ +typedef enum reg_modifier { + REG_LOW = 0, + REG_HIGH = 1 +} reg_modifier_t; + /** Create a ModR/M byte for src1,src2 registers */ static void bemit_modrr(const arch_register_t *src1, const arch_register_t *src2) @@ -2374,6 +2078,16 @@ static void bemit_modrr(const arch_register_t *src1, bemit8(modrm); } +/** Create a ModR/M8 byte for src1,src2 registers */ +static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1, + reg_modifier_t high_part2, const arch_register_t *src2) +{ + unsigned char modrm = MOD_REG; + modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0)); + modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0)); + bemit8(modrm); +} + /** Create a ModR/M byte for one register and extension */ static void bemit_modru(const arch_register_t *reg, unsigned ext) { @@ -2384,20 +2098,14 @@ static void bemit_modru(const arch_register_t *reg, unsigned ext) bemit8(modrm); } -/** - * Calculate the size of an (unsigned) immediate in bytes. - * - * @param offset an offset - */ -static unsigned get_unsigned_imm_size(unsigned offset) +/** Create a ModR/M8 byte for one register */ +static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg) { - if (offset < 256) { - return 1; - } else if (offset < 65536) { - return 2; - } else { - return 4; - } + unsigned char modrm = MOD_REG; + assert(reg_gp_map[reg->index] < 4); + modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0)); + modrm |= MOD_REG; + bemit8(modrm); } /** @@ -2416,53 +2124,6 @@ static unsigned get_signed_imm_size(int offset) } } -/** - * Emit a binop with a immediate operand. - * - * @param node the node to emit - * @param opcode_eax the opcode for the op eax, imm variant - * @param opcode the opcode for the reg, imm variant - * @param ruval the opcode extension for opcode - */ -static void bemit_binop_with_imm( - const ir_node *node, - unsigned char opcode_ax, - unsigned char opcode, unsigned char ruval) -{ - /* Use in-reg, because some instructions (cmp, test) have no out-reg. */ - const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left); - const ir_node *op = get_irn_n(node, n_ia32_binary_right); - const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op); - unsigned size; - - if (attr->symconst != NULL) - size = 4; - else { - /* check for sign extension */ - size = get_signed_imm_size(attr->offset); - } - - switch (size) { - case 1: - bemit8(opcode | SIGNEXT_IMM); - bemit_modru(reg, ruval); - bemit8((unsigned char)attr->offset); - return; - case 2: - case 4: - /* check for eax variant: this variant is shorter for 32bit immediates only */ - if (reg->index == REG_EAX) { - bemit8(opcode_ax); - } else { - bemit8(opcode); - bemit_modru(reg, ruval); - } - bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); - return; - } - panic("invalid imm size?!?"); -} - /** * Emit an address mode. * @@ -2475,12 +2136,13 @@ static void bemit_mod_am(unsigned reg, const ir_node *node) int offs = get_ia32_am_offs_int(node); ir_node *base = get_irn_n(node, n_ia32_base); int has_base = !is_ia32_NoReg_GP(base); - ir_node *index = get_irn_n(node, n_ia32_index); - int has_index = !is_ia32_NoReg_GP(index); + ir_node *idx = get_irn_n(node, n_ia32_index); + int has_index = !is_ia32_NoReg_GP(idx); unsigned modrm = 0; unsigned sib = 0; unsigned emitoffs = 0; bool emitsib = false; + unsigned base_enc; /* set the mod part depending on displacement */ if (ent != NULL) { @@ -2497,53 +2159,42 @@ static void bemit_mod_am(unsigned reg, const ir_node *node) emitoffs = 32; } - /* determine if we need a SIB byte */ - if (has_index) { - int scale; - const arch_register_t *reg_index = arch_get_irn_register(index); - assert(reg_index->index != REG_ESP); - sib |= ENC_INDEX(reg_gp_map[reg_index->index]); - - if (has_base) { - const arch_register_t *base_reg = arch_get_irn_register(base); - sib |= ENC_BASE(reg_gp_map[base_reg->index]); - } else { - /* use the EBP encoding if NO base register */ - sib |= 0x05; - } + if (has_base) { + const arch_register_t *base_reg = arch_get_irn_register(base); + base_enc = reg_gp_map[base_reg->index]; + } else { + /* Use the EBP encoding + MOD_IND if NO base register. There is + * always a 32bit offset present in this case. */ + modrm = MOD_IND; + base_enc = 0x05; + emitoffs = 32; + } - scale = get_ia32_am_scale(node); + /* Determine if we need a SIB byte. */ + if (has_index) { + const arch_register_t *reg_index = arch_get_irn_register(idx); + int scale = get_ia32_am_scale(node); assert(scale < 4); - sib |= ENC_SCALE(scale); + /* R/M set to ESP means SIB in 32bit mode. */ + modrm |= ENC_RM(0x04); + sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc); emitsib = true; + } else if (base_enc == 0x04) { + /* for the above reason we are forced to emit a SIB when base is ESP. + * Only the base is used, index must be ESP too, which means no index. + */ + modrm |= ENC_RM(0x04); + sib = ENC_SIB(0, 0x04, 0x04); + emitsib = true; + } else { + modrm |= ENC_RM(base_enc); } - /* determine modrm byte */ - if (emitsib) { - /* R/M set to ESP means SIB in 32bit mode */ - modrm |= ENC_RM(0x04); - } else if (has_base) { - const arch_register_t *base_reg = arch_get_irn_register(base); - if (base_reg->index == REG_ESP) { - /* for the above reason we are forced to emit a sib when base is - * ESP. Only the base is used, index must be ESP too, which means no - * index. */ - sib = ENC_BASE(0x04) | ENC_INDEX(0x04); - emitsib = true; - - /* we are forced to emit a 8bit offset as EBP base without - offset is a special case for SIB without base register */ - } else if (base_reg->index == REG_EBP && emitoffs == 0) { - assert(GET_MODE(modrm) == MOD_IND); - emitoffs = 8; - modrm |= MOD_IND_BYTE_OFS; - } - - modrm |= ENC_RM(reg_gp_map[base_reg->index]); - } else { - /* only displacement: Use EBP + disp encoding in 32bit mode */ - emitoffs = 32; - modrm = ENC_RM(0x05); + /* We are forced to emit an 8bit offset as EBP base without offset is a + * special case for SIB without base register. */ + if (base_enc == 0x05 && emitoffs == 0) { + modrm |= MOD_IND_BYTE_OFS; + emitoffs = 8; } modrm |= ENC_REG(reg); @@ -2560,31 +2211,79 @@ static void bemit_mod_am(unsigned reg, const ir_node *node) } } +/** + * Emit a binop with a immediate operand. + * + * @param node the node to emit + * @param opcode_eax the opcode for the op eax, imm variant + * @param opcode the opcode for the reg, imm variant + * @param ruval the opcode extension for opcode + */ +static void bemit_binop_with_imm( + const ir_node *node, + unsigned char opcode_ax, + unsigned char opcode, unsigned char ruval) +{ + /* Use in-reg, because some instructions (cmp, test) have no out-reg. */ + const ir_node *op = get_irn_n(node, n_ia32_binary_right); + const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op); + unsigned size; + + /* Some instructions (test) have no short form with 32bit value + 8bit + * immediate. */ + if (attr->symconst != NULL || opcode & SIGNEXT_IMM) { + size = 4; + } else { + /* check for sign extension */ + size = get_signed_imm_size(attr->offset); + } + + switch (size) { + case 1: + bemit8(opcode | SIGNEXT_IMM); + /* cmp has this special mode */ + if (get_ia32_op_type(node) == ia32_AddrModeS) { + bemit_mod_am(ruval, node); + } else { + const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left); + bemit_modru(reg, ruval); + } + bemit8((unsigned char)attr->offset); + return; + case 2: + case 4: + /* check for eax variant: this variant is shorter for 32bit immediates only */ + if (get_ia32_op_type(node) == ia32_AddrModeS) { + bemit8(opcode); + bemit_mod_am(ruval, node); + } else { + const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left); + if (reg->index == REG_GP_EAX) { + bemit8(opcode_ax); + } else { + bemit8(opcode); + bemit_modru(reg, ruval); + } + } + bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); + return; + } + panic("invalid imm size?!?"); +} + /** * Emits a binop. */ static void bemit_binop_2(const ir_node *node, unsigned code) { - const arch_register_t *out = get_in_reg(node, n_ia32_binary_left); - ia32_op_type_t am_type = get_ia32_op_type(node); - unsigned char d = 0; - const arch_register_t *op2; - - switch (am_type) { - case ia32_AddrModeS: - d = 2; - /* FALLTHROUGH */ - case ia32_AddrModeD: - bemit8(code | d); + const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left); + bemit8(code); + if (get_ia32_op_type(node) == ia32_Normal) { + const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right); + bemit_modrr(op2, out); + } else { bemit_mod_am(reg_gp_map[out->index], node); - return; - case ia32_Normal: - bemit8(code); - op2 = get_in_reg(node, n_ia32_binary_right); - bemit_modrr(out, op2); - return; } - panic("invalid address mode"); } /** @@ -2605,19 +2304,29 @@ static void bemit_binop(const ir_node *node, const unsigned char opcodes[4]) */ static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input) { - ia32_op_type_t am_type = get_ia32_op_type(node); - bemit8(code); - if (am_type == ia32_AddrModeD) { - bemit8(code); - bemit_mod_am(ext, node); - } else { - const arch_register_t *in = get_in_reg(node, input); - assert(am_type == ia32_Normal); + if (get_ia32_op_type(node) == ia32_Normal) { + const arch_register_t *in = arch_get_irn_register_in(node, input); bemit_modru(in, ext); + } else { + bemit_mod_am(ext, node); } } +static void bemit_unop_reg(const ir_node *node, unsigned char code, int input) +{ + const arch_register_t *out = arch_get_irn_register_out(node, 0); + bemit_unop(node, code, reg_gp_map[out->index], input); +} + +static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext) +{ + unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); + if (size == 16) + bemit8(0x66); + bemit8(size == 8 ? code : code + 1); + bemit_mod_am(ext, node); +} static void bemit_immediate(const ir_node *node, bool relative) { @@ -2627,11 +2336,10 @@ static void bemit_immediate(const ir_node *node, bool relative) static void bemit_copy(const ir_node *copy) { - const ir_node *op = be_get_Copy_op(copy); - const arch_register_t *in = arch_get_irn_register(op); - const arch_register_t *out = arch_get_irn_register(copy); + const arch_register_t *in = arch_get_irn_register_in(copy, 0); + const arch_register_t *out = arch_get_irn_register_out(copy, 0); - if (in == out || is_unknown_reg(in)) + if (in == out) return; /* copies of vf nodes aren't real... */ if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp]) @@ -2641,21 +2349,52 @@ static void bemit_copy(const ir_node *copy) panic("NIY"); } else { assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]); - bemit8(0x89); - bemit_modrr(out, in); + bemit8(0x8B); + bemit_modrr(in, out); + } +} + +static void bemit_perm(const ir_node *node) +{ + const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0)); + const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1)); + const arch_register_class_t *cls0 = arch_register_get_class(in0); + + assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm"); + + if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) { + if (in0->index == REG_GP_EAX) { + bemit8(0x90 + reg_gp_map[in1->index]); + } else if (in1->index == REG_GP_EAX) { + bemit8(0x90 + reg_gp_map[in0->index]); + } else { + bemit8(0x87); + bemit_modrr(in0, in1); + } + } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) { + panic("unimplemented"); // TODO implement + //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0); + //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1); + //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0); + } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) { + /* is a NOP */ + } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) { + /* is a NOP */ + } else { + panic("unexpected register class in be_Perm (%+F)", node); } } static void bemit_xor0(const ir_node *node) { - const arch_register_t *out = get_out_reg(node, 0); + const arch_register_t *out = arch_get_irn_register_out(node, 0); bemit8(0x31); bemit_modrr(out, out); } static void bemit_mov_const(const ir_node *node) { - const arch_register_t *out = get_out_reg(node, 0); + const arch_register_t *out = arch_get_irn_register_out(node, 0); bemit8(0xB8 + reg_gp_map[out->index]); bemit_immediate(node, false); } @@ -2669,15 +2408,65 @@ static void bemit_ ## op(const ir_node *node) { \ bemit_binop(node, op ## _codes); \ } -/* insn def eax,imm imm */ -BINOP(add, 0x01, 0x05, 0x81, 0 ) -BINOP(or, 0x09, 0x0D, 0x81, 1 ) -BINOP(adc, 0x11, 0x15, 0x81, 2 ) -BINOP(sbb, 0x19, 0x1D, 0x81, 3 ) -BINOP(and, 0x21, 0x25, 0x81, 4 ) -BINOP(sub, 0x29, 0x2D, 0x81, 5 ) -BINOP(xor, 0x31, 0x35, 0x81, 6 ) -BINOP(cmp, 0x39, 0x3D, 0x81, 7 ) +/* insn def eax,imm imm */ +BINOP(add, 0x03, 0x05, 0x81, 0) +BINOP(or, 0x0B, 0x0D, 0x81, 1) +BINOP(adc, 0x13, 0x15, 0x81, 2) +BINOP(sbb, 0x1B, 0x1D, 0x81, 3) +BINOP(and, 0x23, 0x25, 0x81, 4) +BINOP(sub, 0x2B, 0x2D, 0x81, 5) +BINOP(xor, 0x33, 0x35, 0x81, 6) +BINOP(test, 0x85, 0xA9, 0xF7, 0) + +#define BINOPMEM(op, ext) \ +static void bemit_##op(const ir_node *node) \ +{ \ + ir_node *val; \ + unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \ + if (size == 16) \ + bemit8(0x66); \ + val = get_irn_n(node, n_ia32_unary_op); \ + if (is_ia32_Immediate(val)) { \ + const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \ + int offset = attr->offset; \ + if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \ + bemit8(0x83); \ + bemit_mod_am(ext, node); \ + bemit8(offset); \ + } else { \ + bemit8(0x81); \ + bemit_mod_am(ext, node); \ + if (size == 16) { \ + bemit16(offset); \ + } else { \ + bemit_entity(attr->symconst, attr->sc_sign, offset, false); \ + } \ + } \ + } else { \ + bemit8(ext << 3 | 1); \ + bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \ + } \ +} \ + \ +static void bemit_##op##8bit(const ir_node *node) \ +{ \ + ir_node *val = get_irn_n(node, n_ia32_unary_op); \ + if (is_ia32_Immediate(val)) { \ + bemit8(0x80); \ + bemit_mod_am(ext, node); \ + bemit8(get_ia32_immediate_attr_const(val)->offset); \ + } else { \ + bemit8(ext << 3); \ + bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \ + } \ +} + +BINOPMEM(addmem, 0) +BINOPMEM(ormem, 1) +BINOPMEM(andmem, 4) +BINOPMEM(submem, 5) +BINOPMEM(xormem, 6) + /** * Creates a function for an Unop with code /ext encoding. @@ -2687,19 +2476,20 @@ static void bemit_ ## op(const ir_node *node) { \ bemit_unop(node, code, ext, input); \ } -UNOP(not, 0xF7, 2, n_ia32_unary_op) -UNOP(neg, 0xF7, 3, n_ia32_unary_op) -UNOP(mul, 0xF7, 4, n_ia32_binary_right) -UNOP(imul1op, 0xF7, 5, n_ia32_binary_right) -UNOP(div, 0xF7, 6, n_ia32_unary_op) -UNOP(idiv, 0xF7, 7, n_ia32_unary_op) +UNOP(not, 0xF7, 2, n_ia32_Not_val) +UNOP(neg, 0xF7, 3, n_ia32_Neg_val) +UNOP(mul, 0xF7, 4, n_ia32_Mul_right) +UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right) +UNOP(div, 0xF7, 6, n_ia32_Div_divisor) +UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor) -UNOP(ijmp, 0xFF, 4, n_ia32_unary_op) +/* TODO: am support for IJmp */ +UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target) #define SHIFT(op, ext) \ static void bemit_##op(const ir_node *node) \ { \ - const arch_register_t *out = get_out_reg(node, 0); \ + const arch_register_t *out = arch_get_irn_register_out(node, 0); \ ir_node *count = get_irn_n(node, 1); \ if (is_ia32_Immediate(count)) { \ int offset = get_ia32_immediate_attr_const(count)->offset; \ @@ -2715,6 +2505,29 @@ static void bemit_##op(const ir_node *node) \ bemit8(0xD3); \ bemit_modru(out, ext); \ } \ +} \ + \ +static void bemit_##op##mem(const ir_node *node) \ +{ \ + ir_node *count; \ + unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \ + if (size == 16) \ + bemit8(0x66); \ + count = get_irn_n(node, 1); \ + if (is_ia32_Immediate(count)) { \ + int offset = get_ia32_immediate_attr_const(count)->offset; \ + if (offset == 1) { \ + bemit8(size == 8 ? 0xD0 : 0xD1); \ + bemit_mod_am(ext, node); \ + } else { \ + bemit8(size == 8 ? 0xC0 : 0xC1); \ + bemit_mod_am(ext, node); \ + bemit8(offset); \ + } \ + } else { \ + bemit8(size == 8 ? 0xD2 : 0xD3); \ + bemit_mod_am(ext, node); \ + } \ } SHIFT(rol, 0) @@ -2723,30 +2536,425 @@ SHIFT(shl, 4) SHIFT(shr, 5) SHIFT(sar, 7) +static void bemit_shld(const ir_node *node) +{ + const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low); + const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res); + ir_node *count = get_irn_n(node, n_ia32_ShlD_count); + bemit8(0x0F); + if (is_ia32_Immediate(count)) { + bemit8(0xA4); + bemit_modrr(out, in); + bemit8(get_ia32_immediate_attr_const(count)->offset); + } else { + bemit8(0xA5); + bemit_modrr(out, in); + } +} + +static void bemit_shrd(const ir_node *node) +{ + const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low); + const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res); + ir_node *count = get_irn_n(node, n_ia32_ShrD_count); + bemit8(0x0F); + if (is_ia32_Immediate(count)) { + bemit8(0xAC); + bemit_modrr(out, in); + bemit8(get_ia32_immediate_attr_const(count)->offset); + } else { + bemit8(0xAD); + bemit_modrr(out, in); + } +} + +/** + * binary emitter for setcc. + */ +static void bemit_setcc(const ir_node *node) +{ + const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res); + + ia32_condition_code_t cc = get_ia32_condcode(node); + cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc); + if (cc & ia32_cc_float_parity_cases) { + if (cc & ia32_cc_negated) { + /* set%PNC dreg */ + bemit8(0x0F); + bemit8(0x9A); + bemit_modrm8(REG_HIGH, dreg); + + /* orb %>dreg, %dreg */ + bemit8(0x0F); + bemit8(0x9B); + bemit_modrm8(REG_HIGH, dreg); + + /* andb %>dreg, %data.ins_permuted; + const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res); + ia32_condition_code_t cc = get_ia32_condcode(node); + const arch_register_t *in_true; + const arch_register_t *in_false; + + cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc); + + in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true)); + in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false)); + + /* should be same constraint fullfilled? */ + if (out == in_false) { + /* yes -> nothing to do */ + } else if (out == in_true) { + assert(get_ia32_op_type(node) == ia32_Normal); + ins_permuted = !ins_permuted; + in_true = in_false; + } else { + /* we need a mov */ + bemit8(0x8B); // mov %in_false, %out + bemit_modrr(in_false, out); + } + + if (ins_permuted) + cc = ia32_negate_condition_code(cc); + + if (cc & ia32_cc_float_parity_cases) + panic("cmov can't handle parity float cases"); + + bemit8(0x0F); + bemit8(0x40 | pnc2cc(cc)); + if (get_ia32_op_type(node) == ia32_Normal) { + bemit_modrr(in_true, out); + } else { + bemit_mod_am(reg_gp_map[out->index], node); + } +} + +static void bemit_cmp(const ir_node *node) +{ + unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node)); + ir_node *right; + + if (ls_size == 16) + bemit8(0x66); + + right = get_irn_n(node, n_ia32_binary_right); + if (is_ia32_Immediate(right)) { + /* Use in-reg, because some instructions (cmp, test) have no out-reg. */ + const ir_node *op = get_irn_n(node, n_ia32_binary_right); + const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op); + unsigned size; + + if (attr->symconst != NULL) { + size = 4; + } else { + /* check for sign extension */ + size = get_signed_imm_size(attr->offset); + } + + switch (size) { + case 1: + bemit8(0x81 | SIGNEXT_IMM); + /* cmp has this special mode */ + if (get_ia32_op_type(node) == ia32_AddrModeS) { + bemit_mod_am(7, node); + } else { + const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left); + bemit_modru(reg, 7); + } + bemit8((unsigned char)attr->offset); + return; + case 2: + case 4: + /* check for eax variant: this variant is shorter for 32bit immediates only */ + if (get_ia32_op_type(node) == ia32_AddrModeS) { + bemit8(0x81); + bemit_mod_am(7, node); + } else { + const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left); + if (reg->index == REG_GP_EAX) { + bemit8(0x3D); + } else { + bemit8(0x81); + bemit_modru(reg, 7); + } + } + if (ls_size == 16) { + bemit16(attr->offset); + } else { + bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); + } + return; + } + panic("invalid imm size?!?"); + } else { + const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left); + bemit8(0x3B); + if (get_ia32_op_type(node) == ia32_Normal) { + const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right); + bemit_modrr(op2, out); + } else { + bemit_mod_am(reg_gp_map[out->index], node); + } + } +} + +static void bemit_cmp8bit(const ir_node *node) +{ + ir_node *right = get_irn_n(node, n_ia32_binary_right); + if (is_ia32_Immediate(right)) { + if (get_ia32_op_type(node) == ia32_Normal) { + const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left); + if (out->index == REG_GP_EAX) { + bemit8(0x3C); + } else { + bemit8(0x80); + bemit_modru(out, 7); + } + } else { + bemit8(0x80); + bemit_mod_am(7, node); + } + bemit8(get_ia32_immediate_attr_const(right)->offset); + } else { + const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left); + bemit8(0x3A); + if (get_ia32_op_type(node) == ia32_Normal) { + const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right); + bemit_modrr(out, in); + } else { + bemit_mod_am(reg_gp_map[out->index], node); + } + } +} + +static void bemit_test8bit(const ir_node *node) +{ + ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right); + if (is_ia32_Immediate(right)) { + if (get_ia32_op_type(node) == ia32_Normal) { + const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left); + if (out->index == REG_GP_EAX) { + bemit8(0xA8); + } else { + bemit8(0xF6); + bemit_modru(out, 0); + } + } else { + bemit8(0xF6); + bemit_mod_am(0, node); + } + bemit8(get_ia32_immediate_attr_const(right)->offset); + } else { + const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left); + bemit8(0x84); + if (get_ia32_op_type(node) == ia32_Normal) { + const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right); + bemit_modrr(out, in); + } else { + bemit_mod_am(reg_gp_map[out->index], node); + } + } +} + +static void bemit_imul(const ir_node *node) +{ + ir_node *right = get_irn_n(node, n_ia32_IMul_right); + /* Do we need the immediate form? */ + if (is_ia32_Immediate(right)) { + int imm = get_ia32_immediate_attr_const(right)->offset; + if (get_signed_imm_size(imm) == 1) { + bemit_unop_reg(node, 0x6B, n_ia32_IMul_left); + bemit8(imm); + } else { + bemit_unop_reg(node, 0x69, n_ia32_IMul_left); + bemit32(imm); + } + } else { + bemit8(0x0F); + bemit_unop_reg(node, 0xAF, n_ia32_IMul_right); + } +} + static void bemit_dec(const ir_node *node) { - const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res); + const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res); bemit8(0x48 + reg_gp_map[out->index]); } static void bemit_inc(const ir_node *node) { - const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res); + const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res); bemit8(0x40 + reg_gp_map[out->index]); } +#define UNOPMEM(op, code, ext) \ +static void bemit_##op(const ir_node *node) \ +{ \ + bemit_unop_mem(node, code, ext); \ +} + +UNOPMEM(notmem, 0xF6, 2) +UNOPMEM(negmem, 0xF6, 3) +UNOPMEM(incmem, 0xFE, 0) +UNOPMEM(decmem, 0xFE, 1) + +static void bemit_ldtls(const ir_node *node) +{ + const arch_register_t *out = arch_get_irn_register_out(node, 0); + + bemit8(0x65); // gs: + if (out->index == REG_GP_EAX) { + bemit8(0xA1); // movl 0, %eax + } else { + bemit8(0x8B); // movl 0, %reg + bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05)); + } + bemit32(0); +} + /** * Emit a Lea. */ static void bemit_lea(const ir_node *node) { - const arch_register_t *out = get_out_reg(node, 0); + const arch_register_t *out = arch_get_irn_register_out(node, 0); bemit8(0x8D); bemit_mod_am(reg_gp_map[out->index], node); } +/* helper function for bemit_minus64bit */ +static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst) +{ + bemit8(0x8B); // movl %src, %dst + bemit_modrr(src, dst); +} + +/* helper function for bemit_minus64bit */ +static void bemit_helper_neg(const arch_register_t *reg) +{ + bemit8(0xF7); // negl %reg + bemit_modru(reg, 3); +} + +/* helper function for bemit_minus64bit */ +static void bemit_helper_sbb0(const arch_register_t *reg) +{ + bemit8(0x83); // sbbl $0, %reg + bemit_modru(reg, 3); + bemit8(0); +} + +/* helper function for bemit_minus64bit */ +static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst) +{ + bemit8(0x1B); // sbbl %src, %dst + bemit_modrr(src, dst); +} + +/* helper function for bemit_minus64bit */ +static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst) +{ + if (src->index == REG_GP_EAX) { + bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst + } else if (dst->index == REG_GP_EAX) { + bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax + } else { + bemit8(0x87); // xchgl %src, %dst + bemit_modrr(src, dst); + } +} + +/* helper function for bemit_minus64bit */ +static void bemit_helper_zero(const arch_register_t *reg) +{ + bemit8(0x33); // xorl %reg, %reg + bemit_modrr(reg, reg); +} + +static void bemit_minus64bit(const ir_node *node) +{ + const arch_register_t *in_lo = arch_get_irn_register_in(node, 0); + const arch_register_t *in_hi = arch_get_irn_register_in(node, 1); + const arch_register_t *out_lo = arch_get_irn_register_out(node, 0); + const arch_register_t *out_hi = arch_get_irn_register_out(node, 1); + + if (out_lo == in_lo) { + if (out_hi != in_hi) { + /* a -> a, b -> d */ + goto zero_neg; + } else { + /* a -> a, b -> b */ + goto normal_neg; + } + } else if (out_lo == in_hi) { + if (out_hi == in_lo) { + /* a -> b, b -> a */ + bemit_helper_xchg(in_lo, in_hi); + goto normal_neg; + } else { + /* a -> b, b -> d */ + bemit_helper_mov(in_hi, out_hi); + bemit_helper_mov(in_lo, out_lo); + goto normal_neg; + } + } else { + if (out_hi == in_lo) { + /* a -> c, b -> a */ + bemit_helper_mov(in_lo, out_lo); + goto zero_neg; + } else if (out_hi == in_hi) { + /* a -> c, b -> b */ + bemit_helper_mov(in_lo, out_lo); + goto normal_neg; + } else { + /* a -> c, b -> d */ + bemit_helper_mov(in_lo, out_lo); + goto zero_neg; + } + } + +normal_neg: + bemit_helper_neg( out_hi); + bemit_helper_neg( out_lo); + bemit_helper_sbb0(out_hi); + return; + +zero_neg: + bemit_helper_zero(out_hi); + bemit_helper_neg( out_lo); + bemit_helper_sbb( in_hi, out_hi); +} + /** - * Emit a single optcode. + * Emit a single opcode. */ #define EMIT_SINGLEOP(op, code) \ static void bemit_ ## op(const ir_node *node) { \ @@ -2759,19 +2967,20 @@ static void bemit_ ## op(const ir_node *node) { \ //EMIT_SINGLEOP(aaa, 0x37) //EMIT_SINGLEOP(aas, 0x3F) //EMIT_SINGLEOP(nop, 0x90) -//EMIT_SINGLEOP(cwde, 0x98) -EMIT_SINGLEOP(cltd, 0x99) +EMIT_SINGLEOP(cwtl, 0x98) +EMIT_SINGLEOP(cltd, 0x99) //EMIT_SINGLEOP(fwait, 0x9B) -EMIT_SINGLEOP(sahf, 0x9E) +EMIT_SINGLEOP(sahf, 0x9E) //EMIT_SINGLEOP(popf, 0x9D) -EMIT_SINGLEOP(int3, 0xCC) +EMIT_SINGLEOP(leave, 0xC9) +EMIT_SINGLEOP(int3, 0xCC) //EMIT_SINGLEOP(iret, 0xCF) //EMIT_SINGLEOP(xlat, 0xD7) //EMIT_SINGLEOP(lock, 0xF0) -EMIT_SINGLEOP(rep, 0xF3) +EMIT_SINGLEOP(rep, 0xF3) //EMIT_SINGLEOP(halt, 0xF4) -EMIT_SINGLEOP(cmc, 0xF5) -EMIT_SINGLEOP(stc, 0xF9) +EMIT_SINGLEOP(cmc, 0xF5) +EMIT_SINGLEOP(stc, 0xF9) //EMIT_SINGLEOP(cli, 0xFA) //EMIT_SINGLEOP(sti, 0xFB) //EMIT_SINGLEOP(std, 0xFD) @@ -2781,21 +2990,20 @@ EMIT_SINGLEOP(stc, 0xF9) */ static void bemit_load(const ir_node *node) { - const arch_register_t *out = get_out_reg(node, 0); + const arch_register_t *out = arch_get_irn_register_out(node, 0); - if (out->index == REG_EAX) { - ir_entity *ent = get_ia32_am_sc(node); - int offs = get_ia32_am_offs_int(node); + if (out->index == REG_GP_EAX) { ir_node *base = get_irn_n(node, n_ia32_base); int has_base = !is_ia32_NoReg_GP(base); - ir_node *index = get_irn_n(node, n_ia32_index); - int has_index = !is_ia32_NoReg_GP(index); - - if (ent == NULL && !has_base && !has_index) { + ir_node *idx = get_irn_n(node, n_ia32_index); + int has_index = !is_ia32_NoReg_GP(idx); + if (!has_base && !has_index) { + ir_entity *ent = get_ia32_am_sc(node); + int offs = get_ia32_am_offs_int(node); /* load from constant address to EAX can be encoded as 0xA1 [offset] */ bemit8(0xA1); - bemit_entity(NULL, 0, offs, false); + bemit_entity(ent, 0, offs, false); return; } } @@ -2809,35 +3017,75 @@ static void bemit_load(const ir_node *node) static void bemit_store(const ir_node *node) { const ir_node *value = get_irn_n(node, n_ia32_Store_val); + unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); if (is_ia32_Immediate(value)) { - bemit8(0xC7); - bemit_mod_am(0, node); - bemit_immediate(value, false); + if (size == 8) { + bemit8(0xC6); + bemit_mod_am(0, node); + bemit8(get_ia32_immediate_attr_const(value)->offset); + } else if (size == 16) { + bemit8(0x66); + bemit8(0xC7); + bemit_mod_am(0, node); + bemit16(get_ia32_immediate_attr_const(value)->offset); + } else { + bemit8(0xC7); + bemit_mod_am(0, node); + bemit_immediate(value, false); + } } else { - const arch_register_t *in = get_in_reg(node, n_ia32_Store_val); + const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val); - if (in->index == REG_EAX) { - ir_entity *ent = get_ia32_am_sc(node); - int offs = get_ia32_am_offs_int(node); + if (in->index == REG_GP_EAX) { ir_node *base = get_irn_n(node, n_ia32_base); int has_base = !is_ia32_NoReg_GP(base); - ir_node *index = get_irn_n(node, n_ia32_index); - int has_index = !is_ia32_NoReg_GP(index); - - if (ent == NULL && !has_base && !has_index) { + ir_node *idx = get_irn_n(node, n_ia32_index); + int has_index = !is_ia32_NoReg_GP(idx); + if (!has_base && !has_index) { + ir_entity *ent = get_ia32_am_sc(node); + int offs = get_ia32_am_offs_int(node); /* store to constant address from EAX can be encoded as - 0xA3 [offset]*/ - bemit8(0xA3); - bemit_entity(NULL, 0, offs, false); + * 0xA2/0xA3 [offset]*/ + if (size == 8) { + bemit8(0xA2); + } else { + if (size == 16) + bemit8(0x66); + bemit8(0xA3); + } + bemit_entity(ent, 0, offs, false); return; } } - bemit8(0x89); + + if (size == 8) { + bemit8(0x88); + } else { + if (size == 16) + bemit8(0x66); + bemit8(0x89); + } bemit_mod_am(reg_gp_map[in->index], node); } } +static void bemit_conv_i2i(const ir_node *node) +{ + ir_mode *smaller_mode = get_ia32_ls_mode(node); + unsigned opcode; + + bemit8(0x0F); + /* 8 16 bit source + * movzx B6 B7 + * movsx BE BF + */ + opcode = 0xB6; + if (mode_is_signed(smaller_mode)) opcode |= 0x08; + if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01; + bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val); +} + /** * Emit a Push. */ @@ -2848,7 +3096,7 @@ static void bemit_push(const ir_node *node) if (is_ia32_Immediate(value)) { const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(value); - unsigned size = get_unsigned_imm_size(attr->offset); + unsigned size = get_signed_imm_size(attr->offset); if (attr->symconst) size = 4; switch (size) { @@ -2862,9 +3110,12 @@ static void bemit_push(const ir_node *node) bemit_immediate(value, false); break; } - } else { + } else if (is_ia32_NoReg_GP(value)) { bemit8(0xFF); bemit_mod_am(6, node); + } else { + const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val); + bemit8(0x50 + reg_gp_map[reg->index]); } } @@ -2873,13 +3124,14 @@ static void bemit_push(const ir_node *node) */ static void bemit_pop(const ir_node *node) { - const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res); - if (get_ia32_op_type(node) == ia32_Normal) - bemit8(0x58 + reg_gp_map[reg->index]); - else { - bemit8(0x8F); - bemit_mod_am(0, node); - } + const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res); + bemit8(0x58 + reg_gp_map[reg->index]); +} + +static void bemit_popmem(const ir_node *node) +{ + bemit8(0x8F); + bemit_mod_am(0, node); } static void bemit_call(const ir_node *node) @@ -2890,12 +3142,7 @@ static void bemit_call(const ir_node *node) bemit8(0xE8); bemit_immediate(proc, true); } else { - bemit8(0xFF); - if (get_ia32_op_type(node) == ia32_Normal) { - bemit_modru(get_in_reg(node, n_ia32_unary_op), 2); - } else { - bemit_mod_am(2, node); - } + bemit_unop(node, 0xFF, 2, n_ia32_Call_addr); } } @@ -2915,34 +3162,28 @@ static void bemit_jump(const ir_node *node) static void bemit_jcc(int pnc, const ir_node *dest_block) { - unsigned char cc; - - if (pnc == ia32_pn_Cmp_parity) { - cc = 0x0A; - } else { - if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) { - cc = pnc_map_unsigned[pnc & 0x07]; - } else { - cc = pnc_map_signed[pnc & 0x07]; - } - } - + unsigned char cc = pnc2cc(pnc); bemit8(0x0F); bemit8(0x80 + cc); bemit_jmp_destination(dest_block); } +static void bemit_jp(bool odd, const ir_node *dest_block) +{ + bemit8(0x0F); + bemit8(0x8A + odd); + bemit_jmp_destination(dest_block); +} + static void bemit_ia32_jcc(const ir_node *node) { - int pnc = get_ia32_condcode(node); - int need_parity_label = 0; - const ir_node *proj_true; - const ir_node *proj_false; - const ir_node *dest_true; - const ir_node *dest_false; - const ir_node *block; + ia32_condition_code_t cc = get_ia32_condcode(node); + const ir_node *proj_true; + const ir_node *proj_false; + const ir_node *dest_true; + const ir_node *dest_false; - pnc = determine_final_pnc(node, 0, pnc); + cc = determine_final_cc(node, 0, cc); /* get both Projs */ proj_true = get_proj(node, pn_ia32_Jcc_true); @@ -2951,64 +3192,35 @@ static void bemit_ia32_jcc(const ir_node *node) proj_false = get_proj(node, pn_ia32_Jcc_false); assert(proj_false && "Jcc without false Proj"); - block = get_nodes_block(node); - if (can_be_fallthrough(proj_true)) { /* exchange both proj's so the second one can be omitted */ const ir_node *t = proj_true; proj_true = proj_false; proj_false = t; - pnc = ia32_get_negated_pnc(pnc); + cc = ia32_negate_condition_code(cc); } dest_true = get_cfop_target_block(proj_true); dest_false = get_cfop_target_block(proj_false); - if (pnc & ia32_pn_Cmp_float) { - panic("Float jump NIY"); + if (cc & ia32_cc_float_parity_cases) { /* Some floating point comparisons require a test of the parity flag, * which indicates that the result is unordered */ - switch (pnc & 15) { - case pn_Cmp_Uo: { - ia32_emitf(proj_true, "\tjp %L\n"); - break; + if (cc & ia32_cc_negated) { + bemit_jp(false, dest_true); + } else { + /* we need a local label if the false proj is a fallthrough + * as the falseblock might have no label emitted then */ + if (can_be_fallthrough(proj_false)) { + bemit8(0x7A); + bemit8(0x06); // jp + 6 + } else { + bemit_jp(false, dest_false); } - - case pn_Cmp_Leg: - ia32_emitf(proj_true, "\tjnp %L\n"); - break; - - case pn_Cmp_Eq: - case pn_Cmp_Lt: - case pn_Cmp_Le: - /* we need a local label if the false proj is a fallthrough - * as the falseblock might have no label emitted then */ - if (can_be_fallthrough(proj_false)) { - need_parity_label = 1; - ia32_emitf(proj_false, "\tjp 1f\n"); - } else { - ia32_emitf(proj_false, "\tjp %L\n"); - } - goto emit_jcc; - - case pn_Cmp_Ug: - case pn_Cmp_Uge: - case pn_Cmp_Ne: - ia32_emitf(proj_true, "\tjp %L\n"); - goto emit_jcc; - - default: - goto emit_jcc; } - } else { -emit_jcc: - bemit_jcc(pnc, dest_true); - } - - if (need_parity_label) { - panic("parity label NIY"); } + bemit_jcc(cc, dest_true); /* the second Proj might be a fallthrough */ if (can_be_fallthrough(proj_false)) { @@ -3018,6 +3230,17 @@ emit_jcc: } } +static void bemit_switchjmp(const ir_node *node) +{ + ir_entity *jump_table = get_ia32_am_sc(node); + long default_pn = get_ia32_default_pn(node); + + bemit8(0xFF); // jmp *tbl.label(,%in,4) + bemit_mod_am(0x05, node); + + emit_jump_table(node, default_pn, jump_table, get_cfop_target_block); +} + /** * Emits a return. */ @@ -3033,6 +3256,17 @@ static void bemit_return(const ir_node *node) } } +static void bemit_subsp(const ir_node *node) +{ + const arch_register_t *out; + /* sub %in, %esp */ + bemit_sub(node); + /* mov %esp, %out */ + bemit8(0x8B); + out = arch_get_irn_register_out(node, 1); + bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04)); +} + static void bemit_incsp(const ir_node *node) { int offs; @@ -3054,7 +3288,7 @@ static void bemit_incsp(const ir_node *node) size = get_signed_imm_size(offs); bemit8(size == 1 ? 0x83 : 0x81); - reg = get_out_reg(node, 0); + reg = arch_get_irn_register_out(node, 0); bemit_modru(reg, ext); if (size == 1) { @@ -3064,6 +3298,372 @@ static void bemit_incsp(const ir_node *node) } } +static void bemit_copybi(const ir_node *node) +{ + unsigned size = get_ia32_copyb_size(node); + if (size & 1) + bemit8(0xA4); // movsb + if (size & 2) { + bemit8(0x66); + bemit8(0xA5); // movsw + } + size >>= 2; + while (size--) { + bemit8(0xA5); // movsl + } +} + +static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to) +{ + if (get_ia32_op_type(node) == ia32_Normal) { + const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node); + const arch_register_t *in1 = x87_attr->x87[0]; + const arch_register_t *in = x87_attr->x87[1]; + const arch_register_t *out = x87_attr->x87[2]; + + if (out == NULL) { + out = in1; + } else if (out == in) { + in = in1; + } + + if (out->index == 0) { + bemit8(0xD8); + bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index)); + } else { + bemit8(0xDC); + bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index)); + } + } else { + if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) { + bemit8(0xD8); + } else { + bemit8(0xDC); + } + bemit_mod_am(code, node); + } +} + +static void bemit_fbinopp(const ir_node *node, unsigned const code) +{ + const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node); + const arch_register_t *out = x87_attr->x87[2]; + bemit8(0xDE); + bemit8(code + out->index); +} + +static void bemit_fabs(const ir_node *node) +{ + (void)node; + + bemit8(0xD9); + bemit8(0xE1); +} + +static void bemit_fadd(const ir_node *node) +{ + bemit_fbinop(node, 0, 0); +} + +static void bemit_faddp(const ir_node *node) +{ + bemit_fbinopp(node, 0xC0); +} + +static void bemit_fchs(const ir_node *node) +{ + (void)node; + + bemit8(0xD9); + bemit8(0xE0); +} + +static void bemit_fdiv(const ir_node *node) +{ + bemit_fbinop(node, 6, 7); +} + +static void bemit_fdivp(const ir_node *node) +{ + bemit_fbinopp(node, 0xF8); +} + +static void bemit_fdivr(const ir_node *node) +{ + bemit_fbinop(node, 7, 6); +} + +static void bemit_fdivrp(const ir_node *node) +{ + bemit_fbinopp(node, 0xF0); +} + +static void bemit_fild(const ir_node *node) +{ + switch (get_mode_size_bits(get_ia32_ls_mode(node))) { + case 16: + bemit8(0xDF); // filds + bemit_mod_am(0, node); + return; + + case 32: + bemit8(0xDB); // fildl + bemit_mod_am(0, node); + return; + + case 64: + bemit8(0xDF); // fildll + bemit_mod_am(5, node); + return; + + default: + panic("invalid mode size"); + } +} + +static void bemit_fist(const ir_node *node) +{ + switch (get_mode_size_bits(get_ia32_ls_mode(node))) { + case 16: + bemit8(0xDF); // fists + break; + + case 32: + bemit8(0xDB); // fistl + break; + + default: + panic("invalid mode size"); + } + bemit_mod_am(2, node); +} + +static void bemit_fistp(const ir_node *node) +{ + switch (get_mode_size_bits(get_ia32_ls_mode(node))) { + case 16: + bemit8(0xDF); // fistps + bemit_mod_am(3, node); + return; + + case 32: + bemit8(0xDB); // fistpl + bemit_mod_am(3, node); + return; + + case 64: + bemit8(0xDF); // fistpll + bemit_mod_am(7, node); + return; + + default: + panic("invalid mode size"); + } +} + +static void bemit_fld(const ir_node *node) +{ + switch (get_mode_size_bits(get_ia32_ls_mode(node))) { + case 32: + bemit8(0xD9); // flds + bemit_mod_am(0, node); + return; + + case 64: + bemit8(0xDD); // fldl + bemit_mod_am(0, node); + return; + + case 80: + case 96: + bemit8(0xDB); // fldt + bemit_mod_am(5, node); + return; + + default: + panic("invalid mode size"); + } +} + +static void bemit_fld1(const ir_node *node) +{ + (void)node; + bemit8(0xD9); + bemit8(0xE8); // fld1 +} + +static void bemit_fldcw(const ir_node *node) +{ + bemit8(0xD9); // fldcw + bemit_mod_am(5, node); +} + +static void bemit_fldz(const ir_node *node) +{ + (void)node; + bemit8(0xD9); + bemit8(0xEE); // fldz +} + +static void bemit_fmul(const ir_node *node) +{ + bemit_fbinop(node, 1, 1); +} + +static void bemit_fmulp(const ir_node *node) +{ + bemit_fbinopp(node, 0xC8); +} + +static void bemit_fpop(const ir_node *node) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); + bemit8(0xDD); + bemit8(0xD8 + attr->x87[0]->index); +} + +static void bemit_fpush(const ir_node *node) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); + bemit8(0xD9); + bemit8(0xC0 + attr->x87[0]->index); +} + +static void bemit_fpushcopy(const ir_node *node) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); + bemit8(0xD9); + bemit8(0xC0 + attr->x87[0]->index); +} + +static void bemit_fst(const ir_node *node) +{ + switch (get_mode_size_bits(get_ia32_ls_mode(node))) { + case 32: + bemit8(0xD9); // fsts + break; + + case 64: + bemit8(0xDD); // fstl + break; + + default: + panic("invalid mode size"); + } + bemit_mod_am(2, node); +} + +static void bemit_fstp(const ir_node *node) +{ + switch (get_mode_size_bits(get_ia32_ls_mode(node))) { + case 32: + bemit8(0xD9); // fstps + bemit_mod_am(3, node); + return; + + case 64: + bemit8(0xDD); // fstpl + bemit_mod_am(3, node); + return; + + case 80: + case 96: + bemit8(0xDB); // fstpt + bemit_mod_am(7, node); + return; + + default: + panic("invalid mode size"); + } +} + +static void bemit_fsub(const ir_node *node) +{ + bemit_fbinop(node, 4, 5); +} + +static void bemit_fsubp(const ir_node *node) +{ + bemit_fbinopp(node, 0xE8); +} + +static void bemit_fsubr(const ir_node *node) +{ + bemit_fbinop(node, 5, 4); +} + +static void bemit_fsubrp(const ir_node *node) +{ + bemit_fbinopp(node, 0xE0); +} + +static void bemit_fnstcw(const ir_node *node) +{ + bemit8(0xD9); // fnstcw + bemit_mod_am(7, node); +} + +static void bemit_fnstsw(void) +{ + bemit8(0xDF); // fnstsw %ax + bemit8(0xE0); +} + +static void bemit_ftstfnstsw(const ir_node *node) +{ + (void)node; + + bemit8(0xD9); // ftst + bemit8(0xE4); + bemit_fnstsw(); +} + +static void bemit_fucomi(const ir_node *node) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); + bemit8(0xDB); // fucomi + bemit8(0xE8 + attr->x87[1]->index); +} + +static void bemit_fucomip(const ir_node *node) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); + bemit8(0xDF); // fucomip + bemit8(0xE8 + attr->x87[1]->index); +} + +static void bemit_fucomfnstsw(const ir_node *node) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); + bemit8(0xDD); // fucom + bemit8(0xE0 + attr->x87[1]->index); + bemit_fnstsw(); +} + +static void bemit_fucompfnstsw(const ir_node *node) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); + bemit8(0xDD); // fucomp + bemit8(0xE8 + attr->x87[1]->index); + bemit_fnstsw(); +} + +static void bemit_fucomppfnstsw(const ir_node *node) +{ + (void)node; + + bemit8(0xDA); // fucompp + bemit8(0xE9); + bemit_fnstsw(); +} + +static void bemit_fxch(const ir_node *node) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); + bemit8(0xD9); + bemit8(0xC8 + attr->x87[0]->index); +} + /** * The type of a emitter function. */ @@ -3083,55 +3683,129 @@ static void ia32_register_binary_emitters(void) clear_irp_opcodes_generic_func(); /* benode emitter */ - register_emitter(op_be_Copy, bemit_copy); - register_emitter(op_be_IncSP, bemit_incsp); - register_emitter(op_be_Return, bemit_return); - register_emitter(op_ia32_Adc, bemit_adc); - register_emitter(op_ia32_Add, bemit_add); - register_emitter(op_ia32_And, bemit_and); - register_emitter(op_ia32_Breakpoint, bemit_int3); - register_emitter(op_ia32_Call, bemit_call); - register_emitter(op_ia32_Cltd, bemit_cltd); - register_emitter(op_ia32_Cmc, bemit_cmc); - register_emitter(op_ia32_Cmp, bemit_cmp); - register_emitter(op_ia32_Const, bemit_mov_const); - register_emitter(op_ia32_Dec, bemit_dec); - register_emitter(op_ia32_Div, bemit_div); - register_emitter(op_ia32_IDiv, bemit_idiv); - register_emitter(op_ia32_IJmp, bemit_ijmp); - register_emitter(op_ia32_IMul1OP, bemit_imul1op); - register_emitter(op_ia32_Inc, bemit_inc); - register_emitter(op_ia32_Jcc, bemit_ia32_jcc); - register_emitter(op_ia32_Jmp, bemit_jump); - register_emitter(op_ia32_Lea, bemit_lea); - register_emitter(op_ia32_Load, bemit_load); - register_emitter(op_ia32_Mul, bemit_mul); - register_emitter(op_ia32_Neg, bemit_neg); - register_emitter(op_ia32_Not, bemit_not); - register_emitter(op_ia32_Or, bemit_or); - register_emitter(op_ia32_Pop, bemit_pop); - register_emitter(op_ia32_Push, bemit_push); - register_emitter(op_ia32_RepPrefix, bemit_rep); - register_emitter(op_ia32_Rol, bemit_rol); - register_emitter(op_ia32_Ror, bemit_ror); - register_emitter(op_ia32_Sahf, bemit_sahf); - register_emitter(op_ia32_Sar, bemit_sar); - register_emitter(op_ia32_Sbb, bemit_sbb); - register_emitter(op_ia32_Shl, bemit_shl); - register_emitter(op_ia32_Shr, bemit_shr); - register_emitter(op_ia32_Stc, bemit_stc); - register_emitter(op_ia32_Store, bemit_store); - register_emitter(op_ia32_Sub, bemit_sub); - register_emitter(op_ia32_Xor, bemit_xor); - register_emitter(op_ia32_Xor0, bemit_xor0); + register_emitter(op_be_Copy, bemit_copy); + register_emitter(op_be_CopyKeep, bemit_copy); + register_emitter(op_be_IncSP, bemit_incsp); + register_emitter(op_be_Perm, bemit_perm); + register_emitter(op_be_Return, bemit_return); + register_emitter(op_ia32_Adc, bemit_adc); + register_emitter(op_ia32_Add, bemit_add); + register_emitter(op_ia32_AddMem, bemit_addmem); + register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit); + register_emitter(op_ia32_And, bemit_and); + register_emitter(op_ia32_AndMem, bemit_andmem); + register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit); + register_emitter(op_ia32_Breakpoint, bemit_int3); + register_emitter(op_ia32_CMovcc, bemit_cmovcc); + register_emitter(op_ia32_Call, bemit_call); + register_emitter(op_ia32_Cltd, bemit_cltd); + register_emitter(op_ia32_Cmc, bemit_cmc); + register_emitter(op_ia32_Cmp, bemit_cmp); + register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit); + register_emitter(op_ia32_Const, bemit_mov_const); + register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i); + register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i); + register_emitter(op_ia32_CopyB_i, bemit_copybi); + register_emitter(op_ia32_Cwtl, bemit_cwtl); + register_emitter(op_ia32_Dec, bemit_dec); + register_emitter(op_ia32_DecMem, bemit_decmem); + register_emitter(op_ia32_Div, bemit_div); + register_emitter(op_ia32_FldCW, bemit_fldcw); + register_emitter(op_ia32_FnstCW, bemit_fnstcw); + register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw); + register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw); + register_emitter(op_ia32_Fucomi, bemit_fucomi); + register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw); + register_emitter(op_ia32_Fucompi, bemit_fucomip); + register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw); + register_emitter(op_ia32_IDiv, bemit_idiv); + register_emitter(op_ia32_IJmp, bemit_ijmp); + register_emitter(op_ia32_IMul, bemit_imul); + register_emitter(op_ia32_IMul1OP, bemit_imul1op); + register_emitter(op_ia32_Inc, bemit_inc); + register_emitter(op_ia32_IncMem, bemit_incmem); + register_emitter(op_ia32_Jcc, bemit_ia32_jcc); + register_emitter(op_ia32_Jmp, bemit_jump); + register_emitter(op_ia32_LdTls, bemit_ldtls); + register_emitter(op_ia32_Lea, bemit_lea); + register_emitter(op_ia32_Leave, bemit_leave); + register_emitter(op_ia32_Load, bemit_load); + register_emitter(op_ia32_Minus64Bit, bemit_minus64bit); + register_emitter(op_ia32_Mul, bemit_mul); + register_emitter(op_ia32_Neg, bemit_neg); + register_emitter(op_ia32_NegMem, bemit_negmem); + register_emitter(op_ia32_Not, bemit_not); + register_emitter(op_ia32_NotMem, bemit_notmem); + register_emitter(op_ia32_Or, bemit_or); + register_emitter(op_ia32_OrMem, bemit_ormem); + register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit); + register_emitter(op_ia32_Pop, bemit_pop); + register_emitter(op_ia32_PopEbp, bemit_pop); + register_emitter(op_ia32_PopMem, bemit_popmem); + register_emitter(op_ia32_Push, bemit_push); + register_emitter(op_ia32_RepPrefix, bemit_rep); + register_emitter(op_ia32_Rol, bemit_rol); + register_emitter(op_ia32_RolMem, bemit_rolmem); + register_emitter(op_ia32_Ror, bemit_ror); + register_emitter(op_ia32_RorMem, bemit_rormem); + register_emitter(op_ia32_Sahf, bemit_sahf); + register_emitter(op_ia32_Sar, bemit_sar); + register_emitter(op_ia32_SarMem, bemit_sarmem); + register_emitter(op_ia32_Sbb, bemit_sbb); + register_emitter(op_ia32_Setcc, bemit_setcc); + register_emitter(op_ia32_Shl, bemit_shl); + register_emitter(op_ia32_ShlD, bemit_shld); + register_emitter(op_ia32_ShlMem, bemit_shlmem); + register_emitter(op_ia32_Shr, bemit_shr); + register_emitter(op_ia32_ShrD, bemit_shrd); + register_emitter(op_ia32_ShrMem, bemit_shrmem); + register_emitter(op_ia32_Stc, bemit_stc); + register_emitter(op_ia32_Store, bemit_store); + register_emitter(op_ia32_Store8Bit, bemit_store); + register_emitter(op_ia32_Sub, bemit_sub); + register_emitter(op_ia32_SubMem, bemit_submem); + register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit); + register_emitter(op_ia32_SubSP, bemit_subsp); + register_emitter(op_ia32_SwitchJmp, bemit_switchjmp); + register_emitter(op_ia32_Test, bemit_test); + register_emitter(op_ia32_Test8Bit, bemit_test8bit); + register_emitter(op_ia32_Xor, bemit_xor); + register_emitter(op_ia32_Xor0, bemit_xor0); + register_emitter(op_ia32_XorMem, bemit_xormem); + register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit); + register_emitter(op_ia32_fabs, bemit_fabs); + register_emitter(op_ia32_fadd, bemit_fadd); + register_emitter(op_ia32_faddp, bemit_faddp); + register_emitter(op_ia32_fchs, bemit_fchs); + register_emitter(op_ia32_fdiv, bemit_fdiv); + register_emitter(op_ia32_fdivp, bemit_fdivp); + register_emitter(op_ia32_fdivr, bemit_fdivr); + register_emitter(op_ia32_fdivrp, bemit_fdivrp); + register_emitter(op_ia32_fild, bemit_fild); + register_emitter(op_ia32_fist, bemit_fist); + register_emitter(op_ia32_fistp, bemit_fistp); + register_emitter(op_ia32_fld, bemit_fld); + register_emitter(op_ia32_fld1, bemit_fld1); + register_emitter(op_ia32_fldz, bemit_fldz); + register_emitter(op_ia32_fmul, bemit_fmul); + register_emitter(op_ia32_fmulp, bemit_fmulp); + register_emitter(op_ia32_fpop, bemit_fpop); + register_emitter(op_ia32_fpush, bemit_fpush); + register_emitter(op_ia32_fpushCopy, bemit_fpushcopy); + register_emitter(op_ia32_fst, bemit_fst); + register_emitter(op_ia32_fstp, bemit_fstp); + register_emitter(op_ia32_fsub, bemit_fsub); + register_emitter(op_ia32_fsubp, bemit_fsubp); + register_emitter(op_ia32_fsubr, bemit_fsubr); + register_emitter(op_ia32_fsubrp, bemit_fsubrp); + register_emitter(op_ia32_fxch, bemit_fxch); /* ignore the following nodes */ - register_emitter(op_ia32_ProduceVal, emit_Nothing); - register_emitter(op_be_Barrier, emit_Nothing); - register_emitter(op_be_Keep, emit_Nothing); - register_emitter(op_be_Start, emit_Nothing); - register_emitter(op_Phi, emit_Nothing); - register_emitter(op_Start, emit_Nothing); + register_emitter(op_ia32_ProduceVal, emit_Nothing); + register_emitter(op_be_Keep, emit_Nothing); + register_emitter(op_be_Start, emit_Nothing); + register_emitter(op_Phi, emit_Nothing); + register_emitter(op_Start, emit_Nothing); } static void gen_binary_block(ir_node *block) @@ -3146,13 +3820,15 @@ static void gen_binary_block(ir_node *block) } } -void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg) +void ia32_gen_binary_routine(ir_graph *irg) { - ir_entity *entity = get_irg_entity(irg); - int i, n; + ir_entity *entity = get_irg_entity(irg); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_irg_data_t *irg_data = ia32_get_irg_data(irg); + ir_node **blk_sched = irg_data->blk_sched; + size_t i, n; - cg = ia32_cg; - isa = cg->isa; + isa = (ia32_isa_t*) arch_env; ia32_register_binary_emitters(); @@ -3163,16 +3839,16 @@ void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg) irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL); /* initialize next block links */ - n = ARR_LEN(cg->blk_sched); + n = ARR_LEN(blk_sched); for (i = 0; i < n; ++i) { - ir_node *block = cg->blk_sched[i]; - ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL; + ir_node *block = blk_sched[i]; + ir_node *prev = i > 0 ? blk_sched[i-1] : NULL; set_irn_link(block, prev); } for (i = 0; i < n; ++i) { - ir_node *block = cg->blk_sched[i]; + ir_node *block = blk_sched[i]; gen_binary_block(block); } @@ -3185,8 +3861,6 @@ void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg) } - - void ia32_init_emitter(void) { lc_opt_entry_t *be_grp;