X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_emitter.c;h=cc0e8df38f243d165e340498b4f3de040d5904fc;hb=b77d3a47774fd137aa76b086339fe2394dc84477;hp=42dfca1565c3bb3dc96efdc7af6daa42948231f3;hpb=c49103ab934876ff793e8604b1b6dc23c136658c;p=libfirm diff --git a/ir/be/ia32/ia32_emitter.c b/ir/be/ia32/ia32_emitter.c index 42dfca156..603c77be0 100644 --- a/ir/be/ia32/ia32_emitter.c +++ b/ir/be/ia32/ia32_emitter.c @@ -1,9 +1,28 @@ -/** - * This file implements the node emitter. - * @author Christian Wuerdig - * $Id$ +/* + * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * + * This file is part of libFirm. + * + * This file may be distributed and/or modified under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation and appearing in the file LICENSE.GPL included in the + * packaging of this file. + * + * Licensees holding valid libFirm Professional Edition licenses may use + * this file in accordance with the libFirm Commercial License. + * Agreement provided with the Software. + * + * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. */ +/** + * @file + * @brief This file implements the ia32 node emitter. + * @author Christian Wuerdig, Matthias Braun + * @version $Id$ + */ #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -20,9 +39,17 @@ #include "irargs_t.h" #include "irprog_t.h" #include "iredges_t.h" +#include "execfreq.h" +#include "error.h" +#include "raw_bitset.h" #include "../besched_t.h" #include "../benode_t.h" +#include "../beabi.h" +#include "../be_dbgout.h" +#include "../beemitter.h" +#include "../begnuas.h" +#include "../beirg_t.h" #include "ia32_emitter.h" #include "gen_ia32_emitter.h" @@ -32,105 +59,23 @@ #include "ia32_map_regs.h" #include "bearch_ia32_t.h" -#define BLOCK_PREFIX(x) ".L" x - -#define SNPRINTF_BUF_LEN 128 - -/* global arch_env for lc_printf functions */ -static const arch_env_t *arch_env = NULL; - -/** by default, we generate assembler code for the Linux gas */ -asm_flavour_t asm_flavour = ASM_LINUX_GAS; - -/** - * Switch to a new section - */ -void ia32_switch_section(FILE *F, section_t sec) { - static section_t curr_sec = NO_SECTION; - static const char *text[ASM_MAX][SECTION_MAX] = { - { - ".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text" - }, - { - ".section\t.text", ".section\t.data", ".section .rdata,\"dr\"", ".section\t.text" - } - }; - - if (curr_sec == sec) - return; - - curr_sec = sec; - switch (sec) { - - case NO_SECTION: - break; - - case SECTION_TEXT: - case SECTION_DATA: - case SECTION_RODATA: - case SECTION_COMMON: - fprintf(F, "\t%s\n", text[asm_flavour][sec]); - } -} - -static void ia32_dump_function_object(FILE *F, const char *name) -{ - switch (asm_flavour) { - case ASM_LINUX_GAS: - fprintf(F, "\t.type\t%s, @function\n", name); - break; - case ASM_MINGW_GAS: - fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name); - break; - } -} - -static void ia32_dump_function_size(FILE *F, const char *name) -{ - switch (asm_flavour) { - case ASM_LINUX_GAS: - fprintf(F, "\t.size\t%s, .-%s\n", name, name); - break; - } -} - -/************************************************************* - * _ _ __ _ _ - * (_) | | / _| | | | | - * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __ - * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__| - * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ | - * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_| - * | | | | - * |_| |_| - *************************************************************/ - -static INLINE int be_is_unknown_reg(const arch_register_t *reg) { - return \ - REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \ - REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \ - REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]); -} +DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) -/** - * returns true if a node has x87 registers - */ -static INLINE int has_x87_register(const ir_node *n) { - return is_irn_machine_user(n, 0); -} +#define BLOCK_PREFIX ".L" -/* We always pass the ir_node which is a pointer. */ -static int ia32_get_arg_type(const lc_arg_occ_t *occ) { - return lc_arg_type_ptr; -} +#define SNPRINTF_BUF_LEN 128 +static const arch_env_t *arch_env; +static const ia32_isa_t *isa; +static ia32_code_gen_t *cg; /** * Returns the register at in position pos. */ -static const arch_register_t *get_in_reg(const ir_node *irn, int pos) { - ir_node *op; - const arch_register_t *reg = NULL; +static const arch_register_t *get_in_reg(const ir_node *irn, int pos) +{ + ir_node *op; + const arch_register_t *reg = NULL; assert(get_irn_arity(irn) > pos && "Invalid IN position"); @@ -142,13 +87,25 @@ static const arch_register_t *get_in_reg(const ir_node *irn, int pos) { assert(reg && "no in register found"); - /* in case of unknown: just return a register */ - if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN])) - reg = &ia32_gp_regs[REG_EAX]; - else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN])) - reg = &ia32_xmm_regs[REG_XMM0]; - else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN])) - reg = &ia32_vfp_regs[REG_VF0]; + if(reg == &ia32_gp_regs[REG_GP_NOREG]) + panic("trying to emit noreg for %+F input %d", irn, pos); + + /* in case of unknown register: just return a valid register */ + if (reg == &ia32_gp_regs[REG_GP_UKNWN]) { + const arch_register_req_t *req; + + /* ask for the requirements */ + req = arch_get_register_req(arch_env, irn, pos); + + if (arch_register_req_is(req, limited)) { + /* in case of limited requirements: get the first allowed register */ + unsigned idx = rbitset_next(req->limited, 0, 1); + reg = arch_register_for_index(req->cls, idx); + } else { + /* otherwise get first register in class */ + reg = arch_register_for_index(req->cls, 0); + } + } return reg; } @@ -156,9 +113,10 @@ static const arch_register_t *get_in_reg(const ir_node *irn, int pos) { /** * Returns the register at out position pos. */ -static const arch_register_t *get_out_reg(const ir_node *irn, int pos) { - ir_node *proj; - const arch_register_t *reg = NULL; +static const arch_register_t *get_out_reg(const ir_node *irn, int pos) +{ + ir_node *proj; + const arch_register_t *reg = NULL; /* 1st case: irn is not of mode_T, so it has only */ /* one OUT register -> good */ @@ -166,12 +124,11 @@ static const arch_register_t *get_out_reg(const ir_node *irn, int pos) { /* Proj with the corresponding projnum for the register */ if (get_irn_mode(irn) != mode_T) { + assert(pos == 0); reg = arch_get_irn_register(arch_env, irn); - } - else if (is_ia32_irn(irn)) { + } else if (is_ia32_irn(irn)) { reg = get_ia32_out_reg(irn, pos); - } - else { + } else { const ir_edge_t *edge; foreach_out_edge(irn, edge) { @@ -188,504 +145,444 @@ static const arch_register_t *get_out_reg(const ir_node *irn, int pos) { return reg; } -enum io_direction { - IN_REG, - OUT_REG -}; - /** - * Returns the name of the in register at position pos. + * Add a number to a prefix. This number will not be used a second time. */ -static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) { - const arch_register_t *reg; +static char *get_unique_label(char *buf, size_t buflen, const char *prefix) +{ + static unsigned long id = 0; + snprintf(buf, buflen, "%s%lu", prefix, ++id); + return buf; +} - if (in_out == IN_REG) { - reg = get_in_reg(irn, pos); +/************************************************************* + * _ _ __ _ _ + * (_) | | / _| | | | | + * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __ + * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__| + * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ | + * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_| + * | | | | + * |_| |_| + *************************************************************/ - if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) { - /* FIXME: works for binop only */ - assert(2 <= pos && pos <= 3); - reg = get_ia32_attr(irn)->x87[pos - 2]; - } - } - else { - /* destination address mode nodes don't have outputs */ - if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) { - return "MEM"; - } +static void emit_8bit_register(const arch_register_t *reg) +{ + const char *reg_name = arch_register_get_name(reg); - reg = get_out_reg(irn, pos); - if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) - reg = get_ia32_attr(irn)->x87[pos + 2]; - } - return arch_register_get_name(reg); + be_emit_char('%'); + be_emit_char(reg_name[1]); + be_emit_char('l'); } -/** - * Get the register name for a node. - */ -static int ia32_get_reg_name(lc_appendable_t *app, - const lc_arg_occ_t *occ, const lc_arg_value_t *arg) +static void emit_16bit_register(const arch_register_t *reg) { - const char *buf; - ir_node *irn = arg->v_ptr; - int nr = occ->width - 1; - - if (! irn) - return lc_appendable_snadd(app, "(null)", 6); - - buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG); + const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg); - /* append the stupid % to register names */ - lc_appendable_chadd(app, '%'); - return lc_appendable_snadd(app, buf, strlen(buf)); + be_emit_char('%'); + be_emit_string(reg_name); } -/** - * Get the x87 register name for a node. - */ -static int ia32_get_x87_name(lc_appendable_t *app, - const lc_arg_occ_t *occ, const lc_arg_value_t *arg) +static void emit_register(const arch_register_t *reg, const ir_mode *mode) { - const char *buf; - ir_node *irn = arg->v_ptr; - int nr = occ->width - 1; - ia32_attr_t *attr; + const char *reg_name; + + if(mode != NULL) { + int size = get_mode_size_bits(mode); + if(size == 8) { + emit_8bit_register(reg); + return; + } else if(size == 16) { + emit_16bit_register(reg); + return; + } else { + assert(mode_is_float(mode) || size == 32); + } + } - if (! irn) - return lc_appendable_snadd(app, "(null)", 6); + reg_name = arch_register_get_name(reg); - attr = get_ia32_attr(irn); - buf = attr->x87[nr]->name; - lc_appendable_chadd(app, '%'); - return lc_appendable_snadd(app, buf, strlen(buf)); + be_emit_char('%'); + be_emit_string(reg_name); } -/** - * Returns the tarval, offset or scale of an ia32 as a string. - */ -static int ia32_const_to_str(lc_appendable_t *app, - const lc_arg_occ_t *occ, const lc_arg_value_t *arg) +void ia32_emit_source_register(const ir_node *node, int pos) { - const char *buf; - ir_node *irn = arg->v_ptr; + const arch_register_t *reg = get_in_reg(node, pos); - if (! irn) - return lc_arg_append(app, occ, "(null)", 6); + emit_register(reg, NULL); +} - if (occ->conversion == 'C') { - buf = get_ia32_cnst(irn); - } - else { /* 'O' */ - buf = get_ia32_am_offs(irn); +static void emit_ia32_Immediate(const ir_node *node); + +void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos) +{ + const arch_register_t *reg; + ir_node *in = get_irn_n(node, pos); + if(is_ia32_Immediate(in)) { + emit_ia32_Immediate(in); + return; } - return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0; + reg = get_in_reg(node, pos); + emit_8bit_register(reg); } -/** - * Determines the SSE suffix depending on the mode. - */ -static int ia32_get_mode_suffix(lc_appendable_t *app, - const lc_arg_occ_t *occ, const lc_arg_value_t *arg) +void ia32_emit_dest_register(const ir_node *node, int pos) { - ir_node *irn = arg->v_ptr; - ir_mode *mode = get_irn_mode(irn); - - if (mode == mode_T) { - mode = (is_ia32_Ld(irn) || is_ia32_St(irn)) ? get_ia32_ls_mode(irn) : get_ia32_res_mode(irn); - } - - if (! irn) - return lc_arg_append(app, occ, "(null)", 6); + const arch_register_t *reg = get_out_reg(node, pos); - if (mode_is_float(mode)) { - return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd'); - } - else { - return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z'); - } + emit_register(reg, NULL); } -/** - * Return the ia32 printf arg environment. - * We use the firm environment with some additional handlers. - */ -const lc_arg_env_t *ia32_get_arg_env(void) { - static lc_arg_env_t *env = NULL; - - static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name }; - static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str }; - static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix }; - static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name }; +void ia32_emit_8bit_dest_register(const ir_node *node, int pos) +{ + const arch_register_t *reg = get_out_reg(node, pos); - if(env == NULL) { - /* extend the firm printer */ - env = firm_get_arg_env(); + emit_register(reg, mode_Bu); +} - lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler); - lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler); - lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler); - lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler); - lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler); - lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler); - } +void ia32_emit_x87_register(const ir_node *node, int pos) +{ + const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node); - return env; + assert(pos < 3); + be_emit_char('%'); + be_emit_string(attr->x87[pos]->name); } -static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) { - switch(get_mode_size_bits(mode)) { - case 8: - return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg); - case 16: - return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg); - default: - return (char *)arch_register_get_name(reg); +static void ia32_emit_mode_suffix_mode(const ir_mode *mode) +{ + if(mode_is_float(mode)) { + switch(get_mode_size_bits(mode)) { + case 32: be_emit_char('s'); return; + case 64: be_emit_char('l'); return; + case 80: be_emit_char('t'); return; + } + } else { + assert(mode_is_int(mode) || mode_is_reference(mode)); + switch(get_mode_size_bits(mode)) { + case 64: be_emit_cstring("ll"); return; + /* gas docu says q is the suffix but gcc, objdump and icc use + ll apparently */ + case 32: be_emit_char('l'); return; + case 16: be_emit_char('w'); return; + case 8: be_emit_char('b'); return; + } } + panic("Can't output mode_suffix for %+F\n", mode); } -/** - * Emits registers and/or address mode of a binary operation. - */ -const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) { - static char *buf = NULL; +void ia32_emit_mode_suffix(const ir_node *node) +{ + ir_mode *mode = get_ia32_ls_mode(node); + if(mode == NULL) + mode = mode_Iu; - /* verify that this function is never called on non-AM supporting operations */ - //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support"); + ia32_emit_mode_suffix_mode(mode); +} -#define PRODUCES_RESULT(n) \ - (!(is_ia32_St(n) || \ - is_ia32_Store8Bit(n) || \ - is_ia32_CondJmp(n) || \ - is_ia32_xCondJmp(n) || \ - is_ia32_CmpSet(n) || \ - is_ia32_xCmpSet(n) || \ - is_ia32_SwitchJmp(n))) +void ia32_emit_x87_mode_suffix(const ir_node *node) +{ + ir_mode *mode = get_ia32_ls_mode(node); + assert(mode != NULL); + /* we only need to emit the mode on address mode */ + if(get_ia32_op_type(node) != ia32_Normal) + ia32_emit_mode_suffix_mode(mode); +} - if (! buf) { - buf = xcalloc(1, SNPRINTF_BUF_LEN); - } - else { - memset(buf, 0, SNPRINTF_BUF_LEN); +static +char get_xmm_mode_suffix(ir_mode *mode) +{ + assert(mode_is_float(mode)); + switch(get_mode_size_bits(mode)) { + case 32: + return 's'; + case 64: + return 'd'; + default: + assert(0); } + return '%'; +} - switch(get_ia32_op_type(n)) { - case ia32_Normal: - if (is_ia32_ImmConst(n)) { - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n)); - } - else if (is_ia32_ImmSymConst(n)) { - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n)); - } - else { - const arch_register_t *in1 = get_in_reg(n, 2); - const arch_register_t *in2 = get_in_reg(n, 3); - const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL; - const arch_register_t *in; - const char *in_name; - - in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2; - out = out ? out : in1; - in_name = arch_register_get_name(in); - - if (is_ia32_emit_cl(n)) { - assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx"); - in_name = "cl"; - } +void ia32_emit_xmm_mode_suffix(const ir_node *node) +{ + ir_mode *mode = get_ia32_ls_mode(node); + assert(mode != NULL); + be_emit_char('s'); + be_emit_char(get_xmm_mode_suffix(mode)); +} - snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name); - } - break; - case ia32_AddrModeS: - if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) { - assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result"); - snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env)); - } - else { - if (PRODUCES_RESULT(n)) { - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env)); - } - else { - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env)); - } - } - break; - case ia32_AddrModeD: - if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) { - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s", - ia32_emit_am(n, env), - is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */ - get_ia32_cnst(n)); /* tell the assembler to store it's address. */ - } - else { - const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2); - ir_mode *mode = get_ia32_res_mode(n); - const char *in_name; +void ia32_emit_xmm_mode_suffix_s(const ir_node *node) +{ + ir_mode *mode = get_ia32_ls_mode(node); + assert(mode != NULL); + be_emit_char(get_xmm_mode_suffix(mode)); +} - mode = mode ? mode : get_ia32_ls_mode(n); - in_name = ia32_get_reg_name_for_mode(env, mode, in1); +void ia32_emit_extend_suffix(const ir_mode *mode) +{ + if(get_mode_size_bits(mode) == 32) + return; + if(mode_is_signed(mode)) { + be_emit_char('s'); + } else { + be_emit_char('z'); + } +} - if (is_ia32_emit_cl(n)) { - assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx"); - in_name = "cl"; - } +static +void ia32_emit_function_object(const char *name) +{ + switch (be_gas_flavour) { + case GAS_FLAVOUR_NORMAL: + be_emit_cstring("\t.type\t"); + be_emit_string(name); + be_emit_cstring(", @function\n"); + be_emit_write_line(); + break; + case GAS_FLAVOUR_MINGW: + be_emit_cstring("\t.def\t"); + be_emit_string(name); + be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n"); + be_emit_write_line(); + break; + default: + break; + } +} - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name); - } - break; - default: - assert(0 && "unsupported op type"); +static +void ia32_emit_function_size(const char *name) +{ + switch (be_gas_flavour) { + case GAS_FLAVOUR_NORMAL: + be_emit_cstring("\t.size\t"); + be_emit_string(name); + be_emit_cstring(", .-"); + be_emit_string(name); + be_emit_char('\n'); + be_emit_write_line(); + break; + default: + break; } +} -#undef PRODUCES_RESULT - return buf; +void ia32_emit_source_register_or_immediate(const ir_node *node, int pos) +{ + ir_node *in = get_irn_n(node, pos); + if(is_ia32_Immediate(in)) { + emit_ia32_Immediate(in); + } else { + const ir_mode *mode = get_ia32_ls_mode(node); + const arch_register_t *reg = get_in_reg(node, pos); + emit_register(reg, mode); + } } /** - * Returns the xxx PTR string for a given mode - * - * @param mode the mode - * @param x87_insn if non-zero returns the string for a x87 instruction - * else for a SSE instruction + * Emits registers and/or address mode of a binary operation. */ -static const char *pointer_size(ir_mode *mode, int x87_insn) -{ - if (mode) { - switch (get_mode_size_bits(mode)) { - case 8: return "BYTE PTR"; - case 16: return "WORD PTR"; - case 32: return "DWORD PTR"; - case 64: - if (x87_insn) - return "QWORD PTR"; - return NULL; - case 80: - case 96: return "XWORD PTR"; - default: return NULL; +void ia32_emit_binop(const ir_node *node) { + const ir_node *right_op = get_irn_n(node, n_ia32_binary_right); + const ir_mode *mode = get_ia32_ls_mode(node); + const arch_register_t *reg_left; + + switch(get_ia32_op_type(node)) { + case ia32_Normal: + reg_left = get_in_reg(node, n_ia32_binary_left); + if(is_ia32_Immediate(right_op)) { + emit_ia32_Immediate(right_op); + be_emit_cstring(", "); + emit_register(reg_left, mode); + break; + } else { + const arch_register_t *reg_right + = get_in_reg(node, n_ia32_binary_right); + emit_register(reg_right, mode); + be_emit_cstring(", "); + emit_register(reg_left, mode); } + break; + case ia32_AddrModeS: + if(is_ia32_Immediate(right_op)) { + emit_ia32_Immediate(right_op); + be_emit_cstring(", "); + ia32_emit_am(node); + } else { + reg_left = get_in_reg(node, n_ia32_binary_left); + ia32_emit_am(node); + be_emit_cstring(", "); + emit_register(reg_left, mode); + } + break; + case ia32_AddrModeD: + panic("DestMode can't be output by %%binop anymore"); + break; + default: + assert(0 && "unsupported op type"); } - return NULL; } /** * Emits registers and/or address mode of a binary operation. */ -const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) { - static char *buf = NULL; - - /* verify that this function is never called on non-AM supporting operations */ - //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support"); - - if (! buf) { - buf = xcalloc(1, SNPRINTF_BUF_LEN); - } - else { - memset(buf, 0, SNPRINTF_BUF_LEN); - } - - switch(get_ia32_op_type(n)) { +void ia32_emit_x87_binop(const ir_node *node) { + switch(get_ia32_op_type(node)) { case ia32_Normal: - if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) { - ir_mode *mode = get_ia32_ls_mode(n); - const char *p = pointer_size(mode, 1); - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n)); - } - else { - ia32_attr_t *attr = get_ia32_attr(n); - const arch_register_t *in1 = attr->x87[0]; - const arch_register_t *in2 = attr->x87[1]; - const arch_register_t *out = attr->x87[2]; + { + const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node); + const arch_register_t *in1 = x87_attr->x87[0]; + const arch_register_t *in2 = x87_attr->x87[1]; + const arch_register_t *out = x87_attr->x87[2]; const arch_register_t *in; - const char *in_name; - in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2; - out = out ? out : in1; - in_name = arch_register_get_name(in); + in = out ? ((out == in2) ? in1 : in2) : in2; + out = out ? out : in1; - snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name); + be_emit_char('%'); + be_emit_string(arch_register_get_name(in)); + be_emit_cstring(", %"); + be_emit_string(arch_register_get_name(out)); } break; case ia32_AddrModeS: - case ia32_AddrModeD: - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env)); + ia32_emit_am(node); break; + case ia32_AddrModeD: default: assert(0 && "unsupported op type"); } +} - return buf; +void ia32_emit_am_or_dest_register(const ir_node *node, + int pos) { + if(get_ia32_op_type(node) == ia32_Normal) { + ia32_emit_dest_register(node, pos); + } else { + assert(get_ia32_op_type(node) == ia32_AddrModeD); + ia32_emit_am(node); + } } /** * Emits registers and/or address mode of a unary operation. */ -const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) { - static char *buf = NULL; - - if (! buf) { - buf = xcalloc(1, SNPRINTF_BUF_LEN); - } - else { - memset(buf, 0, SNPRINTF_BUF_LEN); - } - - switch(get_ia32_op_type(n)) { - case ia32_Normal: - if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) { - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n); - } - else { - if (is_ia32_MulS(n) || is_ia32_Mulh(n)) { - /* MulS and Mulh implicitly multiply by EAX */ - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n); - } - else - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n); - } - break; - case ia32_AddrModeD: - snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env)); - break; - case ia32_AddrModeS: - /* - Mulh is emitted via emit_unop - imul [MEM] means EDX:EAX <- EAX * [MEM] - */ - assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop"); - lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env)); - break; - default: - assert(0 && "unsupported op type"); +void ia32_emit_unop(const ir_node *node, int pos) { + const ir_node *op; + + switch(get_ia32_op_type(node)) { + case ia32_Normal: + op = get_irn_n(node, pos); + if (is_ia32_Immediate(op)) { + emit_ia32_Immediate(op); + } else { + ia32_emit_source_register(node, pos); + } + break; + case ia32_AddrModeS: + case ia32_AddrModeD: + ia32_emit_am(node); + break; + default: + assert(0 && "unsupported op type"); } - - return buf; } /** * Emits address mode. */ -const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) { - ia32_am_flavour_t am_flav = get_ia32_am_flavour(n); - int had_output = 0; - char *s; - const char *p; - static struct obstack *obst = NULL; - ir_mode *mode = get_ia32_ls_mode(n); - - if (! is_ia32_Lea(n)) - assert(mode && "AM node must have ls_mode attribute set."); - - if (! obst) { - obst = xcalloc(1, sizeof(*obst)); - } - else { - obstack_free(obst, NULL); - } - - /* obstack_free with NULL results in an uninitialized obstack */ - obstack_init(obst); - - p = pointer_size(mode, has_x87_register(n)); - if (p) - obstack_printf(obst, "%s ", p); - - /* emit address mode symconst */ - if (get_ia32_am_sc(n)) { - if (is_ia32_am_sc_sign(n)) - obstack_printf(obst, "-"); - obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n))); - } - - if (am_flav & ia32_B) { - obstack_printf(obst, "["); - lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n); - had_output = 1; +void ia32_emit_am(const ir_node *node) { + ir_entity *ent = get_ia32_am_sc(node); + int offs = get_ia32_am_offs_int(node); + ir_node *base = get_irn_n(node, 0); + int has_base = !is_ia32_NoReg_GP(base); + ir_node *index = get_irn_n(node, 1); + int has_index = !is_ia32_NoReg_GP(index); + + /* just to be sure... */ + assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL); + + /* emit offset */ + if (ent != NULL) { + ident *id; + + set_entity_backend_marked(ent, 1); + id = get_entity_ld_ident(ent); + if (is_ia32_am_sc_sign(node)) + be_emit_char('-'); + be_emit_ident(id); + + if(get_entity_owner(ent) == get_tls_type()) { + if (get_entity_visibility(ent) == visibility_external_allocated) { + be_emit_cstring("@INDNTPOFF"); + } else { + be_emit_cstring("@NTPOFF"); + } + } } - if (am_flav & ia32_I) { - if (had_output) { - obstack_printf(obst, "+"); - } - else { - obstack_printf(obst, "["); + if(offs != 0) { + if(ent != NULL) { + be_emit_irprintf("%+d", offs); + } else { + be_emit_irprintf("%d", offs); } + } - lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n); + if (has_base || has_index) { + be_emit_char('('); - if (am_flav & ia32_S) { - obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n)); + /* emit base */ + if (has_base) { + const arch_register_t *reg = get_in_reg(node, n_ia32_base); + emit_register(reg, NULL); } - had_output = 1; - } - - if (am_flav & ia32_O) { - s = get_ia32_am_offs(n); + /* emit index + scale */ + if (has_index) { + const arch_register_t *reg = get_in_reg(node, n_ia32_index); + int scale; + be_emit_char(','); + emit_register(reg, NULL); - if (s) { - /* omit explicit + if there was no base or index */ - if (! had_output) { - obstack_printf(obst, "["); - if (s[0] == '+') - s++; + scale = get_ia32_am_scale(node); + if (scale > 0) { + be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node)); } - - obstack_printf(obst, s); - had_output = 1; } + be_emit_char(')'); } - if (had_output) - obstack_printf(obst, "] "); - - obstack_1grow(obst, '\0'); - s = obstack_finish(obst); - - return s; + /* special case if nothing is set */ + if(ent == NULL && offs == 0 && !has_base && !has_index) { + be_emit_char('0'); + } } -/** - * emit an address - */ -const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env) +static void emit_ia32_IMul(const ir_node *node) { - static char buf[SNPRINTF_BUF_LEN]; - ir_mode *mode = get_ia32_ls_mode(irn); - const char *adr = get_ia32_cnst(irn); - const char *pref = pointer_size(mode, has_x87_register(irn)); - - snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr); - return buf; -} - -/** - * Formated print of commands and comments. - */ -static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) { - unsigned lineno; - const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL; - - if (name) - fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno); - else - fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf); -} + ir_node *left = get_irn_n(node, n_ia32_IMul_left); + const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res); + be_emit_cstring("\timul"); + ia32_emit_mode_suffix(node); + be_emit_char(' '); + ia32_emit_binop(node); -/** - * Add a number to a prefix. This number will not be used a second time. - */ -static char *get_unique_label(char *buf, size_t buflen, const char *prefix) { - static unsigned long id = 0; - snprintf(buf, buflen, "%s%lu", prefix, ++id); - return buf; + /* do we need the 3-address form? */ + if(is_ia32_NoReg_GP(left) || + get_in_reg(node, n_ia32_IMul_left) != out_reg) { + be_emit_cstring(", "); + emit_register(out_reg, get_ia32_ls_mode(node)); + } + be_emit_finish_line_gas(node); } - - /************************************************* * _ _ _ * (_) | | | @@ -704,29 +601,21 @@ static char *get_unique_label(char *buf, size_t buflen, const char *prefix) { */ struct cmp2conditon_t { const char *name; - pn_Cmp num; + int num; }; /* * positive conditions for signed compares */ static const struct cmp2conditon_t cmp2condition_s[] = { - { NULL, pn_Cmp_False }, /* always false */ - { "e", pn_Cmp_Eq }, /* == */ - { "l", pn_Cmp_Lt }, /* < */ - { "le", pn_Cmp_Le }, /* <= */ - { "g", pn_Cmp_Gt }, /* > */ - { "ge", pn_Cmp_Ge }, /* >= */ - { "ne", pn_Cmp_Lg }, /* != */ - { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */ - { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */ - { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */ - { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */ - { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */ - { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */ - { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */ - { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */ - { NULL, pn_Cmp_True }, /* always true */ + { NULL, pn_Cmp_False }, /* always false */ + { "e", pn_Cmp_Eq }, /* == */ + { "l", pn_Cmp_Lt }, /* < */ + { "le", pn_Cmp_Le }, /* <= */ + { "g", pn_Cmp_Gt }, /* > */ + { "ge", pn_Cmp_Ge }, /* >= */ + { "ne", pn_Cmp_Lg }, /* != */ + { NULL, pn_Cmp_Leg}, /* always true */ }; /* @@ -740,432 +629,347 @@ static const struct cmp2conditon_t cmp2condition_u[] = { { "a", pn_Cmp_Gt }, /* > */ { "ae", pn_Cmp_Ge }, /* >= */ { "ne", pn_Cmp_Lg }, /* != */ - { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */ - { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */ - { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */ - { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */ - { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */ - { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */ - { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */ - { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */ - { NULL, pn_Cmp_True }, /* always true */ + { NULL, pn_Cmp_Leg }, /* always true */ }; -/* - * returns the condition code - */ -static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp) -{ - assert(cmp2condition_s[cmp_code].num == cmp_code); - assert(cmp2condition_u[cmp_code].num == cmp_code); - - return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name; -} - -/** - * Returns the target block for a control flow node. - */ -static ir_node *get_cfop_target_block(const ir_node *irn) { - return get_irn_link(irn); -} +enum { + ia32_pn_Cmp_unsigned = 0x1000, + ia32_pn_Cmp_float = 0x2000, +}; /** - * Returns the target label for a control flow node. + * walks up a tree of copies/perms/spills/reloads to find the original value + * that is moved around */ -static char *get_cfop_target(const ir_node *irn, char *buf) { - ir_node *bl = get_cfop_target_block(irn); - - snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl)); - return buf; -} - -/** Return the next block in Block schedule */ -static ir_node *next_blk_sched(const ir_node *block) { - return get_irn_link(block); +static ir_node *find_original_value(ir_node *node) +{ + inc_irg_visited(current_ir_graph); + while(1) { + mark_irn_visited(node); + if(be_is_Copy(node)) { + node = be_get_Copy_op(node); + } else if(be_is_CopyKeep(node)) { + node = be_get_CopyKeep_op(node); + } else if(is_Proj(node)) { + ir_node *pred = get_Proj_pred(node); + if(be_is_Perm(pred)) { + node = get_irn_n(pred, get_Proj_proj(node)); + } else if(be_is_MemPerm(pred)) { + node = get_irn_n(pred, get_Proj_proj(node) + 1); + } else if(is_ia32_Load(pred)) { + node = get_irn_n(pred, n_ia32_Load_mem); + } else { + return node; + } + } else if(is_ia32_Store(node)) { + node = get_irn_n(node, n_ia32_Store_val); + } else if(is_Phi(node)) { + int i, arity; + arity = get_irn_arity(node); + for(i = 0; i < arity; ++i) { + ir_node *in = get_irn_n(node, i); + if(irn_visited(in)) + continue; + node = in; + break; + } + assert(i < arity); + } else { + return node; + } + } } -/** - * Returns the Proj with projection number proj and NOT mode_M - */ -static ir_node *get_proj(const ir_node *irn, long proj) { - const ir_edge_t *edge; - ir_node *src; - - assert(get_irn_mode(irn) == mode_T && "expected mode_T node"); +static int determine_final_pnc(const ir_node *node, int flags_pos, + int pnc) +{ + ir_node *flags = get_irn_n(node, flags_pos); + const ia32_attr_t *flags_attr; + flags = skip_Proj(flags); + + if(is_ia32_Sahf(flags)) { + ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val); + if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp) + || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) { + cmp = find_original_value(cmp); + assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp) + || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp)); + } - foreach_out_edge(irn, edge) { - src = get_edge_src_irn(edge); + flags_attr = get_ia32_attr_const(cmp); + if(flags_attr->data.ins_permuted) + pnc = get_mirrored_pnc(pnc); + pnc |= ia32_pn_Cmp_float; + } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags) + || is_ia32_Fucompi(flags)) { + flags_attr = get_ia32_attr_const(flags); - assert(is_Proj(src) && "Proj expected"); - if (get_irn_mode(src) == mode_M) - continue; + if(flags_attr->data.ins_permuted) + pnc = get_mirrored_pnc(pnc); + pnc |= ia32_pn_Cmp_float; + } else { + assert(is_ia32_Cmp(flags) || is_ia32_Test(flags) + || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags)); + flags_attr = get_ia32_attr_const(flags); - if (get_Proj_proj(src) == proj) - return src; + if(flags_attr->data.ins_permuted) + pnc = get_mirrored_pnc(pnc); + if(flags_attr->data.cmp_unsigned) + pnc |= ia32_pn_Cmp_unsigned; } - return NULL; -} -/** - * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false) - */ -static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) { - const ir_node *proj1, *proj2 = NULL; - const ir_node *block, *next_bl = NULL; - char buf[SNPRINTF_BUF_LEN]; - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - - /* get both Proj's */ - proj1 = get_proj(irn, pn_Cond_true); - assert(proj1 && "CondJmp without true Proj"); + return pnc; +} - proj2 = get_proj(irn, pn_Cond_false); - assert(proj2 && "CondJmp without false Proj"); +static void ia32_emit_cmp_suffix(int pnc) +{ + const char *str; - /* for now, the code works for scheduled and non-schedules blocks */ - block = get_nodes_block(irn); + if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) { + pnc = pnc & 7; + assert(cmp2condition_u[pnc].num == pnc); + str = cmp2condition_u[pnc].name; + } else { + pnc = pnc & 7; + assert(cmp2condition_s[pnc].num == pnc); + str = cmp2condition_s[pnc].name; + } - /* we have a block schedule */ - next_bl = next_blk_sched(block); + be_emit_string(str); +} - if (get_cfop_target_block(proj1) == next_bl) { - /* exchange both proj's so the second one can be omitted */ - const ir_node *t = proj1; - proj1 = proj2; - proj2 = t; - } +void ia32_emit_cmp_suffix_node(const ir_node *node, + int flags_pos) +{ + const ia32_attr_t *attr = get_ia32_attr_const(node); - /* the first Proj must always be created */ - if (get_Proj_proj(proj1) == pn_Cond_true) { - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s", - get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))), - get_cfop_target(proj1, buf)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == TRUE */"); - } - else { - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s", - get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode), - ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))), - get_cfop_target(proj1, buf)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == FALSE */"); - } - IA32_DO_EMIT(irn); + pn_Cmp pnc = get_ia32_condcode(node); - /* the second Proj might be a fallthrough */ - if (get_cfop_target_block(proj2) != next_bl) { - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */"); - } - else { - cmd_buf[0] = '\0'; - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj2, buf)); + pnc = determine_final_pnc(node, flags_pos, pnc); + if(attr->data.ins_permuted) { + if(pnc & ia32_pn_Cmp_float) { + pnc = get_negated_pnc(pnc, mode_F); + } else { + pnc = get_negated_pnc(pnc, mode_Iu); + } } - IA32_DO_EMIT(irn); -} - -/** - * Emits code for conditional jump. - */ -static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) { - FILE *F = env->out; - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env)); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn); - IA32_DO_EMIT(irn); - finish_CondJmp(F, irn, get_ia32_res_mode(irn)); + ia32_emit_cmp_suffix(pnc); } /** - * Emits code for conditional jump with two variables. + * Returns the target block for a control flow node. */ -static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) { - CondJmp_emitter(irn, env); +static +ir_node *get_cfop_target_block(const ir_node *irn) { + return get_irn_link(irn); } /** - * Emits code for conditional test and jump. + * Emits a block label for the given block. */ -static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) { - -#define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) - - FILE *F = env->out; - const char *op1 = arch_register_get_name(get_in_reg(irn, 0)); - const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL; - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - - if (! op2) - op2 = arch_register_get_name(get_in_reg(irn, 1)); - - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn); - - IA32_DO_EMIT(irn); - finish_CondJmp(F, irn, get_ia32_res_mode(irn)); - -#undef IA32_IS_IMMOP +static +void ia32_emit_block_name(const ir_node *block) +{ + if (has_Block_label(block)) { + be_emit_string(be_gas_label_prefix()); + be_emit_irprintf("%u", (unsigned)get_Block_label(block)); + } else { + be_emit_cstring(BLOCK_PREFIX); + be_emit_irprintf("%d", get_irn_node_nr(block)); + } } /** - * Emits code for conditional test and jump with two variables. + * Emits the target label for a control flow node. */ -static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) { - TestJmp_emitter(irn, env); -} - -static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) { - FILE *F = env->out; - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - - snprintf(cmd_buf, SNPRINTF_BUF_LEN, " "); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn); - IA32_DO_EMIT(irn); - finish_CondJmp(F, irn, get_ia32_res_mode(irn)); -} - -static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) { - FILE *F = env->out; - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; +static void ia32_emit_cfop_target(const ir_node *node) +{ + ir_node *block = get_cfop_target_block(node); - snprintf(cmd_buf, SNPRINTF_BUF_LEN, " "); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn); - IA32_DO_EMIT(irn); - finish_CondJmp(F, irn, get_ia32_res_mode(irn)); + ia32_emit_block_name(block); } -/** - * Emits code for conditional SSE floating point jump with two variables. - */ -static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) { - FILE *F = env->out; - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env)); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn); - IA32_DO_EMIT(irn); - finish_CondJmp(F, irn, get_ia32_res_mode(irn)); - +/** Return the next block in Block schedule */ +static ir_node *next_blk_sched(const ir_node *block) +{ + return get_irn_link(block); } /** - * Emits code for conditional x87 floating point jump with two variables. + * Returns the Proj with projection number proj and NOT mode_M */ -static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) { - FILE *F = env->out; - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - ia32_attr_t *attr = get_ia32_attr(irn); - const char *reg = attr->x87[1]->name; - const char *instr = "fcom"; - int reverse = 0; - - switch (get_ia32_pncode(irn)) { - case iro_ia32_fcomrJmp: - reverse = 1; - case iro_ia32_fcomJmp: - default: - instr = "fucom"; - break; - case iro_ia32_fcomrpJmp: - reverse = 1; - case iro_ia32_fcompJmp: - instr = "fucomp"; - break; - case iro_ia32_fcomrppJmp: - reverse = 1; - case iro_ia32_fcomppJmp: - instr = "fucompp"; - reg = ""; - break; - } - - if (reverse) - set_ia32_pncode(irn, (long)get_negated_pnc(get_ia32_pncode(irn), mode_Is)); - - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %%%s", instr, reg); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn); - IA32_DO_EMIT(irn); - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */"); - IA32_DO_EMIT(irn); - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf"); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */"); - IA32_DO_EMIT(irn); - - finish_CondJmp(F, irn, mode_Is); -} - -static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) { - FILE *F = env->out; - const lc_arg_env_t *arg_env = ia32_get_arg_env(); - const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))); - int is_PsiCondCMov = is_ia32_PsiCondCMov(irn); - - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - const arch_register_t *in1, *in2, *out; +static ir_node *get_proj(const ir_node *node, long proj) { + const ir_edge_t *edge; + ir_node *src; - out = arch_get_irn_register(env->arch_env, irn); - in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2 - is_PsiCondCMov)); - in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3 - is_PsiCondCMov)); + assert(get_irn_mode(node) == mode_T && "expected mode_T node"); - /* we have to emit the cmp first, because the destination register */ - /* could be one of the compare registers */ - if (is_ia32_CmpCMov(irn)) { - lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn); - } - else if (is_ia32_xCmpCMov(irn)) { - lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn); - } - else if (is_PsiCondCMov) { - /* omit compare because flags are already set by And/Or */ - snprintf(cmd_buf, SNPRINTF_BUF_LEN, " "); - } - else { - assert(0 && "unsupported CMov"); - } - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" ); - IA32_DO_EMIT(irn); - - if (REGS_ARE_EQUAL(out, in2)) { - /* best case: default in == out -> do nothing */ - } - else if (REGS_ARE_EQUAL(out, in1)) { - /* true in == out -> need complement compare and exchange true and default in */ - ir_node *t = get_irn_n(irn, 2); - set_irn_n(irn, 2, get_irn_n(irn, 3)); - set_irn_n(irn, 3, t); + foreach_out_edge(node, edge) { + src = get_edge_src_irn(edge); - cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))); + assert(is_Proj(src) && "Proj expected"); + if (get_irn_mode(src) == mode_M) + continue; + if (get_Proj_proj(src) == proj) + return src; } - else { - /* out is different from in: need copy default -> out */ - lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn); - lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" ); - IA32_DO_EMIT(irn); - } - - lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn); - lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" ); - IA32_DO_EMIT(irn); -} - -static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) { - CMov_emitter(irn, env); -} - -static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) { - CMov_emitter(irn, env); + return NULL; } -static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) { - CMov_emitter(irn, env); -} +/** + * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false) + */ +static void emit_ia32_Jcc(const ir_node *node) +{ + const ir_node *proj_true; + const ir_node *proj_false; + const ir_node *block; + const ir_node *next_block; + pn_Cmp pnc = get_ia32_condcode(node); -static void Set_emitter(ir_node *irn, ia32_emit_env_t *env) { - FILE *F = env->out; - const lc_arg_env_t *arg_env = ia32_get_arg_env(); - const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))); - const char *instr = "xor"; - const char *reg8bit; + pnc = determine_final_pnc(node, 0, pnc); - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - const arch_register_t *out; + /* get both Projs */ + proj_true = get_proj(node, pn_ia32_Jcc_true); + assert(proj_true && "Jcc without true Proj"); - out = arch_get_irn_register(env->arch_env, irn); - reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out); + proj_false = get_proj(node, pn_ia32_Jcc_false); + assert(proj_false && "Jcc without false Proj"); - if (env->isa->opt_arch == arch_pentium_4) { - /* P4 prefers sub r, r, others xor r, r */ - instr = "sub"; - } + block = get_nodes_block(node); + next_block = next_blk_sched(block); - if (is_ia32_CmpSet(irn)) { - lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env)); - } - else if (is_ia32_xCmpSet(irn)) { - lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 0), ia32_emit_binop(irn, env)); - } - else if (is_ia32_PsiCondSet(irn)) { - /* omit compare because flags are already set by And/Or */ - snprintf(cmd_buf, SNPRINTF_BUF_LEN, " "); - } - else { - assert(0 && "unsupported Set"); + if (get_cfop_target_block(proj_true) == next_block) { + /* exchange both proj's so the second one can be omitted */ + const ir_node *t = proj_true; + + proj_true = proj_false; + proj_false = t; + if(pnc & ia32_pn_Cmp_float) { + pnc = get_negated_pnc(pnc, mode_F); + } else { + pnc = get_negated_pnc(pnc, mode_Iu); + } } - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" ); - IA32_DO_EMIT(irn); - /* use mov to clear target because it doesn't affect the eflags */ - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */"); - IA32_DO_EMIT(irn); + if (pnc & ia32_pn_Cmp_float) { + /* Some floating point comparisons require a test of the parity flag, + * which indicates that the result is unordered */ + switch (pnc & 15) { + case pn_Cmp_Uo: + be_emit_cstring("\tjp "); + ia32_emit_cfop_target(proj_true); + be_emit_finish_line_gas(proj_true); + break; - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" ); - IA32_DO_EMIT(irn); -} + case pn_Cmp_Leg: + be_emit_cstring("\tjnp "); + ia32_emit_cfop_target(proj_true); + be_emit_finish_line_gas(proj_true); + break; -static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) { - Set_emitter(irn, env); -} + case pn_Cmp_Eq: + case pn_Cmp_Lt: + case pn_Cmp_Le: + be_emit_cstring("\tjp "); + ia32_emit_cfop_target(proj_false); + be_emit_finish_line_gas(proj_false); + goto emit_jcc; + + case pn_Cmp_Ug: + case pn_Cmp_Uge: + case pn_Cmp_Ne: + be_emit_cstring("\tjp "); + ia32_emit_cfop_target(proj_true); + be_emit_finish_line_gas(proj_true); + goto emit_jcc; -static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) { - Set_emitter(irn, env); -} + default: + goto emit_jcc; + } + } else { +emit_jcc: + be_emit_cstring("\tj"); + ia32_emit_cmp_suffix(pnc); + be_emit_char(' '); + ia32_emit_cfop_target(proj_true); + be_emit_finish_line_gas(proj_true); + } -static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) { - Set_emitter(irn, env); + /* the second Proj might be a fallthrough */ + if (get_cfop_target_block(proj_false) != next_block) { + be_emit_cstring("\tjmp "); + ia32_emit_cfop_target(proj_false); + be_emit_finish_line_gas(proj_false); + } else { + be_emit_cstring("\t/* fallthrough to "); + ia32_emit_cfop_target(proj_false); + be_emit_cstring(" */"); + be_emit_finish_line_gas(proj_false); + } } -static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) { - FILE *F = env->out; - const lc_arg_env_t *arg_env = ia32_get_arg_env(); - int sse_pnc = -1; - char cmd_buf[SNPRINTF_BUF_LEN]; - char cmnt_buf[SNPRINTF_BUF_LEN]; - - switch (get_ia32_pncode(irn)) { - case pn_Cmp_Leg: /* odered */ - sse_pnc = 7; - break; - case pn_Cmp_Uo: /* unordered */ - sse_pnc = 3; - break; - case pn_Cmp_Ue: /* == */ - sse_pnc = 0; - break; - case pn_Cmp_Ul: /* < */ - sse_pnc = 1; - break; - case pn_Cmp_Ule: /* <= */ - sse_pnc = 2; - break; - case pn_Cmp_Ug: /* > */ - sse_pnc = 6; - break; - case pn_Cmp_Uge: /* >= */ - sse_pnc = 5; - break; - case pn_Cmp_Ne: /* != */ - sse_pnc = 4; - break; +static void emit_ia32_CMov(const ir_node *node) +{ + const ia32_attr_t *attr = get_ia32_attr_const(node); + int ins_permuted = attr->data.ins_permuted; + const arch_register_t *out = arch_get_irn_register(arch_env, node); + pn_Cmp pnc = get_ia32_condcode(node); + const arch_register_t *in_true; + const arch_register_t *in_false; + + pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc); + + in_true = arch_get_irn_register(arch_env, + get_irn_n(node, n_ia32_CMov_val_true)); + in_false = arch_get_irn_register(arch_env, + get_irn_n(node, n_ia32_CMov_val_false)); + + /* should be same constraint fullfilled? */ + if(out == in_false) { + /* yes -> nothing to do */ + } else if(out == in_true) { + const arch_register_t *tmp; + + assert(get_ia32_op_type(node) == ia32_Normal); + + ins_permuted = !ins_permuted; + + tmp = in_true; + in_true = in_false; + in_false = tmp; + } else { + /* we need a mov */ + be_emit_cstring("\tmovl "); + emit_register(in_false, NULL); + be_emit_cstring(", "); + emit_register(out, NULL); + be_emit_finish_line_gas(node); + } + + if(ins_permuted) { + if(pnc & ia32_pn_Cmp_float) { + pnc = get_negated_pnc(pnc, mode_F); + } else { + pnc = get_negated_pnc(pnc, mode_Iu); + } } - assert(sse_pnc >= 0 && "unsupported floating point compare"); + /* TODO: handling of Nans isn't correct yet */ - lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmps%M %s, %d", irn, ia32_emit_binop(irn, env), sse_pnc); - lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare with result in %1D */", irn); - IA32_DO_EMIT(irn); + be_emit_cstring("\tcmov"); + ia32_emit_cmp_suffix(pnc); + be_emit_char(' '); + if(get_ia32_op_type(node) == ia32_AddrModeS) { + ia32_emit_am(node); + } else { + emit_register(in_true, get_ia32_ls_mode(node)); + } + be_emit_cstring(", "); + emit_register(out, get_ia32_ls_mode(node)); + be_emit_finish_line_gas(node); } /********************************************************* @@ -1188,9 +992,9 @@ typedef struct _branch_t { /* jump table for switch generation */ typedef struct _jmp_tbl_t { ir_node *defProj; /**< default target */ - int min_value; /**< smallest switch case */ - int max_value; /**< largest switch case */ - int num_branches; /**< number of jumps */ + long min_value; /**< smallest switch case */ + long max_value; /**< largest switch case */ + long num_branches; /**< number of jumps */ char *label; /**< label of the jump table */ branch_t *branches; /**< jump array */ } jmp_tbl_t; @@ -1198,7 +1002,8 @@ typedef struct _jmp_tbl_t { /** * Compare two variables of type branch_t. Used to sort all switch cases */ -static int ia32_cmp_branch_t(const void *a, const void *b) { +static +int ia32_cmp_branch_t(const void *a, const void *b) { branch_t *b1 = (branch_t *)a; branch_t *b2 = (branch_t *)b; @@ -1213,43 +1018,41 @@ static int ia32_cmp_branch_t(const void *a, const void *b) { * possible otherwise a cmp-jmp cascade). Port from * cggg ia32 backend */ -static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) { +static +void emit_ia32_SwitchJmp(const ir_node *node) { unsigned long interval; - char buf[SNPRINTF_BUF_LEN]; - int last_value, i, pn; + int last_value, i; + long pnc; jmp_tbl_t tbl; ir_node *proj; const ir_edge_t *edge; - const lc_arg_env_t *env = ia32_get_arg_env(); - FILE *F = emit_env->out; - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; /* fill the table structure */ tbl.label = xmalloc(SNPRINTF_BUF_LEN); tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_"); tbl.defProj = NULL; - tbl.num_branches = get_irn_n_edges(irn); + tbl.num_branches = get_irn_n_edges(node); tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0])); tbl.min_value = INT_MAX; tbl.max_value = INT_MIN; i = 0; /* go over all proj's and collect them */ - foreach_out_edge(irn, edge) { + foreach_out_edge(node, edge) { proj = get_edge_src_irn(edge); assert(is_Proj(proj) && "Only proj allowed at SwitchJmp"); - pn = get_Proj_proj(proj); + pnc = get_Proj_proj(proj); /* create branch entry */ tbl.branches[i].target = proj; - tbl.branches[i].value = pn; + tbl.branches[i].value = pnc; - tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value; - tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value; + tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value; + tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value; /* check for default proj */ - if (pn == get_ia32_pncode(irn)) { + if (pnc == get_ia32_condcode(node)) { assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp"); tbl.defProj = proj; } @@ -1264,48 +1067,53 @@ static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) { interval = tbl.max_value - tbl.min_value; /* emit the table */ - lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */"); - IA32_DO_EMIT(irn); + be_emit_cstring("\tcmpl $"); + be_emit_irprintf("%u, ", interval); + ia32_emit_source_register(node, 0); + be_emit_finish_line_gas(node); - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */"); - IA32_DO_EMIT(irn); + be_emit_cstring("\tja "); + ia32_emit_cfop_target(tbl.defProj); + be_emit_finish_line_gas(node); if (tbl.num_branches > 1) { /* create table */ + be_emit_cstring("\tjmp *"); + be_emit_string(tbl.label); + be_emit_cstring("(,"); + ia32_emit_source_register(node, 0); + be_emit_cstring(",4)"); + be_emit_finish_line_gas(node); - lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */"); - IA32_DO_EMIT(irn); + be_gas_emit_switch_section(GAS_SECTION_RODATA); + be_emit_cstring("\t.align 4\n"); + be_emit_write_line(); - ia32_switch_section(F, SECTION_RODATA); - fprintf(F, "\t.align 4\n"); + be_emit_string(tbl.label); + be_emit_cstring(":\n"); + be_emit_write_line(); - fprintf(F, "%s:\n", tbl.label); - - snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value); - IA32_DO_EMIT(irn); + be_emit_cstring(".long "); + ia32_emit_cfop_target(tbl.branches[0].target); + be_emit_finish_line_gas(NULL); last_value = tbl.branches[0].value; for (i = 1; i < tbl.num_branches; ++i) { while (++last_value < tbl.branches[i].value) { - snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */"); - IA32_DO_EMIT(irn); + be_emit_cstring(".long "); + ia32_emit_cfop_target(tbl.defProj); + be_emit_finish_line_gas(NULL); } - snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value); - IA32_DO_EMIT(irn); + be_emit_cstring(".long "); + ia32_emit_cfop_target(tbl.branches[i].target); + be_emit_finish_line_gas(NULL); } - ia32_switch_section(F, SECTION_TEXT); - } - else { + be_gas_emit_switch_section(GAS_SECTION_TEXT); + } else { /* one jump is enough */ - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf)); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */"); - IA32_DO_EMIT(irn); + be_emit_cstring("\tjmp "); + ia32_emit_cfop_target(tbl.branches[0].target); + be_emit_finish_line_gas(node); } if (tbl.label) @@ -1317,53 +1125,206 @@ static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) { /** * Emits code for a unconditional jump. */ -static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) { - ir_node *block, *next_bl; - FILE *F = env->out; - char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; +static void emit_Jmp(const ir_node *node) +{ + ir_node *block, *next_block; /* for now, the code works for scheduled and non-schedules blocks */ - block = get_nodes_block(irn); + block = get_nodes_block(node); /* we have a block schedule */ - next_bl = next_blk_sched(block); - if (get_cfop_target_block(irn) != next_bl) { - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf)); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn)); + next_block = next_blk_sched(block); + if (get_cfop_target_block(node) != next_block) { + be_emit_cstring("\tjmp "); + ia32_emit_cfop_target(node); + } else { + be_emit_cstring("\t/* fallthrough to "); + ia32_emit_cfop_target(node); + be_emit_cstring(" */"); + } + be_emit_finish_line_gas(node); +} + +static void emit_ia32_Immediate(const ir_node *node) +{ + const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node); + + be_emit_char('$'); + if(attr->symconst != NULL) { + ident *id = get_entity_ld_ident(attr->symconst); + + if(attr->sc_sign) + be_emit_char('-'); + be_emit_ident(id); } - else { - cmd_buf[0] = '\0'; - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf)); + if(attr->symconst == NULL || attr->offset != 0) { + if(attr->symconst != NULL) { + be_emit_irprintf("%+d", attr->offset); + } else { + be_emit_irprintf("0x%X", attr->offset); + } } - IA32_DO_EMIT(irn); } -/**************************** - * _ - * (_) - * _ __ _ __ ___ _ ___ - * | '_ \| '__/ _ \| |/ __| - * | |_) | | | (_) | |\__ \ - * | .__/|_| \___/| ||___/ - * | | _/ | - * |_| |__/ - ****************************/ +/** + * Emit an inline assembler operand. + * + * @param node the ia32_ASM node + * @param s points to the operand (a %c) + * + * @return pointer to the first char in s NOT in the current operand + */ +static const char* emit_asm_operand(const ir_node *node, const char *s) +{ + const ia32_attr_t *ia32_attr = get_ia32_attr_const(node); + const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, + ia32_attr); + const arch_register_t *reg; + const ia32_asm_reg_t *asm_regs = attr->register_map; + const ia32_asm_reg_t *asm_reg; + const char *reg_name; + char c; + char modifier = 0; + int num = -1; + int p; + + assert(*s == '%'); + c = *(++s); + + /* parse modifiers */ + switch(c) { + case 0: + ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node); + be_emit_char('%'); + return s + 1; + case '%': + be_emit_char('%'); + return s + 1; + case 'w': + case 'b': + case 'h': + modifier = c; + ++s; + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + break; + default: + ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier " + "'%c' for asm op\n", node, c); + ++s; + break; + } + + /* parse number */ + sscanf(s, "%d%n", &num, &p); + if(num < 0) { + ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n", + node); + return s; + } else { + s += p; + } + + if(num < 0 || num >= ARR_LEN(asm_regs)) { + ir_fprintf(stderr, "Error: Custom assembler references invalid " + "input/output (%+F)\n", node); + return s; + } + asm_reg = & asm_regs[num]; + assert(asm_reg->valid); + + /* get register */ + if(asm_reg->use_input == 0) { + reg = get_out_reg(node, asm_reg->inout_pos); + } else { + ir_node *pred = get_irn_n(node, asm_reg->inout_pos); + + /* might be an immediate value */ + if(is_ia32_Immediate(pred)) { + emit_ia32_Immediate(pred); + return s; + } + reg = get_in_reg(node, asm_reg->inout_pos); + } + if(reg == NULL) { + ir_fprintf(stderr, "Warning: no register assigned for %d asm op " + "(%+F)\n", num, node); + return s; + } + + if(asm_reg->memory) { + be_emit_char('('); + } + + /* emit it */ + if(modifier != 0) { + be_emit_char('%'); + switch(modifier) { + case 'b': + reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg); + break; + case 'h': + reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg); + break; + case 'w': + reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg); + break; + default: + panic("Invalid asm op modifier"); + } + be_emit_string(reg_name); + } else { + emit_register(reg, asm_reg->mode); + } + + if(asm_reg->memory) { + be_emit_char(')'); + } + + return s; +} /** - * Emits code for a proj -> node + * Emits code for an ASM pseudo op. */ -static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) { - ir_node *pred = get_Proj_pred(irn); +static void emit_ia32_Asm(const ir_node *node) +{ + const void *gen_attr = get_irn_generic_attr_const(node); + const ia32_asm_attr_t *attr + = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr); + ident *asm_text = attr->asm_text; + const char *s = get_id_str(asm_text); - if (get_irn_op(pred) == op_Start) { - switch(get_Proj_proj(irn)) { - case pn_Start_X_initial_exec: - emit_Jmp(irn, env); - break; - default: - break; + be_emit_cstring("# Begin ASM \t"); + be_emit_finish_line_gas(node); + + if (s[0] != '\t') + be_emit_char('\t'); + + while(*s != 0) { + if(*s == '%') { + s = emit_asm_operand(node, s); + continue; + } else { + be_emit_char(*s); } + ++s; } + + be_emit_char('\n'); + be_emit_write_line(); + + be_emit_cstring("# End ASM\n"); + be_emit_write_line(); } /********************************** @@ -1380,70 +1341,54 @@ static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) { /** * Emit movsb/w instructions to make mov count divideable by 4 */ -static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) { - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; - - ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn); - - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld"); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */"); - - switch(rem) { - case 1: - IA32_DO_EMIT(NULL); - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb"); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */"); - break; - case 2: - IA32_DO_EMIT(NULL); - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw"); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */"); - break; - case 3: - IA32_DO_EMIT(NULL); - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb"); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */"); - IA32_DO_EMIT(NULL); - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw"); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */"); - break; +static void emit_CopyB_prolog(unsigned size) { + be_emit_cstring("\tcld"); + be_emit_finish_line_gas(NULL); + + switch (size) { + case 1: + be_emit_cstring("\tmovsb"); + be_emit_finish_line_gas(NULL); + break; + case 2: + be_emit_cstring("\tmovsw"); + be_emit_finish_line_gas(NULL); + break; + case 3: + be_emit_cstring("\tmovsb"); + be_emit_finish_line_gas(NULL); + be_emit_cstring("\tmovsw"); + be_emit_finish_line_gas(NULL); + break; } - - IA32_DO_EMIT(NULL); } /** * Emit rep movsd instruction for memcopy. */ -static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) { - FILE *F = emit_env->out; - tarval *tv = get_ia32_Immop_tarval(irn); - int rem = get_tarval_long(tv); - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; +static void emit_ia32_CopyB(const ir_node *node) +{ + unsigned size = get_ia32_copyb_size(node); - emit_CopyB_prolog(F, irn, rem); + emit_CopyB_prolog(size); - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd"); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */"); - IA32_DO_EMIT(irn); + be_emit_cstring("\trep movsd"); + be_emit_finish_line_gas(node); } /** * Emits unrolled memcopy. */ -static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) { - tarval *tv = get_ia32_Immop_tarval(irn); - int size = get_tarval_long(tv); - FILE *F = emit_env->out; - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; +static void emit_ia32_CopyB_i(const ir_node *node) +{ + unsigned size = get_ia32_copyb_size(node); - emit_CopyB_prolog(F, irn, size & 0x3); + emit_CopyB_prolog(size & 0x3); size >>= 2; while (size--) { - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd"); - snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */"); - IA32_DO_EMIT(irn); + be_emit_cstring("\tmovsd"); + be_emit_finish_line_gas(NULL); } } @@ -1462,119 +1407,126 @@ static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) { /** * Emit code for conversions (I, FP), (FP, I) and (FP, FP). */ -static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) { - FILE *F = emit_env->out; - const lc_arg_env_t *env = ia32_get_arg_env(); - ir_mode *src_mode = get_ia32_src_mode(irn); - ir_mode *tgt_mode = get_ia32_tgt_mode(irn); - char *from, *to, buf[64]; - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; - - from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si"; - to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si"; - - switch(get_ia32_op_type(irn)) { +static void emit_ia32_Conv_with_FP(const ir_node *node) +{ + ir_mode *ls_mode = get_ia32_ls_mode(node); + int ls_bits = get_mode_size_bits(ls_mode); + + be_emit_cstring("\tcvt"); + + if(is_ia32_Conv_I2FP(node)) { + if(ls_bits == 32) { + be_emit_cstring("si2ss"); + } else { + be_emit_cstring("si2sd"); + } + } else if(is_ia32_Conv_FP2I(node)) { + if(ls_bits == 32) { + be_emit_cstring("ss2si"); + } else { + be_emit_cstring("sd2si"); + } + } else { + assert(is_ia32_Conv_FP2FP(node)); + if(ls_bits == 32) { + be_emit_cstring("sd2ss"); + } else { + be_emit_cstring("ss2sd"); + } + } + be_emit_char(' '); + + switch(get_ia32_op_type(node)) { case ia32_Normal: - lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn); + ia32_emit_source_register(node, n_ia32_unary_op); break; case ia32_AddrModeS: - lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env)); + ia32_emit_am(node); break; default: assert(0 && "unsupported op type for Conv"); } - - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf); - lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode); - IA32_DO_EMIT(irn); + be_emit_cstring(", "); + ia32_emit_dest_register(node, 0); + be_emit_finish_line_gas(node); } -static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) { - emit_ia32_Conv_with_FP(irn, emit_env); +static void emit_ia32_Conv_I2FP(const ir_node *node) +{ + emit_ia32_Conv_with_FP(node); } -static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) { - emit_ia32_Conv_with_FP(irn, emit_env); +static void emit_ia32_Conv_FP2I(const ir_node *node) +{ + emit_ia32_Conv_with_FP(node); } -static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) { - emit_ia32_Conv_with_FP(irn, emit_env); +static void emit_ia32_Conv_FP2FP(const ir_node *node) +{ + emit_ia32_Conv_with_FP(node); } /** * Emits code for an Int conversion. */ -static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) { - FILE *F = emit_env->out; - const lc_arg_env_t *env = ia32_get_arg_env(); - char *move_cmd = "movzx"; - char *conv_cmd = NULL; - ir_mode *src_mode = get_ia32_src_mode(irn); - ir_mode *tgt_mode = get_ia32_tgt_mode(irn); - int n, m; - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; +static void emit_ia32_Conv_I2I(const ir_node *node) +{ + const char *sign_suffix; + ir_mode *smaller_mode = get_ia32_ls_mode(node); + int smaller_bits = get_mode_size_bits(smaller_mode); + int signed_mode; const arch_register_t *in_reg, *out_reg; - n = get_mode_size_bits(src_mode); - m = get_mode_size_bits(tgt_mode); + assert(!mode_is_float(smaller_mode)); + assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32); - if (mode_is_signed(n < m ? src_mode : tgt_mode)) { - move_cmd = "movsx"; - if (n == 8 || m == 8) - conv_cmd = "cbw"; - else if (n == 16 || m == 16) - conv_cmd = "cwde"; - else - assert(0 && "unsupported Conv_I2I"); + signed_mode = mode_is_signed(smaller_mode); + if(smaller_bits == 32) { + // this should not happen as it's no convert + assert(0); + sign_suffix = ""; + } else { + sign_suffix = signed_mode ? "s" : "z"; } - switch(get_ia32_op_type(irn)) { + out_reg = get_out_reg(node, 0); + + switch(get_ia32_op_type(node)) { case ia32_Normal: - in_reg = get_in_reg(irn, 2); - out_reg = get_out_reg(irn, 0); + in_reg = get_in_reg(node, n_ia32_unary_op); - if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) && - REGS_ARE_EQUAL(out_reg, in_reg) && - mode_is_signed(n < m ? src_mode : tgt_mode)) + if (in_reg == &ia32_gp_regs[REG_EAX] && + out_reg == &ia32_gp_regs[REG_EAX] && + signed_mode && + smaller_bits == 16) { /* argument and result are both in EAX and */ - /* signedness is ok: -> use converts */ - lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd); - } - else if (REGS_ARE_EQUAL(out_reg, in_reg) && - ! mode_is_signed(n < m ? src_mode : tgt_mode)) - { - /* argument and result are in the same register */ - /* and signedness is ok: -> use and with mask */ - int mask = (1 << (n < m ? n : m)) - 1; - lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask); - } - else { - /* use move w/o sign extension */ - lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s", - move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg)); + /* signedness is ok: -> use the smaller cwtl opcode */ + be_emit_cstring("\tcwtl"); + } else { + be_emit_cstring("\tmov"); + be_emit_string(sign_suffix); + ia32_emit_mode_suffix_mode(smaller_mode); + be_emit_cstring("l "); + emit_register(in_reg, smaller_mode); + be_emit_cstring(", "); + emit_register(out_reg, NULL); } - break; - case ia32_AddrModeS: - lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s", - move_cmd, irn, ia32_emit_am(irn, emit_env)); + case ia32_AddrModeS: { + be_emit_cstring("\tmov"); + be_emit_string(sign_suffix); + ia32_emit_mode_suffix_mode(smaller_mode); + be_emit_cstring("l "); + ia32_emit_am(node); + be_emit_cstring(", "); + emit_register(out_reg, NULL); break; + } default: assert(0 && "unsupported op type for Conv"); } - - lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */", - irn, n, src_mode, m, tgt_mode); - - IA32_DO_EMIT(irn); -} - -/** - * Emits code for an 8Bit Int conversion. - */ -void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) { - emit_ia32_Conv_I2I(irn, emit_env); + be_emit_finish_line_gas(node); } @@ -1591,159 +1543,286 @@ void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) { /** * Emits a backend call */ -static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) { - FILE *F = emit_env->out; - entity *ent = be_Call_get_entity(irn); - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; +static void emit_be_Call(const ir_node *node) +{ + ir_entity *ent = be_Call_get_entity(node); + be_emit_cstring("\tcall "); if (ent) { - snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent)); + set_entity_backend_marked(ent, 1); + be_emit_string(get_entity_ld_name(ent)); + } else { + const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr); + be_emit_char('*'); + emit_register(reg, NULL); } - else { - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr)); - } - - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn); - - IA32_DO_EMIT(irn); + be_emit_finish_line_gas(node); } /** * Emits code to increase stack pointer. */ -static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) { - FILE *F = emit_env->out; - unsigned offs = be_get_IncSP_offset(irn); - be_stack_dir_t dir = be_get_IncSP_direction(irn); - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; - - if (offs) { - if (dir == be_stack_dir_expand) - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs); - else - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, offs); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn); - } - else { - snprintf(cmd_buf, SNPRINTF_BUF_LEN, " "); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn); - } - - IA32_DO_EMIT(irn); -} +static void emit_be_IncSP(const ir_node *node) +{ + int offs = be_get_IncSP_offset(node); + const arch_register_t *reg = arch_get_irn_register(arch_env, node); -/** - * Emits code to set stack pointer. - */ -static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) { - FILE *F = emit_env->out; - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; + if (offs == 0) + return; - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn); - IA32_DO_EMIT(irn); + if (offs > 0) { + be_emit_cstring("\tsubl $"); + be_emit_irprintf("%u, ", offs); + emit_register(reg, NULL); + } else { + be_emit_cstring("\taddl $"); + be_emit_irprintf("%u, ", -offs); + emit_register(reg, NULL); + } + be_emit_finish_line_gas(node); } /** * Emits code for Copy/CopyKeep. */ -static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) { - FILE *F = emit_env->out; - const arch_env_t *aenv = emit_env->arch_env; - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; +static void Copy_emitter(const ir_node *node, const ir_node *op) +{ + const arch_register_t *in = arch_get_irn_register(arch_env, op); + const arch_register_t *out = arch_get_irn_register(arch_env, node); + ir_mode *mode; - if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) || - be_is_unknown_reg(arch_get_irn_register(aenv, op))) + if(in == out) { + return; + } + if(is_unknown_reg(in)) + return; + /* copies of vf nodes aren't real... */ + if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp]) return; - if (mode_is_float(get_irn_mode(irn))) - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn); - else - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn); - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn); - IA32_DO_EMIT(irn); + mode = get_irn_mode(node); + if (mode == mode_E) { + be_emit_cstring("\tmovsd "); + emit_register(in, NULL); + be_emit_cstring(", "); + emit_register(out, NULL); + } else { + be_emit_cstring("\tmovl "); + emit_register(in, NULL); + be_emit_cstring(", "); + emit_register(out, NULL); + } + be_emit_finish_line_gas(node); } -static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) { - Copy_emitter(irn, be_get_Copy_op(irn), emit_env); +static void emit_be_Copy(const ir_node *node) +{ + Copy_emitter(node, be_get_Copy_op(node)); } -static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) { - Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env); +static void emit_be_CopyKeep(const ir_node *node) +{ + Copy_emitter(node, be_get_CopyKeep_op(node)); } /** * Emits code for exchange. */ -static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) { - FILE *F = emit_env->out; - char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN]; - const arch_register_t *in1, *in2; - const arch_register_class_t *cls1, *cls2; +static void emit_be_Perm(const ir_node *node) +{ + const arch_register_t *in0, *in1; + const arch_register_class_t *cls0, *cls1; - in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0)); - in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1)); + in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0)); + in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1)); + cls0 = arch_register_get_class(in0); cls1 = arch_register_get_class(in1); - cls2 = arch_register_get_class(in2); - assert(cls1 == cls2 && "Register class mismatch at Perm"); - - if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) { - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn); - } - else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) { - lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, - "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn); + assert(cls0 == cls1 && "Register class mismatch at Perm"); + + if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) { + be_emit_cstring("\txchg "); + emit_register(in1, NULL); + be_emit_cstring(", "); + emit_register(in0, NULL); + be_emit_finish_line_gas(node); + } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) { + be_emit_cstring("\txorpd "); + emit_register(in1, NULL); + be_emit_cstring(", "); + emit_register(in0, NULL); + be_emit_finish_line_gas(NULL); + + be_emit_cstring("\txorpd "); + emit_register(in0, NULL); + be_emit_cstring(", "); + emit_register(in1, NULL); + be_emit_finish_line_gas(NULL); + + be_emit_cstring("\txorpd "); + emit_register(in1, NULL); + be_emit_cstring(", "); + emit_register(in0, NULL); + be_emit_finish_line_gas(node); + } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) { + /* is a NOP */ + } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) { + /* is a NOP */ + } else { + panic("unexpected register class in be_Perm (%+F)\n", node); } - else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) { - assert(0 && "Perm with vfp should not happen"); - } - else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) { - assert(0 && "Perm with st(X) should not happen"); - } - - lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn); - IA32_DO_EMIT(irn); } /** * Emits code for Constant loading. */ -static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) { - FILE *F = env->out; - char cmd_buf[256], cmnt_buf[256]; - const lc_arg_env_t *arg_env = ia32_get_arg_env(); - - if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) { - const char *instr = "xor"; - if (env->isa->opt_arch == arch_pentium_4) { - /* P4 prefers sub r, r, others xor r, r */ - instr = "sub"; +static void emit_ia32_Const(const ir_node *node) +{ + be_emit_cstring("\tmovl "); + emit_ia32_Immediate(node); + be_emit_cstring(", "); + ia32_emit_dest_register(node, 0); + + be_emit_finish_line_gas(node); +} + +/** + * Emits code to load the TLS base + */ +static void emit_ia32_LdTls(const ir_node *node) +{ + be_emit_cstring("\tmovl %gs:0, "); + ia32_emit_dest_register(node, 0); + be_emit_finish_line_gas(node); +} + +/* helper function for emit_ia32_Minus64Bit */ +static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst) +{ + be_emit_cstring("\tmovl "); + emit_register(src, NULL); + be_emit_cstring(", "); + emit_register(dst, NULL); + be_emit_finish_line_gas(node); +} + +/* helper function for emit_ia32_Minus64Bit */ +static void emit_neg(const ir_node* node, const arch_register_t *reg) +{ + be_emit_cstring("\tnegl "); + emit_register(reg, NULL); + be_emit_finish_line_gas(node); +} + +/* helper function for emit_ia32_Minus64Bit */ +static void emit_sbb0(const ir_node* node, const arch_register_t *reg) +{ + be_emit_cstring("\tsbbl $0, "); + emit_register(reg, NULL); + be_emit_finish_line_gas(node); +} + +/* helper function for emit_ia32_Minus64Bit */ +static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst) +{ + be_emit_cstring("\tsbbl "); + emit_register(src, NULL); + be_emit_cstring(", "); + emit_register(dst, NULL); + be_emit_finish_line_gas(node); +} + +/* helper function for emit_ia32_Minus64Bit */ +static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst) +{ + be_emit_cstring("\txchgl "); + emit_register(src, NULL); + be_emit_cstring(", "); + emit_register(dst, NULL); + be_emit_finish_line_gas(node); +} + +/* helper function for emit_ia32_Minus64Bit */ +static void emit_zero(const ir_node* node, const arch_register_t *reg) +{ + be_emit_cstring("\txorl "); + emit_register(reg, NULL); + be_emit_cstring(", "); + emit_register(reg, NULL); + be_emit_finish_line_gas(node); +} + +static void emit_ia32_Minus64Bit(const ir_node *node) +{ + const arch_register_t *in_lo = get_in_reg(node, 0); + const arch_register_t *in_hi = get_in_reg(node, 1); + const arch_register_t *out_lo = get_out_reg(node, 0); + const arch_register_t *out_hi = get_out_reg(node, 1); + + if (out_lo == in_lo) { + if (out_hi != in_hi) { + /* a -> a, b -> d */ + goto zero_neg; + } else { + /* a -> a, b -> b */ + goto normal_neg; } - lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n); - lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */"); - } - else { - if (get_ia32_op_type(n) == ia32_SymConst) { - lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n); - lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */"); + } else if (out_lo == in_hi) { + if (out_hi == in_lo) { + /* a -> b, b -> a */ + emit_xchg(node, in_lo, in_hi); + goto normal_neg; + } else { + /* a -> b, b -> d */ + emit_mov(node, in_hi, out_hi); + emit_mov(node, in_lo, out_lo); + goto normal_neg; } - else { - lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n); - lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */"); + } else { + if (out_hi == in_lo) { + /* a -> c, b -> a */ + emit_mov(node, in_lo, out_lo); + goto zero_neg; + } else if (out_hi == in_hi) { + /* a -> c, b -> b */ + emit_mov(node, in_lo, out_lo); + goto normal_neg; + } else { + /* a -> c, b -> d */ + emit_mov(node, in_lo, out_lo); + goto zero_neg; } } - lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n); + +normal_neg: + emit_neg( node, out_hi); + emit_neg( node, out_lo); + emit_sbb0(node, out_hi); + return; + +zero_neg: + emit_zero(node, out_hi); + emit_neg( node, out_lo); + emit_sbb( node, in_hi, out_hi); } -static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) { - FILE *F = env->out; - const lc_arg_env_t *arg_env = ia32_get_arg_env(); +static void emit_be_Return(const ir_node *node) +{ + unsigned pop; + be_emit_cstring("\tret"); - lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n); + pop = be_Return_get_pop(node); + if(pop > 0) { + be_emit_irprintf(" $%d", pop); + } + be_emit_finish_line_gas(node); } +static void emit_Nothing(const ir_node *node) +{ + (void) node; +} /*********************************************************************************** @@ -1760,12 +1839,15 @@ static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) { * Enters the emitter functions for handled nodes into the generic * pointer of an opcode. */ -static void ia32_register_emitters(void) { +static +void ia32_register_emitters(void) { #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b #define IA32_EMIT(a) IA32_EMIT2(a,a) #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a +#define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a +#define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing /* first clear the generic function pointer for all ops */ clear_irp_opcodes_generic_func(); @@ -1774,14 +1856,9 @@ static void ia32_register_emitters(void) { ia32_register_spec_emitters(); /* other ia32 emitter functions */ - IA32_EMIT(CondJmp); - IA32_EMIT(TestJmp); - IA32_EMIT(CJmp); - IA32_EMIT(CJmpAM); - IA32_EMIT(CmpCMov); - IA32_EMIT(PsiCondCMov); - IA32_EMIT(CmpSet); - IA32_EMIT(PsiCondSet); + IA32_EMIT(Asm); + IA32_EMIT(CMov); + IA32_EMIT(IMul); IA32_EMIT(SwitchJmp); IA32_EMIT(CopyB); IA32_EMIT(CopyB_i); @@ -1789,180 +1866,324 @@ static void ia32_register_emitters(void) { IA32_EMIT(Conv_FP2I); IA32_EMIT(Conv_FP2FP); IA32_EMIT(Conv_I2I); - IA32_EMIT(Conv_I2I8Bit); + IA32_EMIT2(Conv_I2I8Bit, Conv_I2I); IA32_EMIT(Const); - IA32_EMIT(xCmp); - IA32_EMIT(xCmpSet); - IA32_EMIT(xCmpCMov); - IA32_EMIT(xCondJmp); - IA32_EMIT2(fcomJmp, x87CondJmp); - IA32_EMIT2(fcompJmp, x87CondJmp); - IA32_EMIT2(fcomppJmp, x87CondJmp); - IA32_EMIT2(fcomrJmp, x87CondJmp); - IA32_EMIT2(fcomrpJmp, x87CondJmp); - IA32_EMIT2(fcomrppJmp, x87CondJmp); + IA32_EMIT(LdTls); + IA32_EMIT(Minus64Bit); + IA32_EMIT(Jcc); /* benode emitter */ BE_EMIT(Call); BE_EMIT(IncSP); - BE_EMIT(SetSP); BE_EMIT(Copy); BE_EMIT(CopyKeep); BE_EMIT(Perm); BE_EMIT(Return); + BE_IGN(RegParams); + BE_IGN(Barrier); + BE_IGN(Keep); + /* firm emitter */ EMIT(Jmp); - EMIT(Proj); + IGN(Proj); + IGN(Phi); + IGN(Start); #undef BE_EMIT #undef EMIT +#undef IGN #undef IA32_EMIT2 #undef IA32_EMIT } +static const char *last_name = NULL; +static unsigned last_line = -1; +static unsigned num = -1; + +/** + * Emit the debug support for node node. + */ +static void ia32_emit_dbg(const ir_node *node) +{ + dbg_info *db = get_irn_dbg_info(node); + unsigned lineno; + const char *fname = be_retrieve_dbg_info(db, &lineno); + + if (! cg->birg->main_env->options->stabs_debug_support) + return; + + if (fname) { + if (last_name != fname) { + last_line = -1; + be_dbg_include_begin(cg->birg->main_env->db_handle, fname); + last_name = fname; + } + if (last_line != lineno) { + char name[64]; + + snprintf(name, sizeof(name), ".LM%u", ++num); + last_line = lineno; + be_dbg_line(cg->birg->main_env->db_handle, lineno, name); + be_emit_string(name); + be_emit_cstring(":\n"); + be_emit_write_line(); + } + } +} + +typedef void (*emit_func_ptr) (const ir_node *); + /** * Emits code for a node. */ -static void ia32_emit_node(const ir_node *irn, void *env) { - ia32_emit_env_t *emit_env = env; - FILE *F = emit_env->out; - ir_op *op = get_irn_op(irn); - DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;) +static void ia32_emit_node(const ir_node *node) +{ + ir_op *op = get_irn_op(node); - DBG((mod, LEVEL_1, "emitting code for %+F\n", irn)); + DBG((dbg, LEVEL_1, "emitting code for %+F\n", node)); if (op->ops.generic) { - void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic; - (*emit)(irn, env); - } - else { - ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", irn, irn); + emit_func_ptr func = (emit_func_ptr) op->ops.generic; + ia32_emit_dbg(node); + (*func) (node); + } else { + emit_Nothing(node); + ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph); + abort(); } } /** * Emits gas alignment directives */ -static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) { - fprintf(F, "\t.p2align %u,,%u\n", align, skip); +static void ia32_emit_alignment(unsigned align, unsigned skip) +{ + be_emit_cstring("\t.p2align "); + be_emit_irprintf("%u,,%u\n", align, skip); + be_emit_write_line(); } /** * Emits gas alignment directives for Functions depended on cpu architecture. */ -static void ia32_emit_align_func(FILE *F, cpu_support cpu) { - unsigned align; unsigned maximum_skip; - - /* gcc doesn't emit alignment for p4 ?*/ - if (cpu == arch_pentium_4) - return; +static void ia32_emit_align_func(cpu_support cpu) +{ + unsigned align; + unsigned maximum_skip; switch (cpu) { case arch_i386: - align = 2; maximum_skip = 3; + align = 2; break; case arch_i486: - align = 4; maximum_skip = 15; + align = 4; break; case arch_k6: - align = 5; maximum_skip = 31; + align = 5; break; default: - align = 4; maximum_skip = 15; + align = 4; } - ia32_emit_alignment(F, align, maximum_skip); + maximum_skip = (1 << align) - 1; + ia32_emit_alignment(align, maximum_skip); } /** * Emits gas alignment directives for Labels depended on cpu architecture. */ -static void ia32_emit_align_label(FILE *F, cpu_support cpu) { +static void ia32_emit_align_label(cpu_support cpu) +{ unsigned align; unsigned maximum_skip; - /* gcc doesn't emit alignment for p4 ?*/ - if (cpu == arch_pentium_4) - return; - switch (cpu) { case arch_i386: - align = 2; maximum_skip = 3; + align = 2; break; case arch_i486: - align = 4; maximum_skip = 15; + align = 4; break; case arch_k6: - align = 5; maximum_skip = 7; + align = 5; break; default: - align = 4; maximum_skip = 7; + align = 4; } - ia32_emit_alignment(F, align, maximum_skip); + maximum_skip = (1 << align) - 1; + ia32_emit_alignment(align, maximum_skip); } /** - * Walks over the nodes in a block connected by scheduling edges - * and emits code for each node. + * Test wether a block should be aligned. + * For cpus in the P4/Athlon class it is useful to align jump labels to + * 16 bytes. However we should only do that if the alignment nops before the + * label aren't executed more often than we have jumps to the label. */ -static void ia32_gen_block(ir_node *block, void *env) { - ia32_emit_env_t *emit_env = env; - const ir_node *irn; - int need_label = block != get_irg_start_block(get_irn_irg(block)); +static int should_align_block(ir_node *block, ir_node *prev) +{ + static const double DELTA = .0001; + ir_exec_freq *exec_freq = cg->birg->exec_freq; + double block_freq; + double prev_freq = 0; /**< execfreq of the fallthrough block */ + double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */ + cpu_support cpu = isa->opt_arch; + int i, n_cfgpreds; + + if(exec_freq == NULL) + return 0; + if(cpu == arch_i386 || cpu == arch_i486) + return 0; + + block_freq = get_block_execfreq(exec_freq, block); + if(block_freq < DELTA) + return 0; + + n_cfgpreds = get_Block_n_cfgpreds(block); + for(i = 0; i < n_cfgpreds; ++i) { + ir_node *pred = get_Block_cfgpred_block(block, i); + double pred_freq = get_block_execfreq(exec_freq, pred); + + if(pred == prev) { + prev_freq += pred_freq; + } else { + jmp_freq += pred_freq; + } + } - if (! is_Block(block)) - return; + if(prev_freq < DELTA && !(jmp_freq < DELTA)) + return 1; + + jmp_freq /= prev_freq; + + switch (cpu) { + case arch_athlon: + case arch_athlon_64: + case arch_k6: + return jmp_freq > 3; + default: + return jmp_freq > 2; + } +} + +static void ia32_emit_block_header(ir_node *block, ir_node *prev) +{ + int n_cfgpreds; + int need_label; + int i, arity; + ir_exec_freq *exec_freq = cg->birg->exec_freq; + + n_cfgpreds = get_Block_n_cfgpreds(block); + need_label = (n_cfgpreds != 0); - if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) { - /* if the extended block scheduler is used, only leader blocks need - labels. */ - need_label = (block == get_extbb_leader(get_nodes_extbb(block))); + if (should_align_block(block, prev)) { + assert(need_label); + ia32_emit_align_label(isa->opt_arch); } - if (need_label) { - ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch); - fprintf(emit_env->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block)); + if(need_label) { + ia32_emit_block_name(block); + be_emit_char(':'); + + be_emit_pad_comment(); + be_emit_cstring(" /* preds:"); + + /* emit list of pred blocks in comment */ + arity = get_irn_arity(block); + for (i = 0; i < arity; ++i) { + ir_node *predblock = get_Block_cfgpred_block(block, i); + be_emit_irprintf(" %d", get_irn_node_nr(predblock)); + } + } else { + be_emit_cstring("\t/* "); + ia32_emit_block_name(block); + be_emit_cstring(": "); + } + if (exec_freq != NULL) { + be_emit_irprintf(" freq: %f", + get_block_execfreq(exec_freq, block)); } + be_emit_cstring(" */\n"); + be_emit_write_line(); +} + +/** + * Walks over the nodes in a block connected by scheduling edges + * and emits code for each node. + */ +static void ia32_gen_block(ir_node *block, ir_node *last_block) +{ + const ir_node *node; + + ia32_emit_block_header(block, last_block); - sched_foreach(block, irn) { - ia32_emit_node(irn, env); + /* emit the contents of the block */ + ia32_emit_dbg(block); + sched_foreach(block, node) { + ia32_emit_node(node); } } /** * Emits code for function start. */ -static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) { - entity *irg_ent = get_irg_entity(irg); +static void ia32_emit_func_prolog(ir_graph *irg) +{ + ir_entity *irg_ent = get_irg_entity(irg); const char *irg_name = get_entity_ld_name(irg_ent); - - fprintf(F, "\n"); - ia32_switch_section(F, SECTION_TEXT); - ia32_emit_align_func(F, cpu); + cpu_support cpu = isa->opt_arch; + const be_irg_t *birg = cg->birg; + + /* write the begin line (used by scripts processing the assembler... */ + be_emit_write_line(); + be_emit_cstring("# -- Begin "); + be_emit_string(irg_name); + be_emit_char('\n'); + be_emit_write_line(); + + be_gas_emit_switch_section(GAS_SECTION_TEXT); + be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi)); + ia32_emit_align_func(cpu); if (get_entity_visibility(irg_ent) == visibility_external_visible) { - fprintf(F, ".globl %s\n", irg_name); + be_emit_cstring(".global "); + be_emit_string(irg_name); + be_emit_char('\n'); + be_emit_write_line(); } - ia32_dump_function_object(F, irg_name); - fprintf(F, "%s:\n", irg_name); + ia32_emit_function_object(irg_name); + be_emit_string(irg_name); + be_emit_cstring(":\n"); + be_emit_write_line(); } /** * Emits code for function end */ -static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) { - const char *irg_name = get_entity_ld_name(get_irg_entity(irg)); +static void ia32_emit_func_epilog(ir_graph *irg) +{ + const char *irg_name = get_entity_ld_name(get_irg_entity(irg)); + const be_irg_t *birg = cg->birg; + + ia32_emit_function_size(irg_name); + be_dbg_method_end(birg->main_env->db_handle); - ia32_dump_function_size(F, irg_name); - fprintf(F, "\n"); + be_emit_cstring("# -- End "); + be_emit_string(irg_name); + be_emit_char('\n'); + be_emit_write_line(); + + be_emit_char('\n'); + be_emit_write_line(); } /** * Block-walker: * Sets labels for control flow nodes (jump target) - * TODO: Jump optimization */ -static void ia32_gen_labels(ir_node *block, void *env) { +static void ia32_gen_labels(ir_node *block, void *data) +{ ir_node *pred; int n = get_Block_n_cfgpreds(block); + (void) data; for (n--; n >= 0; n--) { pred = get_Block_cfgpred(block, n); @@ -1970,48 +2191,53 @@ static void ia32_gen_labels(ir_node *block, void *env) { } } +/** + * Emit an exception label if the current instruction can fail. + */ +void ia32_emit_exc_label(const ir_node *node) +{ + if (get_ia32_exc_label(node)) { + be_emit_irprintf(".EXL%u\n", 0); + be_emit_write_line(); + } +} + /** * Main driver. Emits the code for one routine. */ -void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) { - ia32_emit_env_t emit_env; +void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg) +{ ir_node *block; + ir_node *last_block = NULL; + int i, n; - emit_env.out = F; - emit_env.arch_env = cg->arch_env; - emit_env.cg = cg; - emit_env.isa = (ia32_isa_t *)cg->arch_env->isa; - FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter"); - - /* set the global arch_env (needed by print hooks) */ + cg = ia32_cg; + isa = (const ia32_isa_t*) cg->arch_env->isa; arch_env = cg->arch_env; ia32_register_emitters(); - ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch); - irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env); + ia32_emit_func_prolog(irg); + irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL); - if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) { - int i, n = ARR_LEN(cg->blk_sched); + n = ARR_LEN(cg->blk_sched); + for (i = 0; i < n;) { + ir_node *next_bl; - for (i = 0; i < n;) { - ir_node *next_bl; + block = cg->blk_sched[i]; + ++i; + next_bl = i < n ? cg->blk_sched[i] : NULL; - block = cg->blk_sched[i]; - ++i; - next_bl = i < n ? cg->blk_sched[i] : NULL; - - /* set here the link. the emitter expects to find the next block here */ - set_irn_link(block, next_bl); - ia32_gen_block(block, &emit_env); - } - } - else { - /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block - in the block schedule. As this number should NEVER be equal the next block, - we does not need a clear block link here. */ - irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env); + /* set here the link. the emitter expects to find the next block here */ + set_irn_link(block, next_bl); + ia32_gen_block(block, last_block); + last_block = block; } - ia32_emit_func_epilog(F, irg); + ia32_emit_func_epilog(irg); +} + +void ia32_init_emitter(void) +{ + FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter"); }