X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_emitter.c;h=4cd44f10d3da8e912347a84317c8f1f434f51a13;hb=a1a465eb2b3f54027b29f829423fffd0396937f4;hp=ec363f397440c557aeaf4b7759bc9b7659b5f8de;hpb=80fd56ac0ffd1de6c526a5c820a1ff31f659104b;p=libfirm

diff --git a/ir/be/ia32/ia32_emitter.c b/ir/be/ia32/ia32_emitter.c
index ec363f397..4cd44f10d 100644
--- a/ir/be/ia32/ia32_emitter.c
+++ b/ir/be/ia32/ia32_emitter.c
@@ -1,6 +1,6 @@
 /**
  * This file implements the node emitter.
- *
+ * @author Christian Wuerdig
  * $Id$
  */
 
@@ -20,9 +20,12 @@
 #include "irargs_t.h"
 #include "irprog_t.h"
 #include "iredges_t.h"
+#include "execfreq.h"
 
 #include "../besched_t.h"
 #include "../benode_t.h"
+#include "../beabi.h"
+#include "../be_dbgout.h"
 
 #include "ia32_emitter.h"
 #include "gen_ia32_emitter.h"
@@ -30,6 +33,7 @@
 #include "ia32_nodes_attr.h"
 #include "ia32_new_nodes.h"
 #include "ia32_map_regs.h"
+#include "bearch_ia32_t.h"
 
 #define BLOCK_PREFIX(x) ".L" x
 
@@ -46,12 +50,22 @@ asm_flavour_t asm_flavour = ASM_LINUX_GAS;
  */
 void ia32_switch_section(FILE *F, section_t sec) {
 	static section_t curr_sec = NO_SECTION;
-  static const char *text[ASM_MAX][SECTION_MAX] = {
+	static const char *text[ASM_MAX][SECTION_MAX] = {
 		{
-			".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text"
+			".section\t.text",
+			".section\t.data",
+			".section\t.rodata",
+			".section\t.text",
+			".section\t.tbss,\"awT\",@nobits",
+			".section\t.ctors,\"aw\",@progbits"
 		},
 		{
-			".section\t.text", ".section\t.data", ".section .rdata,\"dr\"", ".section\t.text"
+			".section\t.text",
+			".section\t.data",
+			".section .rdata,\"dr\"",
+			".section\t.text",
+			".section\t.tbss,\"awT\",@nobits",
+			".section\t.ctors,\"aw\",@progbits"
 		}
 	};
 
@@ -68,7 +82,13 @@ void ia32_switch_section(FILE *F, section_t sec) {
 	case SECTION_DATA:
 	case SECTION_RODATA:
 	case SECTION_COMMON:
+	case SECTION_TLS:
+	case SECTION_CTOR:
 		fprintf(F, "\t%s\n", text[asm_flavour][sec]);
+		break;
+
+	default:
+		break;
 	}
 }
 
@@ -81,6 +101,8 @@ static void ia32_dump_function_object(FILE *F, const char *name)
 	case ASM_MINGW_GAS:
 		fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
 		break;
+	default:
+		break;
 	}
 }
 
@@ -90,6 +112,8 @@ static void ia32_dump_function_size(FILE *F, const char *name)
 	case ASM_LINUX_GAS:
 		fprintf(F, "\t.size\t%s, .-%s\n", name, name);
 		break;
+	default:
+		break;
 	}
 }
 
@@ -104,13 +128,6 @@ static void ia32_dump_function_size(FILE *F, const char *name)
  * |_|                                       |_|
  *************************************************************/
 
-/**
- * returns true if a node has x87 registers
- */
-static int has_x87_register(const ir_node *n) {
-	return is_irn_machine_user(n, 0);
-}
-
 /* We always pass the ir_node which is a pointer. */
 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
 	return lc_arg_type_ptr;
@@ -134,15 +151,29 @@ static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
 
 	assert(reg && "no in register found");
 
-	/* in case of unknown: just return a register */
-	if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
-		reg = &ia32_gp_regs[REG_EAX];
-	else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
-		reg = &ia32_xmm_regs[REG_XMM0];
-	else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
-		reg = &ia32_vfp_regs[REG_VF0];
-	else if (REGS_ARE_EQUAL(reg, &ia32_st_regs[REG_ST_UKNWN]))
-		reg = &ia32_st_regs[REG_ST0];
+	/* in case of a joker register: just return a valid register */
+	if (arch_register_type_is(reg, joker)) {
+		arch_register_req_t       req;
+		const arch_register_req_t *p_req;
+
+		/* ask for the requirements */
+		p_req = arch_get_register_req(arch_env, &req, irn, pos);
+
+		if (arch_register_req_is(p_req, limited)) {
+			/* in case of limited requirements: get the first allowed register */
+
+			bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
+			int      idx;
+
+			p_req->limited(p_req->limited_env, bs);
+			idx = bitset_next_set(bs, 0);
+			reg = arch_register_for_index(p_req->cls, idx);
+		}
+		else {
+			/* otherwise get first register in class */
+			reg = arch_register_for_index(p_req->cls, 0);
+		}
+	}
 
 	return reg;
 }
@@ -222,13 +253,13 @@ static int ia32_get_reg_name(lc_appendable_t *app,
     const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
 {
 	const char *buf;
-	ir_node    *X  = arg->v_ptr;
+	ir_node    *irn = arg->v_ptr;
 	int         nr = occ->width - 1;
 
-	if (!X)
+	if (! irn)
 		return lc_appendable_snadd(app, "(null)", 6);
 
-	buf = get_ia32_reg_name(X, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
+	buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
 
 	/* append the stupid % to register names */
 	lc_appendable_chadd(app, '%');
@@ -242,14 +273,14 @@ static int ia32_get_x87_name(lc_appendable_t *app,
     const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
 {
 	const char *buf;
-	ir_node     *X  = arg->v_ptr;
+	ir_node     *irn = arg->v_ptr;
 	int         nr = occ->width - 1;
 	ia32_attr_t *attr;
 
-	if (!X)
+	if (! irn)
 		return lc_appendable_snadd(app, "(null)", 6);
 
-	attr = get_ia32_attr(X);
+	attr = get_ia32_attr(irn);
 	buf = attr->x87[nr]->name;
 	lc_appendable_chadd(app, '%');
 	return lc_appendable_snadd(app, buf, strlen(buf));
@@ -262,16 +293,16 @@ static int ia32_const_to_str(lc_appendable_t *app,
     const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
 {
 	const char *buf;
-	ir_node    *X = arg->v_ptr;
+	ir_node    *irn = arg->v_ptr;
 
-	if (!X)
+	if (! irn)
 		return lc_arg_append(app, occ, "(null)", 6);
 
 	if (occ->conversion == 'C') {
-		buf = get_ia32_cnst(X);
+		buf = get_ia32_cnst(irn);
 	}
 	else { /* 'O' */
-		buf = get_ia32_am_offs(X);
+		buf = get_ia32_am_offs(irn);
 	}
 
 	return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
@@ -283,14 +314,16 @@ static int ia32_const_to_str(lc_appendable_t *app,
 static int ia32_get_mode_suffix(lc_appendable_t *app,
     const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
 {
-	ir_node *X    = arg->v_ptr;
-	ir_mode *mode = get_irn_mode(X);
+	ir_node *irn  = arg->v_ptr;
+	ir_mode *mode = get_irn_mode(irn);
 
 	if (mode == mode_T) {
-		mode = is_ia32_AddrModeS(X) || is_ia32_AddrModeD(X) ? get_ia32_ls_mode(X) : get_ia32_res_mode(X);
+		mode = get_ia32_res_mode(irn);
+		if (! mode)
+			mode = get_ia32_ls_mode(irn);
 	}
 
-	if (!X)
+	if (! irn)
 		return lc_arg_append(app, occ, "(null)", 6);
 
 	if (mode_is_float(mode)) {
@@ -328,7 +361,7 @@ const lc_arg_env_t *ia32_get_arg_env(void) {
 	return env;
 }
 
-static char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
+static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
 	switch(get_mode_size_bits(mode)) {
 		case 8:
 			return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
@@ -342,7 +375,7 @@ static char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, con
 /**
  * Emits registers and/or address mode of a binary operation.
  */
-char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
 	static char *buf = NULL;
 
 	/* verify that this function is never called on non-AM supporting operations */
@@ -352,7 +385,9 @@ char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
 	(!(is_ia32_St(n)      || \
 	is_ia32_Store8Bit(n)  || \
 	is_ia32_CondJmp(n)    || \
-	is_ia32_fCondJmp(n)   || \
+	is_ia32_xCondJmp(n)   || \
+	is_ia32_CmpSet(n)     || \
+	is_ia32_xCmpSet(n)    || \
 	is_ia32_SwitchJmp(n)))
 
 	if (! buf) {
@@ -364,9 +399,12 @@ char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
 
 	switch(get_ia32_op_type(n)) {
 		case ia32_Normal:
-			if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+			if (is_ia32_ImmConst(n)) {
 				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
 			}
+			else if (is_ia32_ImmSymConst(n)) {
+				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
+			}
 			else {
 				const arch_register_t *in1 = get_in_reg(n, 2);
 				const arch_register_t *in2 = get_in_reg(n, 3);
@@ -396,7 +434,7 @@ char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
 					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
 				}
 				else {
-					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S, %s", n, ia32_emit_am(n, env));
+					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
 				}
 			}
 			break;
@@ -408,9 +446,9 @@ char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
 					get_ia32_cnst(n));                               /* tell the assembler to store it's address.   */
 			}
 			else {
-				const arch_register_t *in1 = get_in_reg(n, 2);
-				ir_mode              *mode = get_ia32_res_mode(n);
-				const char           *in_name;
+				const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
+				ir_mode               *mode = get_ia32_res_mode(n);
+				const char            *in_name;
 
 				mode    = mode ? mode : get_ia32_ls_mode(n);
 				in_name = ia32_get_reg_name_for_mode(env, mode, in1);
@@ -432,10 +470,36 @@ char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
 	return buf;
 }
 
+/**
+ * Returns the xxx PTR string for a given mode
+ *
+ * @param mode      the mode
+ * @param x87_insn  if non-zero returns the string for a x87 instruction
+ *                  else for a SSE instruction
+ */
+static const char *pointer_size(ir_mode *mode, int x87_insn)
+{
+	if (mode) {
+		switch (get_mode_size_bits(mode)) {
+		case 8:  return "BYTE PTR";
+		case 16: return "WORD PTR";
+		case 32: return "DWORD PTR";
+		case 64:
+			if (x87_insn)
+				return "QWORD PTR";
+			return NULL;
+		case 80:
+		case 96: return "XWORD PTR";
+		default: return NULL;
+		}
+	}
+	return NULL;
+}
+
 /**
  * Emits registers and/or address mode of a binary operation.
  */
-char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
 	static char *buf = NULL;
 
 	/* verify that this function is never called on non-AM supporting operations */
@@ -451,7 +515,9 @@ char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
 	switch(get_ia32_op_type(n)) {
 		case ia32_Normal:
 			if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
-				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
+				ir_mode *mode = get_ia32_ls_mode(n);
+				const char *p = pointer_size(mode, 1);
+				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
 			}
 			else {
 				ia32_attr_t *attr = get_ia32_attr(n);
@@ -476,15 +542,13 @@ char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
 			assert(0 && "unsupported op type");
 	}
 
-#undef PRODUCES_RESULT
-
 	return buf;
 }
 
 /**
  * Emits registers and/or address mode of a unary operation.
  */
-char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
 	static char *buf = NULL;
 
 	if (! buf) {
@@ -496,15 +560,34 @@ char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
 
 	switch(get_ia32_op_type(n)) {
 		case ia32_Normal:
-			if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
+			if (is_ia32_ImmConst(n)) {
 				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
 			}
+			else if (is_ia32_ImmSymConst(n)) {
+				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "OFFSET FLAT:%C", n);
+			}
 			else {
-				lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
+				if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
+					/* MulS and Mulh implicitly multiply by EAX */
+					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
+				} else if(is_ia32_Push(n)) {
+					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S", n);
+				} else {
+					lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
+				}
 			}
 			break;
-		case ia32_am_Dest:
-			snprintf(buf, SNPRINTF_BUF_LEN, ia32_emit_am(n, env));
+		case ia32_AddrModeD:
+			assert(!is_ia32_Push(n));
+			snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
+			break;
+		case ia32_AddrModeS:
+			/*
+				Mulh is emitted via emit_unop
+				imul [MEM]  means EDX:EAX <- EAX * [MEM]
+			*/
+			assert((is_ia32_Mulh(n) || is_ia32_MulS(n) || is_ia32_Push(n)) && "Only MulS and Mulh can have AM source as unop");
+			lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
 			break;
 		default:
 			assert(0 && "unsupported op type");
@@ -516,11 +599,11 @@ char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
 /**
  * Emits address mode.
  */
-char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
+const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
 	ia32_am_flavour_t am_flav    = get_ia32_am_flavour(n);
 	int               had_output = 0;
-	char             *s;
-	int               size;
+	char              *s;
+	const char        *p;
 	static struct obstack *obst  = NULL;
 	ir_mode *mode = get_ia32_ls_mode(n);
 
@@ -537,30 +620,9 @@ char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
 	/* obstack_free with NULL results in an uninitialized obstack */
 	obstack_init(obst);
 
-	if (mode) {
-		switch (get_mode_size_bits(mode)) {
-			case 8:
-				obstack_printf(obst, "BYTE PTR ");
-				break;
-			case 16:
-				obstack_printf(obst, "WORD PTR ");
-				break;
-			case 32:
-				obstack_printf(obst, "DWORD PTR ");
-				break;
-			case 64:
-				if (has_x87_register(n))
-					/* ARGHHH: stupid gas x87 wants QWORD PTR but SSE must be WITHOUT */
-					obstack_printf(obst, "QWORD PTR ");
-				break;
-			case 80:
-			case 96:
-				obstack_printf(obst, "XWORD PTR ");
-				break;
-			default:
-				break;
-		}
-	}
+	p = pointer_size(mode, ia32_has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
+	if (p)
+		obstack_printf(obst, "%s ", p);
 
 	/* emit address mode symconst */
 	if (get_ia32_am_sc(n)) {
@@ -593,17 +655,16 @@ char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
 	}
 
 	if (am_flav & ia32_O) {
-		s = get_ia32_am_offs(n);
+		int offs = get_ia32_am_offs_int(n);
 
-		if (s) {
+		if (offs != 0) {
 			/* omit explicit + if there was no base or index */
 			if (! had_output) {
-				obstack_printf(obst, "[");
-				if (s[0] == '+')
-					s++;
+				obstack_printf(obst, "[%d", offs);
+			} else {
+				obstack_printf(obst, "%+d", offs);
 			}
 
-			obstack_printf(obst, s);
 			had_output = 1;
 		}
 	}
@@ -611,14 +672,25 @@ char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
 	if (had_output)
 		obstack_printf(obst, "] ");
 
-	size        = obstack_object_size(obst);
-	s           = obstack_finish(obst);
-	s[size - 1] = '\0';
+	obstack_1grow(obst, '\0');
+	s = obstack_finish(obst);
 
 	return s;
 }
 
+/**
+ * emit an address
+ */
+const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
+{
+	static char buf[SNPRINTF_BUF_LEN];
+	ir_mode    *mode = get_ia32_ls_mode(irn);
+	const char *adr  = get_ia32_cnst(irn);
+	const char *pref = pointer_size(mode, ia32_has_x87_register(irn));
 
+	snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
+	return buf;
+}
 
 /**
  * Formated print of commands and comments.
@@ -680,12 +752,12 @@ static const struct cmp2conditon_t cmp2condition_s[] = {
   { "ne",              pn_Cmp_Lg },     /* != */
   { "ordered",         pn_Cmp_Leg },    /* Floating point: ordered */
   { "unordered",       pn_Cmp_Uo },     /* FLoting point: unordered */
-  { "unordered or ==", pn_Cmp_Ue },     /* Floating point: unordered or == */
-  { "unordered or <",  pn_Cmp_Ul },     /* Floating point: unordered or < */
-  { "unordered or <=", pn_Cmp_Ule },    /* Floating point: unordered or <= */
-  { "unordered or >",  pn_Cmp_Ug },     /* Floating point: unordered or > */
-  { "unordered or >=", pn_Cmp_Uge },    /* Floating point: unordered or >= */
-  { "unordered or !=", pn_Cmp_Ne },     /* Floating point: unordered or != */
+  { "e",               pn_Cmp_Ue },     /* Floating point: unordered or == */
+  { "b",               pn_Cmp_Ul },     /* Floating point: unordered or < */
+  { "be",              pn_Cmp_Ule },    /* Floating point: unordered or <= */
+  { "a",               pn_Cmp_Ug },     /* Floating point: unordered or > */
+  { "ae",              pn_Cmp_Uge },    /* Floating point: unordered or >= */
+  { "ne",              pn_Cmp_Ne },     /* Floating point: unordered or != */
   { NULL,              pn_Cmp_True },   /* always true */
 };
 
@@ -702,12 +774,12 @@ static const struct cmp2conditon_t cmp2condition_u[] = {
 	{ "ne",              pn_Cmp_Lg },     /* != */
 	{ "ordered",         pn_Cmp_Leg },    /* Floating point: ordered */
 	{ "unordered",       pn_Cmp_Uo },     /* FLoting point: unordered */
-	{ "unordered or ==", pn_Cmp_Ue },     /* Floating point: unordered or == */
-	{ "unordered or <",  pn_Cmp_Ul },     /* Floating point: unordered or < */
-	{ "unordered or <=", pn_Cmp_Ule },    /* Floating point: unordered or <= */
-	{ "unordered or >",  pn_Cmp_Ug },     /* Floating point: unordered or > */
-	{ "unordered or >=", pn_Cmp_Uge },    /* Floating point: unordered or >= */
-	{ "unordered or !=", pn_Cmp_Ne },     /* Floating point: unordered or != */
+	{ "e",               pn_Cmp_Ue },     /* Floating point: unordered or == */
+	{ "b",               pn_Cmp_Ul },     /* Floating point: unordered or < */
+	{ "be",              pn_Cmp_Ule },    /* Floating point: unordered or <= */
+	{ "a",               pn_Cmp_Ug },     /* Floating point: unordered or > */
+	{ "ae",              pn_Cmp_Uge },    /* Floating point: unordered or >= */
+	{ "ne",              pn_Cmp_Ne },     /* Floating point: unordered or != */
 	{ NULL,              pn_Cmp_True },   /* always true */
 };
 
@@ -744,70 +816,87 @@ static ir_node *next_blk_sched(const ir_node *block) {
 	return get_irn_link(block);
 }
 
+/**
+ * Returns the Proj with projection number proj and NOT mode_M
+ */
+static ir_node *get_proj(const ir_node *irn, long proj) {
+	const ir_edge_t *edge;
+	ir_node         *src;
+
+	assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
+
+	foreach_out_edge(irn, edge) {
+		src = get_edge_src_irn(edge);
+
+		assert(is_Proj(src) && "Proj expected");
+		if (get_irn_mode(src) == mode_M)
+			continue;
+
+		if (get_Proj_proj(src) == proj)
+			return src;
+	}
+	return NULL;
+}
+
 /**
  * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
  */
 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
-	const ir_node   *proj1, *proj2 = NULL;
-	const ir_node   *block, *next_bl = NULL;
-	const ir_edge_t *edge;
+	const ir_node *proj_true;
+	const ir_node *proj_false;
+	const ir_node *block;
+	const ir_node *next_block;
 	char buf[SNPRINTF_BUF_LEN];
 	char cmd_buf[SNPRINTF_BUF_LEN];
 	char cmnt_buf[SNPRINTF_BUF_LEN];
+	int is_unsigned;
+	int pnc;
+	int flipped = 0;
 
 	/* get both Proj's */
-	edge = get_irn_out_edge_first(irn);
-	proj1 = get_edge_src_irn(edge);
-	assert(is_Proj(proj1) && "CondJmp with a non-Proj");
+	proj_true = get_proj(irn, pn_Cond_true);
+	assert(proj_true && "CondJmp without true Proj");
 
-	edge = get_irn_out_edge_next(irn, edge);
-	if (edge) {
-		proj2 = get_edge_src_irn(edge);
-		assert(is_Proj(proj2) && "CondJmp with a non-Proj");
-	}
+	proj_false = get_proj(irn, pn_Cond_false);
+	assert(proj_false && "CondJmp without false Proj");
+
+	pnc = get_ia32_pncode(irn);
 
 	/* for now, the code works for scheduled and non-schedules blocks */
 	block = get_nodes_block(irn);
-	if (proj2) {
-		/* we have a block schedule */
-		next_bl = next_blk_sched(block);
-
-		if (get_cfop_target_block(proj1) == next_bl) {
-			/* exchange both proj's so the second one can be omitted */
-			const ir_node *t = proj1;
-			proj1 = proj2;
-			proj2 = t;
-		}
+
+	/* we have a block schedule */
+	next_block = next_blk_sched(block);
+
+	if (get_cfop_target_block(proj_true) == next_block) {
+		/* exchange both proj's so the second one can be omitted */
+		const ir_node *t = proj_true;
+		proj_true = proj_false;
+		proj_false = t;
+
+		flipped = 1;
+		pnc = get_negated_pnc(pnc, mode);
 	}
 
 	/* the first Proj must always be created */
-	if (get_Proj_proj(proj1) == pn_Cond_true) {
-		snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
-					get_cmp_suffix(get_ia32_pncode(irn), !mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
-					get_cfop_target(proj1, buf));
-		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == TRUE */");
-	}
-	else  {
-		snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
-					get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode),
-					!mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
-					get_cfop_target(proj1, buf));
-		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == FALSE */");
-	}
+	is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
+	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
+	         get_cmp_suffix(pnc, is_unsigned),
+	         get_cfop_target(proj_true, buf));
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
+	         get_pnc_string(pnc), flipped ? "(was flipped)" : "");
 	IA32_DO_EMIT(irn);
 
 	/* the second Proj might be a fallthrough */
-	if (proj2) {
-		if (get_cfop_target_block(proj2) != next_bl) {
-			snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
-			snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
-		}
-		else {
-			cmd_buf[0] = '\0';
-			snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrogh %s */", get_cfop_target(proj2, buf));
-		}
-		IA32_DO_EMIT(irn);
+	if (get_cfop_target_block(proj_false) != next_block) {
+		snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
+		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
+	}
+	else {
+		cmd_buf[0] = '\0';
+		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
 	}
+	IA32_DO_EMIT(irn);
 }
 
 /**
@@ -885,6 +974,282 @@ static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
 	finish_CondJmp(F, irn, get_ia32_res_mode(irn));
 }
 
+/**
+ * Emits code for conditional SSE floating point jump with two variables.
+ */
+static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
+	FILE *F = env->out;
+	char cmd_buf[SNPRINTF_BUF_LEN];
+	char cmnt_buf[SNPRINTF_BUF_LEN];
+
+	lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
+	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
+	IA32_DO_EMIT(irn);
+	finish_CondJmp(F, irn, mode_F);
+
+}
+
+/**
+ * Emits code for conditional x87 floating point jump with two variables.
+ */
+static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
+	FILE *F = env->out;
+	char cmd_buf[SNPRINTF_BUF_LEN];
+	char cmnt_buf[SNPRINTF_BUF_LEN];
+	ia32_attr_t *attr = get_ia32_attr(irn);
+	const char *reg = attr->x87[1]->name;
+	const char *instr = "fcom";
+	int reverse = 0;
+
+	switch (get_ia32_irn_opcode(irn)) {
+	case iro_ia32_fcomrJmp:
+		reverse = 1;
+	case iro_ia32_fcomJmp:
+	default:
+		instr = "fucom";
+		break;
+	case iro_ia32_fcomrpJmp:
+		reverse = 1;
+	case iro_ia32_fcompJmp:
+		instr = "fucomp";
+		break;
+	case iro_ia32_fcomrppJmp:
+		reverse = 1;
+	case iro_ia32_fcomppJmp:
+		instr = "fucompp";
+		reg = "";
+		break;
+	}
+
+	if (reverse)
+		set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
+
+	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
+	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
+	IA32_DO_EMIT(irn);
+	lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
+	IA32_DO_EMIT(irn);
+	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
+	IA32_DO_EMIT(irn);
+
+	/* the compare flags must be evaluated using carry , ie unsigned */
+	finish_CondJmp(F, irn, mode_Iu);
+}
+
+static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
+	FILE               *F       = env->out;
+	const lc_arg_env_t *arg_env = ia32_get_arg_env();
+	ir_mode    *mode       = get_irn_mode(get_irn_n(irn, 0));
+	int        is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
+	const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
+	int is_PsiCondCMov     = is_ia32_PsiCondCMov(irn);
+	int idx_left  = 2 - is_PsiCondCMov;
+	int idx_right = 3 - is_PsiCondCMov;
+
+	char cmd_buf[SNPRINTF_BUF_LEN];
+	char cmnt_buf[SNPRINTF_BUF_LEN];
+	const arch_register_t *in1, *in2, *out;
+
+	out = arch_get_irn_register(env->arch_env, irn);
+	in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
+	in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
+
+	/* we have to emit the cmp first, because the destination register */
+	/* could be one of the compare registers                           */
+	if (is_ia32_CmpCMov(irn)) {
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
+	}
+	else if (is_ia32_xCmpCMov(irn)) {
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
+	}
+	else if (is_PsiCondCMov) {
+		/* omit compare because flags are already set by And/Or */
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
+	}
+	else {
+		assert(0 && "unsupported CMov");
+	}
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
+	IA32_DO_EMIT(irn);
+
+	if (REGS_ARE_EQUAL(out, in2)) {
+		/* best case: default in == out -> do nothing */
+	}
+	else if (REGS_ARE_EQUAL(out, in1)) {
+		/* true in == out -> need complement compare and exchange true and default in */
+		ir_node *t = get_irn_n(irn, idx_left);
+		set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
+		set_irn_n(irn, idx_right, t);
+
+		cmp_suffix  = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
+
+	}
+	else {
+		/* out is different from in: need copy default -> out */
+		if (is_PsiCondCMov)
+			lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
+		else
+			lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
+
+		lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
+		IA32_DO_EMIT(irn);
+	}
+
+	if (is_PsiCondCMov)
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
+	else
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
+
+	lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
+	IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
+	CMov_emitter(irn, env);
+}
+
+static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
+	CMov_emitter(irn, env);
+}
+
+static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
+	CMov_emitter(irn, env);
+}
+
+static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
+	FILE               *F       = env->out;
+	const lc_arg_env_t *arg_env = ia32_get_arg_env();
+	int        is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
+	const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
+	const char *reg8bit;
+
+	char cmd_buf[SNPRINTF_BUF_LEN];
+	char cmnt_buf[SNPRINTF_BUF_LEN];
+	const arch_register_t *out;
+
+	out     = arch_get_irn_register(env->arch_env, irn);
+	reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
+
+	if (is_ia32_CmpSet(irn)) {
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
+	}
+	else if (is_ia32_xCmpSet(irn)) {
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
+	}
+	else if (is_ia32_PsiCondSet(irn)) {
+		/* omit compare because flags are already set by And/Or */
+		snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
+	}
+	else {
+		assert(0 && "unsupported Set");
+	}
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
+	IA32_DO_EMIT(irn);
+
+	/* use mov to clear target because it doesn't affect the eflags */
+	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
+	IA32_DO_EMIT(irn);
+
+	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
+	IA32_DO_EMIT(irn);
+}
+
+static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
+	Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
+}
+
+static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
+	Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
+}
+
+static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
+	Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
+}
+
+static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
+	FILE               *F       = env->out;
+	const lc_arg_env_t *arg_env = ia32_get_arg_env();
+	int                sse_pnc  = -1;
+	long               pnc      = get_ia32_pncode(irn);
+	long               unord    = pnc & pn_Cmp_Uo;
+	char cmd_buf[SNPRINTF_BUF_LEN];
+	char cmnt_buf[SNPRINTF_BUF_LEN];
+
+	switch (pnc) {
+		case pn_Cmp_Leg: /* odered */
+			sse_pnc = 7;
+			break;
+		case pn_Cmp_Uo:  /* unordered */
+			sse_pnc = 3;
+			break;
+		case pn_Cmp_Ue:
+		case pn_Cmp_Eq:  /* == */
+			sse_pnc = 0;
+			break;
+		case pn_Cmp_Ul:
+		case pn_Cmp_Lt:  /* < */
+			sse_pnc = 1;
+			break;
+		case pn_Cmp_Ule:
+		case pn_Cmp_Le: /* <= */
+			sse_pnc = 2;
+			break;
+		case pn_Cmp_Ug:
+		case pn_Cmp_Gt:  /* > */
+			sse_pnc = 6;
+			break;
+		case pn_Cmp_Uge:
+		case pn_Cmp_Ge: /* >= */
+			sse_pnc = 5;
+			break;
+		case pn_Cmp_Ne:
+		case pn_Cmp_Lg:  /* != */
+			sse_pnc = 4;
+			break;
+	}
+
+	assert(sse_pnc >= 0 && "unsupported compare");
+
+	if (unord && sse_pnc != 3) {
+		/*
+			We need a separate compare against unordered.
+			Quick and Dirty solution:
+			- get some memory on stack
+			- compare
+			- store result
+			- compare
+			- and result and stored result
+		    - cleanup stack
+		*/
+		snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
+		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
+		IA32_DO_EMIT(NULL);
+		snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
+		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
+		IA32_DO_EMIT(NULL);
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
+		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
+		IA32_DO_EMIT(NULL);
+	}
+
+	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
+	lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
+	IA32_DO_EMIT(irn);
+
+	if (unord && sse_pnc != 3) {
+		lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
+		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
+		IA32_DO_EMIT(NULL);
+		snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
+		snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
+		IA32_DO_EMIT(NULL);
+	}
+}
+
 /*********************************************************
  *                 _ _       _
  *                (_) |     (_)
@@ -943,7 +1308,7 @@ static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
 
 	/* fill the table structure */
 	tbl.label        = xmalloc(SNPRINTF_BUF_LEN);
-	tbl.label        = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, "JMPTBL_");
+	tbl.label        = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
 	tbl.defProj      = NULL;
 	tbl.num_branches = get_irn_n_edges(irn);
 	tbl.branches     = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
@@ -1097,25 +1462,27 @@ static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
 /**
  * Emit movsb/w instructions to make mov count divideable by 4
  */
-static void emit_CopyB_prolog(FILE *F, int rem, int size) {
+static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
 	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
 
-	fprintf(F, "\t/* memcopy %d bytes*/\n", size);
+	ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
 
 	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
-	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward*/");
-	IA32_DO_EMIT(NULL);
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
 
 	switch(rem) {
 		case 1:
+			IA32_DO_EMIT(NULL);
 			snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
 			snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
 			break;
 		case 2:
+			IA32_DO_EMIT(NULL);
 			snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
 			snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
 			break;
 		case 3:
+			IA32_DO_EMIT(NULL);
 			snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
 			snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
 			IA32_DO_EMIT(NULL);
@@ -1131,18 +1498,12 @@ static void emit_CopyB_prolog(FILE *F, int rem, int size) {
  * Emit rep movsd instruction for memcopy.
  */
 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
-	FILE    *F         = emit_env->out;
-	tarval  *tv        = get_ia32_Immop_tarval(irn);
-	int      rem       = get_tarval_long(tv);
-	ir_node *size_node = get_irn_n(irn, 2);
-	int      size;
+	FILE   *F  = emit_env->out;
+	tarval *tv = get_ia32_Immop_tarval(irn);
+	int    rem = get_tarval_long(tv);
 	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
 
-	/* beware: size_node could be a be_Copy to fulfill constraints for ecx */
-	size_node = be_is_Copy(size_node) ? be_get_Copy_op(size_node) : size_node;
-	size      = get_tarval_long(get_ia32_Immop_tarval(size_node));
-
-	emit_CopyB_prolog(F, rem, size);
+	emit_CopyB_prolog(F, irn, rem);
 
 	snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
 	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
@@ -1158,7 +1519,7 @@ static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
 	FILE   *F    = emit_env->out;
 	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
 
-	emit_CopyB_prolog(F, size & 0x3, size);
+	emit_CopyB_prolog(F, irn, size & 0x3);
 
 	size >>= 2;
 	while (size--) {
@@ -1232,6 +1593,7 @@ static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
 	char               *conv_cmd = NULL;
 	ir_mode	           *src_mode = get_ia32_src_mode(irn);
 	ir_mode            *tgt_mode = get_ia32_tgt_mode(irn);
+	int                signed_mode;
 	int n, m;
 	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
 	const arch_register_t *in_reg, *out_reg;
@@ -1239,14 +1601,13 @@ static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
 	n = get_mode_size_bits(src_mode);
 	m = get_mode_size_bits(tgt_mode);
 
-	if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
+	assert(n == 8 || n == 16 || n == 32);
+	assert(m == 8 || m == 16 || m == 32);
+	assert(n != m);
+
+	signed_mode = mode_is_signed(n < m ? src_mode : tgt_mode);
+	if(signed_mode) {
 		move_cmd = "movsx";
-		if (n == 8 || m == 8)
-			conv_cmd = "cbw";
-		else if (n == 16 || m == 16)
-			conv_cmd = "cwde";
-		else
-			assert(0 && "unsupported Conv_I2I");
 	}
 
 	switch(get_ia32_op_type(irn)) {
@@ -1256,14 +1617,18 @@ static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
 
 			if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
 				REGS_ARE_EQUAL(out_reg, in_reg)                &&
-				mode_is_signed(n < m ? src_mode : tgt_mode))
+				signed_mode)
 			{
+				if (n == 8 || m == 8)
+					conv_cmd = "cbw";
+				else if (n == 16 || m == 16)
+					conv_cmd = "cwde";
+
 				/* argument and result are both in EAX and */
 				/* signedness is ok: -> use converts       */
 				lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
 			}
-			else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
-				! mode_is_signed(n < m ? src_mode : tgt_mode))
+			else if (REGS_ARE_EQUAL(out_reg, in_reg) &&	! signed_mode)
 			{
 				/* argument and result are in the same register */
 				/* and signedness is ok: -> use and with mask   */
@@ -1321,7 +1686,7 @@ static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
 		snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
 	}
 	else {
-		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "%1D", get_irn_n(irn, be_pos_Call_ptr));
+		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
 	}
 
 	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
@@ -1334,15 +1699,14 @@ static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
  */
 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
 	FILE          *F    = emit_env->out;
-	unsigned       offs = be_get_IncSP_offset(irn);
-	be_stack_dir_t dir  = be_get_IncSP_direction(irn);
+	int offs = be_get_IncSP_offset(irn);
 	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
 
 	if (offs) {
-		if (dir == be_stack_dir_expand)
+		if (offs > 0)
 			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
 		else
-			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, offs);
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
 		lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
 	}
 	else {
@@ -1366,14 +1730,15 @@ static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
 }
 
 /**
- * Emits code for Copy.
+ * Emits code for Copy/CopyKeep.
  */
-static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
-	FILE *F = emit_env->out;
+static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
+	FILE             *F    = emit_env->out;
 	const arch_env_t *aenv = emit_env->arch_env;
 	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
 
-	if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, be_get_Copy_op(irn))))
+	if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
+		arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
 		return;
 
 	if (mode_is_float(get_irn_mode(irn)))
@@ -1384,14 +1749,58 @@ static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
 	IA32_DO_EMIT(irn);
 }
 
+static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
+	Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
+}
+
+static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
+	Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
+}
+
 /**
  * Emits code for exchange.
  */
 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
 	FILE *F = emit_env->out;
 	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
+	const arch_register_t *in1, *in2;
+	const arch_register_class_t *cls1, *cls2;
+
+	in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
+	in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
+
+	cls1 = arch_register_get_class(in1);
+	cls2 = arch_register_get_class(in2);
+
+	assert(cls1 == cls2 && "Register class mismatch at Perm");
+
+	if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
+		if(emit_env->isa->opt_arch == arch_athlon) {
+			// xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
+			// it is nearly always beneficial to use the 3 xor trick instead of an xchg
+			cmnt_buf[0] = 0;
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
+			IA32_DO_EMIT(irn);
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
+			IA32_DO_EMIT(irn);
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
+		} else {
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
+		}
+	}
+	else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
+		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
+			"pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
+	}
+	else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
+		/* is a NOP */
+		cmd_buf[0] = '\0';
+	}
+	else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
+		/* is a NOP */
+		cmd_buf[0] = '\0';
+	}
 
-	lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
 	lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
 	IA32_DO_EMIT(irn);
 }
@@ -1400,32 +1809,117 @@ static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
  * Emits code for Constant loading.
  */
 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
-  FILE *F = env->out;
-  char cmd_buf[256], cmnt_buf[256];
-  const lc_arg_env_t *arg_env = ia32_get_arg_env();
-
-  if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
-		const char *instr = "xor";
-		if (env->isa->opt_arch == arch_pentium_4) {
-			/* P4 prefers sub r, r, others xor r, r */
-			instr = "sub";
-		}
-    lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
-    lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
-  }
-  else {
-    if (get_ia32_op_type(n) == ia32_SymConst) {
-      lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
-      lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
-    }
-		else {
-				lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
-				lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
+	FILE *F = env->out;
+	char cmd_buf[256], cmnt_buf[256];
+	const lc_arg_env_t *arg_env = ia32_get_arg_env();
+	ir_mode *mode = get_irn_mode(n);
+	tarval *tv = get_ia32_Immop_tarval(n);
+
+	if (get_ia32_op_type(n) == ia32_SymConst) {
+		lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
+		lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
+	} else {
+		assert(mode == get_tarval_mode(tv) || (mode_is_reference(get_tarval_mode(tv)) && mode == mode_Iu));
+		/* beware: in some rare cases mode is mode_b which has no tarval_null() */
+		if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
+			const char *instr = "xor";
+			if (env->isa->opt_arch == arch_pentium_4) {
+				/* P4 prefers sub r, r, others xor r, r */
+				instr = "sub";
+			}
+			lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
+			lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
+		} else {
+			lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
+			lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
 		}
-  }
-  lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
+	}
+	lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
 }
 
+/**
+ * Emits code to increase stack pointer.
+ */
+static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
+	FILE *F = emit_env->out;
+	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
+
+	if (is_ia32_ImmConst(irn)) {
+		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
+	}
+	else if (is_ia32_ImmSymConst(irn)) {
+		if (get_ia32_op_type(irn) == ia32_Normal)
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
+		else /* source address mode */
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
+	}
+	else {
+		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
+	}
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
+
+	IA32_DO_EMIT(irn);
+}
+
+/**
+ * Emits code to increase stack pointer.
+ */
+static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
+	FILE *F = emit_env->out;
+	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
+
+	if (is_ia32_ImmConst(irn)) {
+		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
+	}
+	else if (is_ia32_ImmSymConst(irn)) {
+		if (get_ia32_op_type(irn) == ia32_Normal)
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
+		else /* source address mode */
+			lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
+	}
+	else {
+		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
+	}
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
+
+	IA32_DO_EMIT(irn);
+}
+
+/**
+ * Emits code to load the TLS base
+ */
+static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
+	FILE *F = emit_env->out;
+	char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
+
+	switch (asm_flavour) {
+	case ASM_LINUX_GAS:
+		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
+		break;
+	case ASM_MINGW_GAS:
+		lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
+		break;
+	default:
+		assert(0 && "unsupported TLS");
+		break;
+	}
+	snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
+
+	IA32_DO_EMIT(irn);
+}
+
+static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
+	FILE *F = env->out;
+	const lc_arg_env_t *arg_env = ia32_get_arg_env();
+
+	lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
+}
+
+static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
+	FILE *F = env->out;
+
+	ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
+}
 
 
 /***********************************************************************************
@@ -1444,9 +1938,12 @@ static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
  */
 static void ia32_register_emitters(void) {
 
-#define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
-#define EMIT(a)      op_##a->ops.generic = (op_func)emit_##a
-#define BE_EMIT(a)   op_be_##a->ops.generic = (op_func)emit_be_##a
+#define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
+#define IA32_EMIT(a)    IA32_EMIT2(a,a)
+#define EMIT(a)         op_##a->ops.generic = (op_func)emit_##a
+#define IGN(a)			op_##a->ops.generic = (op_func)emit_Nothing
+#define BE_EMIT(a)      op_be_##a->ops.generic = (op_func)emit_be_##a
+#define BE_IGN(a)		op_be_##a->ops.generic = (op_func)emit_Nothing
 
 	/* first clear the generic function pointer for all ops */
 	clear_irp_opcodes_generic_func();
@@ -1459,6 +1956,10 @@ static void ia32_register_emitters(void) {
 	IA32_EMIT(TestJmp);
 	IA32_EMIT(CJmp);
 	IA32_EMIT(CJmpAM);
+	IA32_EMIT(CmpCMov);
+	IA32_EMIT(PsiCondCMov);
+	IA32_EMIT(CmpSet);
+	IA32_EMIT(PsiCondSet);
 	IA32_EMIT(SwitchJmp);
 	IA32_EMIT(CopyB);
 	IA32_EMIT(CopyB_i);
@@ -1468,21 +1969,74 @@ static void ia32_register_emitters(void) {
 	IA32_EMIT(Conv_I2I);
 	IA32_EMIT(Conv_I2I8Bit);
 	IA32_EMIT(Const);
+	IA32_EMIT(AddSP);
+	IA32_EMIT(SubSP);
+	IA32_EMIT(LdTls);
+	IA32_EMIT(xCmp);
+	IA32_EMIT(xCmpSet);
+	IA32_EMIT(xCmpCMov);
+	IA32_EMIT(xCondJmp);
+	IA32_EMIT2(fcomJmp, x87CondJmp);
+	IA32_EMIT2(fcompJmp, x87CondJmp);
+	IA32_EMIT2(fcomppJmp, x87CondJmp);
+	IA32_EMIT2(fcomrJmp, x87CondJmp);
+	IA32_EMIT2(fcomrpJmp, x87CondJmp);
+	IA32_EMIT2(fcomrppJmp, x87CondJmp);
 
 	/* benode emitter */
 	BE_EMIT(Call);
 	BE_EMIT(IncSP);
 	BE_EMIT(SetSP);
 	BE_EMIT(Copy);
+	BE_EMIT(CopyKeep);
 	BE_EMIT(Perm);
+	BE_EMIT(Return);
+
+	BE_IGN(RegParams);
+	BE_IGN(Barrier);
+	BE_IGN(Keep);
 
 	/* firm emitter */
 	EMIT(Jmp);
 	EMIT(Proj);
+	IGN(Phi);
+	IGN(Start);
 
-#undef IA32_EMIT
 #undef BE_EMIT
 #undef EMIT
+#undef IGN
+#undef IA32_EMIT2
+#undef IA32_EMIT
+}
+
+static const char *last_name = NULL;
+static unsigned last_line = -1;
+static unsigned num = -1;
+
+/**
+ * Emit the debug support for node irn.
+ */
+static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
+	dbg_info *db = get_irn_dbg_info(irn);
+	unsigned lineno;
+	const char *fname = be_retrieve_dbg_info(db, &lineno);
+
+	if (fname) {
+		if (last_name != fname) {
+			last_line = -1;
+			be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
+			last_name = fname;
+		}
+		if (last_line != lineno) {
+			char name[64];
+			FILE *F = env->out;
+
+			snprintf(name, sizeof(name), ".LM%u", ++num);
+			last_line = lineno;
+			be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
+			fprintf(F, "%s:\n", name);
+		}
+	}
 }
 
 /**
@@ -1490,7 +2044,6 @@ static void ia32_register_emitters(void) {
  */
 static void ia32_emit_node(const ir_node *irn, void *env) {
 	ia32_emit_env_t   *emit_env = env;
-	FILE              *F        = emit_env->out;
 	ir_op             *op       = get_irn_op(irn);
 	DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
 
@@ -1498,24 +2051,207 @@ static void ia32_emit_node(const ir_node *irn, void *env) {
 
 	if (op->ops.generic) {
 		void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
+		ia32_emit_dbg(irn, emit_env);
 		(*emit)(irn, env);
 	}
 	else {
-		ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", irn, irn);
+		emit_Nothing(irn, env);
+		ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
 	}
 }
 
+/**
+ * Emits gas alignment directives
+ */
+static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
+	fprintf(F, "\t.p2align %u,,%u\n", align, skip);
+}
+
+/**
+ * Emits gas alignment directives for Functions depended on cpu architecture.
+ */
+static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
+	unsigned align;
+	unsigned maximum_skip;
+
+	switch (cpu) {
+		case arch_i386:
+			align = 2;
+			break;
+		case arch_i486:
+			align = 4;
+			break;
+		case arch_k6:
+			align = 5;
+			break;
+		default:
+			align = 4;
+	}
+	maximum_skip = (1 << align) - 1;
+	ia32_emit_alignment(F, align, maximum_skip);
+}
+
+/**
+ * Emits gas alignment directives for Labels depended on cpu architecture.
+ */
+static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
+	unsigned align; unsigned maximum_skip;
+
+	switch (cpu) {
+		case arch_i386:
+			align = 2;
+			break;
+		case arch_i486:
+			align = 4;
+			break;
+		case arch_k6:
+			align = 5;
+			break;
+		default:
+			align = 4;
+	}
+	maximum_skip = (1 << align) - 1;
+	ia32_emit_alignment(F, align, maximum_skip);
+}
+
+static int is_first_loop_block(ir_node *block, ir_node *prev_block, ia32_emit_env_t *env) {
+	ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
+	double block_freq, prev_freq;
+	static const double DELTA = .0001;
+	cpu_support cpu = env->isa->opt_arch;
+
+	if(execfreqs == NULL)
+		return 0;
+	if(cpu == arch_i386 || cpu == arch_i486)
+		return 0;
+
+	block_freq = get_block_execfreq(execfreqs, block);
+	prev_freq = get_block_execfreq(execfreqs, prev_block);
+
+	if(block_freq < DELTA || prev_freq < DELTA)
+		return 0;
+
+	block_freq /= prev_freq;
+
+	switch (cpu) {
+		case arch_athlon:
+		case arch_athlon_64:
+		case arch_k6:
+			return block_freq > 3;
+		default:
+			break;
+	}
+
+	return block_freq > 2;
+}
+
 /**
  * Walks over the nodes in a block connected by scheduling edges
  * and emits code for each node.
  */
-static void ia32_gen_block(ir_node *block, void *env) {
+static void ia32_gen_block(ir_node *block, ir_node *last_block, ia32_emit_env_t *env) {
+	ir_graph      *irg         = get_irn_irg(block);
+	ir_node       *start_block = get_irg_start_block(irg);
+	int           need_label   = 1;
+	FILE          *F           = env->out;
 	const ir_node *irn;
+	int           i;
 
-	if (! is_Block(block))
-		return;
+	assert(is_Block(block));
+
+	if (block == start_block)
+		need_label = 0;
+
+	if (need_label && get_irn_arity(block) == 1) {
+		ir_node *pred_block = get_Block_cfgpred_block(block, 0);
+
+		if (pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
+			need_label = 0;
+	}
+
+	/* special case: if one of our cfg preds is a switch-jmp we need a label, */
+	/*               otherwise there might be jump table entries jumping to   */
+	/*               non-existent (omitted) labels                            */
+	for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
+		ir_node *pred = get_Block_cfgpred(block, i);
+
+		if (is_Proj(pred)) {
+			assert(get_irn_mode(pred) == mode_X);
+			if (is_ia32_SwitchJmp(get_Proj_pred(pred))) {
+				need_label = 1;
+				break;
+			}
+		}
+	}
+
+	/* special case because the start block contains no jump instruction */
+	if (last_block == start_block) {
+		const ir_edge_t *edge;
+		ir_node *startsucc = NULL;
 
-	fprintf(((ia32_emit_env_t *)env)->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
+		foreach_block_succ(start_block, edge) {
+			startsucc = get_edge_src_irn(edge);
+			if (startsucc != start_block)
+				break;
+		}
+		assert(startsucc != NULL);
+
+		/* if the last block was the start block and we are not inside the */
+		/* start successor, emit a jump to the start successor             */
+		if (startsucc != block) {
+			char buf[SNPRINTF_BUF_LEN];
+			ir_snprintf(buf, sizeof(buf), BLOCK_PREFIX("%d"),
+			            get_irn_node_nr(startsucc));
+			ir_fprintf(F, "\tjmp %s\n", buf);
+		}
+	}
+
+	if (need_label) {
+		char cmd_buf[SNPRINTF_BUF_LEN];
+		int i, arity;
+		int align = 1;
+		ir_exec_freq *execfreqs = env->cg->birg->execfreqs;
+
+		/* align the loop headers */
+		if (! is_first_loop_block(block, last_block, env)) {
+			/* align blocks where the previous block has no fallthrough */
+			arity = get_irn_arity(block);
+
+			for (i = 0; i < arity; ++i) {
+				ir_node *predblock = get_Block_cfgpred_block(block, i);
+
+				if (predblock == last_block) {
+					align = 0;
+					break;
+				}
+			}
+		}
+
+		if (align)
+			ia32_emit_align_label(env->out, env->isa->opt_arch);
+
+		ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
+		            get_irn_node_nr(block));
+		fprintf(F, "%-43s ", cmd_buf);
+
+		/* emit list of pred blocks in comment */
+		fprintf(F, "/* preds:");
+
+		arity = get_irn_arity(block);
+		for (i = 0; i < arity; ++i) {
+			ir_node *predblock = get_Block_cfgpred_block(block, i);
+			fprintf(F, " %ld", get_irn_node_nr(predblock));
+		}
+
+		if (execfreqs != NULL) {
+			fprintf(F, " freq: %f", get_block_execfreq(execfreqs, block));
+		}
+
+		fprintf(F, " */\n");
+	}
+
+	/* emit the contents of the block */
+	ia32_emit_dbg(block, env);
 	sched_foreach(block, irn) {
 		ia32_emit_node(irn, env);
 	}
@@ -1524,12 +2260,16 @@ static void ia32_gen_block(ir_node *block, void *env) {
 /**
  * Emits code for function start.
  */
-static void ia32_emit_func_prolog(FILE *F, ir_graph *irg) {
+static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
 	entity     *irg_ent  = get_irg_entity(irg);
 	const char *irg_name = get_entity_ld_name(irg_ent);
+	cpu_support cpu      = emit_env->isa->opt_arch;
+	const be_irg_t *birg = emit_env->cg->birg;
 
 	fprintf(F, "\n");
 	ia32_switch_section(F, SECTION_TEXT);
+	be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
+	ia32_emit_align_func(F, cpu);
 	if (get_entity_visibility(irg_ent) == visibility_external_visible) {
 		fprintf(F, ".globl %s\n", irg_name);
 	}
@@ -1540,11 +2280,12 @@ static void ia32_emit_func_prolog(FILE *F, ir_graph *irg) {
 /**
  * Emits code for function end
  */
-static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
+static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
 	const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
+	const be_irg_t *birg = emit_env->cg->birg;
 
-	fprintf(F, "\tret\n");
 	ia32_dump_function_size(F, irg_name);
+	be_dbg_method_end(birg->main_env->db_handle);
 	fprintf(F, "\n");
 }
 
@@ -1569,6 +2310,7 @@ static void ia32_gen_labels(ir_node *block, void *env) {
 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
 	ia32_emit_env_t emit_env;
 	ir_node *block;
+	ir_node *last_block = NULL;
 
 	emit_env.out      = F;
 	emit_env.arch_env = cg->arch_env;
@@ -1581,7 +2323,7 @@ void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
 
 	ia32_register_emitters();
 
-	ia32_emit_func_prolog(F, irg);
+	ia32_emit_func_prolog(F, irg, &emit_env);
 	irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
 
 	if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
@@ -1596,15 +2338,18 @@ void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
 
 			/* set here the link. the emitter expects to find the next block here */
 			set_irn_link(block, next_bl);
-			ia32_gen_block(block, &emit_env);
+			ia32_gen_block(block, last_block, &emit_env);
+			last_block = block;
 		}
 	}
 	else {
 		/* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
 		   in the block schedule. As this number should NEVER be equal the next block,
 		   we does not need a clear block link here. */
-		irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
+
+		//irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
+		// TODO
 	}
 
-	ia32_emit_func_epilog(F, irg);
+	ia32_emit_func_epilog(F, irg, &emit_env);
 }