X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_common_transform.c;h=d81b1cf5f16af2122bba6fba425cb130b4737868;hb=ef668aa395ab2cb4b3fb4066a8fa4c65c05aabf6;hp=24d4226104a708fa3a4de12783f32c666864975b;hpb=6d660d16232bfc516269d34a21fed1a08fb6e898;p=libfirm diff --git a/ir/be/ia32/ia32_common_transform.c b/ir/be/ia32/ia32_common_transform.c index 24d422610..d81b1cf5f 100644 --- a/ir/be/ia32/ia32_common_transform.c +++ b/ir/be/ia32/ia32_common_transform.c @@ -30,9 +30,11 @@ #include "ircons.h" #include "irprintf.h" #include "typerep.h" +#include "bitset.h" #include "../betranshlp.h" -#include "../beirg_t.h" +#include "../beirg.h" +#include "../beabi.h" #include "ia32_architecture.h" #include "ia32_common_transform.h" @@ -72,13 +74,8 @@ static int check_immediate_constraint(long val, char immediate_constraint_type) } } -/** - * creates a unique ident by adding a number to a tag - * - * @param tag the tag string, must contain a %d if a number - * should be added - */ -static ident *unique_id(const char *tag) +/* creates a unique ident by adding a number to a tag */ +ident *ia32_unique_id(const char *tag) { static unsigned id = 0; char str[256]; @@ -88,7 +85,7 @@ static ident *unique_id(const char *tag) } /** - * Get a primitive type for a mode. + * Get a primitive type for a mode with alignment 16. */ static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode) { @@ -99,7 +96,9 @@ static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode) char buf[64]; snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode)); res = new_type_primitive(new_id_from_str(buf), mode); - set_type_alignment_bytes(res, 16); + if (get_mode_size_bits(mode) >= 80) { + set_type_alignment_bytes(res, 16); + } pmap_insert(types, mode, res); } else @@ -143,7 +142,7 @@ ir_entity *create_float_const_entity(ir_node *cnst) } else tp = ia32_get_prim_type(isa->types, mode); - res = new_entity(get_glob_type(), unique_id(".LC%u"), tp); + res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp); set_entity_ld_ident(res, get_entity_ident(res)); set_entity_visibility(res, visibility_local); @@ -165,12 +164,12 @@ ir_entity *create_float_const_entity(ir_node *cnst) return res; } -ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val) +ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val) { ir_graph *irg = current_ir_graph; ir_node *start_block = get_irg_start_block(irg); ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst, - symconst_sign, val); + symconst_sign, no_pic_adjust, val); arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]); return immediate; @@ -189,13 +188,13 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber) cls = & ia32_reg_classes[c]; for(r = 0; r < cls->n_regs; ++r) { const arch_register_t *temp_reg = arch_register_for_index(cls, r); - if(strcmp(temp_reg->name, clobber) == 0 + if (strcmp(temp_reg->name, clobber) == 0 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) { reg = temp_reg; break; } } - if(reg != NULL) + if (reg != NULL) break; } @@ -203,9 +202,9 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber) } int ia32_mode_needs_gp_reg(ir_mode *mode) { - if(mode == mode_fpcw) + if (mode == mode_fpcw) return 0; - if(get_mode_size_bits(mode) > 32) + if (get_mode_size_bits(mode) > 32) return 0; return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b; } @@ -224,7 +223,7 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, memset(constraint, 0, sizeof(constraint[0])); constraint->same_as = -1; - if(*c == 0) { + if (*c == 0) { /* a memory constraint: no need to do anything in backend about it * (the dependencies are already respected by the memory edge of * the node) */ @@ -244,6 +243,8 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, case '=': break; case '+': break; + case '&': break; + case '*': ++c; break; @@ -381,7 +382,7 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, panic("can only specify same constraint on input"); sscanf(c, "%d%n", &same_as, &p); - if(same_as >= 0) { + if (same_as >= 0) { c += p; continue; } @@ -417,7 +418,7 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, ++c; } - if(same_as >= 0) { + if (same_as >= 0) { if (cls != NULL) panic("same as and register constraint not supported"); if (immediate_type != '\0') @@ -437,6 +438,18 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, constraint->immediate_type = immediate_type; } +static bool can_match(const arch_register_req_t *in, + const arch_register_req_t *out) +{ + if (in->cls != out->cls) + return false; + if ( (in->type & arch_register_req_type_limited) == 0 + || (out->type & arch_register_req_type_limited) == 0 ) + return true; + + return (*in->limited & *out->limited) != 0; +} + ir_node *gen_ASM(ir_node *node) { ir_node *block = NULL; @@ -459,6 +472,8 @@ ir_node *gen_ASM(ir_node *node) ident **clobbers; int clobbers_flags = 0; unsigned clobber_bits[N_CLASSES]; + int out_size; + backend_info_t *info; memset(&clobber_bits, 0, sizeof(clobber_bits)); @@ -521,7 +536,7 @@ ir_node *gen_ASM(ir_node *node) } for (i = 0; i < arity; ++i) { const ir_asm_constraint *constraint = &in_constraints[i]; - if(constraint->pos > reg_map_size) + if (constraint->pos > reg_map_size) reg_map_size = constraint->pos; } ++reg_map_size; @@ -531,7 +546,8 @@ ir_node *gen_ASM(ir_node *node) memset(register_map, 0, reg_map_size * sizeof(register_map[0])); /* construct output constraints */ - out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0])); + out_size = out_arity + 1; + out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0])); for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) { const ir_asm_constraint *constraint = &out_constraints[out_idx]; @@ -610,7 +626,7 @@ ir_node *gen_ASM(ir_node *node) if (parsed_constraint.cls == NULL && parsed_constraint.same_as < 0) { is_memory_op = 1; - } else if(parsed_constraint.memory_possible) { + } else if (parsed_constraint.memory_possible) { /* TODO: match Load or Load/Store if memory possible is set */ } } @@ -636,13 +652,139 @@ ir_node *gen_ASM(ir_node *node) ++out_idx; } + /* Attempt to make ASM node register pressure faithful. + * (This does not work for complicated cases yet!) + * + * Algorithm: Check if there are fewer inputs or outputs (I will call this + * the smaller list). Then try to match each constraint of the smaller list + * to 1 of the other list. If we can't match it, then we have to add a dummy + * input/output to the other list + * + * FIXME: This is still broken in lots of cases. But at least better than + * before... + * FIXME: need to do this per register class... + */ + if (out_arity <= arity) { + int orig_arity = arity; + int in_size = arity; + int o; + bitset_t *used_ins = bitset_alloca(arity); + for (o = 0; o < out_arity; ++o) { + int i; + const arch_register_req_t *outreq = out_reg_reqs[o]; + + if (outreq->cls == NULL) { + continue; + } + + for (i = 0; i < orig_arity; ++i) { + const arch_register_req_t *inreq; + if (bitset_is_set(used_ins, i)) + continue; + inreq = in_reg_reqs[i]; + if (!can_match(outreq, inreq)) + continue; + bitset_set(used_ins, i); + break; + } + /* did we find any match? */ + if (i < orig_arity) + continue; + + /* we might need more space in the input arrays */ + if (arity >= in_size) { + const arch_register_req_t **new_in_reg_reqs; + ir_node **new_in; + + in_size *= 2; + new_in_reg_reqs + = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0])); + memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0])); + new_in = ALLOCANZ(ir_node*, in_size); + memcpy(new_in, in, arity*sizeof(new_in[0])); + + in_reg_reqs = new_in_reg_reqs; + in = new_in; + } + + /* add a new (dummy) input which occupies the register */ + assert(outreq->type & arch_register_req_type_limited); + in_reg_reqs[arity] = outreq; + in[arity] = new_bd_ia32_ProduceVal(NULL, block); + be_dep_on_frame(in[arity]); + ++arity; + } + } else { + int i; + bitset_t *used_outs = bitset_alloca(out_arity); + int orig_out_arity = out_arity; + for (i = 0; i < arity; ++i) { + int o; + const arch_register_req_t *inreq = in_reg_reqs[i]; + + if (inreq->cls == NULL) { + continue; + } + + for (o = 0; o < orig_out_arity; ++o) { + const arch_register_req_t *outreq; + if (bitset_is_set(used_outs, o)) + continue; + outreq = out_reg_reqs[o]; + if (!can_match(outreq, inreq)) + continue; + bitset_set(used_outs, i); + break; + } + /* did we find any match? */ + if (o < orig_out_arity) + continue; + + /* we might need more space in the output arrays */ + if (out_arity >= out_size) { + const arch_register_req_t **new_out_reg_reqs; + + out_size *= 2; + new_out_reg_reqs + = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0])); + memcpy(new_out_reg_reqs, out_reg_reqs, + out_arity * sizeof(new_out_reg_reqs[0])); + out_reg_reqs = new_out_reg_reqs; + } + + /* add a new (dummy) output which occupies the register */ + assert(inreq->type & arch_register_req_type_limited); + out_reg_reqs[out_arity] = inreq; + ++out_arity; + } + } + + /* append none register requirement for the memory output */ + if (out_arity + 1 >= out_size) { + const arch_register_req_t **new_out_reg_reqs; + + out_size = out_arity + 1; + new_out_reg_reqs + = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0])); + memcpy(new_out_reg_reqs, out_reg_reqs, + out_arity * sizeof(new_out_reg_reqs[0])); + out_reg_reqs = new_out_reg_reqs; + } + + /* add a new (dummy) output which occupies the register */ + out_reg_reqs[out_arity] = arch_no_register_req; + ++out_arity; + new_node = new_bd_ia32_Asm(dbgi, new_block, arity, in, out_arity, get_ASM_text(node), register_map); if (arity == 0) be_dep_on_frame(new_node); - set_ia32_out_req_all(new_node, out_reg_reqs); + info = be_get_info(new_node); + for (i = 0; i < out_arity; ++i) { + info->out_infos[i].req = out_reg_reqs[i]; + } set_ia32_in_req_all(new_node, in_reg_reqs); SET_IA32_ORIG_NODE(new_node, node); @@ -693,12 +835,12 @@ ir_node *gen_CopyB(ir_node *node) { rem = size & 0x3; /* size % 4 */ size >>= 2; - res = new_bd_ia32_Const(dbgi, block, NULL, 0, size); + res = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, size); be_dep_on_frame(res); res = new_bd_ia32_CopyB(dbgi, block, new_dst, new_src, res, new_mem, rem); } else { - if(size == 0) { + if (size == 0) { ir_fprintf(stderr, "Optimization warning copyb %+F with size <4\n", node); } @@ -820,7 +962,7 @@ const arch_register_req_t *parse_clobber(const char *clobber) arch_register_req_t *req; unsigned *limited; - if(reg == NULL) { + if (reg == NULL) { panic("Register '%s' mentioned in asm clobber is unknown", clobber); } @@ -891,46 +1033,46 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) ir_node *new_node; mode = get_irn_mode(node); - if(!mode_is_int(mode) && !mode_is_reference(mode)) { + if (!mode_is_int(mode) && !mode_is_reference(mode)) { return NULL; } - if(is_Minus(node)) { + if (is_Minus(node)) { minus = 1; node = get_Minus_op(node); } - if(is_Const(node)) { + if (is_Const(node)) { cnst = node; symconst = NULL; offset_sign = minus; - } else if(is_SymConst(node)) { + } else if (is_SymConst(node)) { cnst = NULL; symconst = node; symconst_sign = minus; - } else if(is_Add(node)) { + } else if (is_Add(node)) { ir_node *left = get_Add_left(node); ir_node *right = get_Add_right(node); - if(is_Const(left) && is_SymConst(right)) { + if (is_Const(left) && is_SymConst(right)) { cnst = left; symconst = right; symconst_sign = minus; offset_sign = minus; - } else if(is_SymConst(left) && is_Const(right)) { + } else if (is_SymConst(left) && is_Const(right)) { cnst = right; symconst = left; symconst_sign = minus; offset_sign = minus; } - } else if(is_Sub(node)) { + } else if (is_Sub(node)) { ir_node *left = get_Sub_left(node); ir_node *right = get_Sub_right(node); - if(is_Const(left) && is_SymConst(right)) { + if (is_Const(left) && is_SymConst(right)) { cnst = left; symconst = right; symconst_sign = !minus; offset_sign = minus; - } else if(is_SymConst(left) && is_Const(right)) { + } else if (is_SymConst(left) && is_Const(right)) { cnst = right; symconst = left; symconst_sign = minus; @@ -940,9 +1082,9 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) return NULL; } - if(cnst != NULL) { + if (cnst != NULL) { offset = get_Const_tarval(cnst); - if(tarval_is_long(offset)) { + if (tarval_is_long(offset)) { val = get_tarval_long(offset); } else { ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a " @@ -950,31 +1092,31 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) return NULL; } - if(!check_immediate_constraint(val, immediate_constraint_type)) + if (!check_immediate_constraint(val, immediate_constraint_type)) return NULL; } - if(symconst != NULL) { - if(immediate_constraint_type != 0) { + if (symconst != NULL) { + if (immediate_constraint_type != 0) { /* we need full 32bits for symconsts */ return NULL; } /* unfortunately the assembler/linker doesn't support -symconst */ - if(symconst_sign) + if (symconst_sign) return NULL; - if(get_SymConst_kind(symconst) != symconst_addr_ent) + if (get_SymConst_kind(symconst) != symconst_addr_ent) return NULL; symconst_ent = get_SymConst_entity(symconst); } - if(cnst == NULL && symconst == NULL) + if (cnst == NULL && symconst == NULL) return NULL; - if(offset_sign && offset != NULL) { + if (offset_sign && offset != NULL) { offset = tarval_neg(offset); } - new_node = create_Immediate(symconst_ent, symconst_sign, val); + new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val); return new_node; }