X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_common_transform.c;h=5b2276826f5a52f236f25329558838b5d69f6e8e;hb=ce6161a7e42a48f7422b7babcc64d8ace18e2687;hp=7beb0d67dfe81b6caf9992bfc6acf97c71d03e3a;hpb=0860cafaff791b93c568c77739bd7d9c7240ee2f;p=libfirm diff --git a/ir/be/ia32/ia32_common_transform.c b/ir/be/ia32/ia32_common_transform.c index 7beb0d67d..5b2276826 100644 --- a/ir/be/ia32/ia32_common_transform.c +++ b/ir/be/ia32/ia32_common_transform.c @@ -31,6 +31,7 @@ #include "irprintf.h" #include "typerep.h" #include "bitset.h" +#include "heights.h" #include "../betranshlp.h" #include "../beirg.h" @@ -43,18 +44,7 @@ #include "gen_ia32_new_nodes.h" #include "gen_ia32_regalloc_if.h" -/** hold the current code generator during transformation */ -ia32_code_gen_t *env_cg = NULL; - -heights_t *heights = NULL; - -static const arch_register_req_t no_register_req = { - arch_register_req_type_none, - NULL, /* regclass */ - NULL, /* limit bitset */ - 0, /* same pos */ - 0 /* different pos */ -}; +ir_heights_t *heights = NULL; static int check_immediate_constraint(long val, char immediate_constraint_type) { @@ -74,93 +64,64 @@ static int check_immediate_constraint(long val, char immediate_constraint_type) } } -/* creates a unique ident by adding a number to a tag */ -ident *ia32_unique_id(const char *tag) -{ - static unsigned id = 0; - char str[256]; - - snprintf(str, sizeof(str), tag, ++id); - return new_id_from_str(str); -} - /** * Get a primitive type for a mode with alignment 16. */ static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode) { - pmap_entry *e = pmap_find(types, mode); - ir_type *res; - - if (! e) { - char buf[64]; - snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode)); - res = new_type_primitive(new_id_from_str(buf), mode); - if (get_mode_size_bits(mode) >= 80) { - set_type_alignment_bytes(res, 16); - } - pmap_insert(types, mode, res); + ir_type *res = (ir_type*)pmap_get(types, mode); + if (res != NULL) + return res; + + res = new_type_primitive(mode); + if (get_mode_size_bits(mode) >= 80) { + set_type_alignment_bytes(res, 16); } - else - res = e->value; + pmap_insert(types, mode, res); return res; } ir_entity *create_float_const_entity(ir_node *cnst) { - ia32_isa_t *isa = env_cg->isa; - tarval *key = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(isa->tv_ent, key); - ir_entity *res; - ir_graph *rem; - - if (e == NULL) { - tarval *tv = key; - ir_mode *mode = get_tarval_mode(tv); - ir_type *tp; - - if (! ia32_cg_config.use_sse2) { - /* try to reduce the mode to produce smaller sized entities */ - if (mode != mode_F) { - if (tarval_ieee754_can_conv_lossless(tv, mode_F)) { - mode = mode_F; + ir_graph *irg = get_irn_irg(cnst); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_isa_t *isa = (ia32_isa_t*) arch_env; + ir_tarval *tv = get_Const_tarval(cnst); + ir_entity *res = (ir_entity*)pmap_get(isa->tv_ent, tv); + ir_initializer_t *initializer; + ir_mode *mode; + ir_type *tp; + + if (res != NULL) + return res; + + mode = get_tarval_mode(tv); + + if (! ia32_cg_config.use_sse2) { + /* try to reduce the mode to produce smaller sized entities */ + if (mode != mode_F) { + if (tarval_ieee754_can_conv_lossless(tv, mode_F)) { + mode = mode_F; + tv = tarval_convert_to(tv, mode); + } else if (mode != mode_D) { + if (tarval_ieee754_can_conv_lossless(tv, mode_D)) { + mode = mode_D; tv = tarval_convert_to(tv, mode); - } else if (mode != mode_D) { - if (tarval_ieee754_can_conv_lossless(tv, mode_D)) { - mode = mode_D; - tv = tarval_convert_to(tv, mode); - } } } } - - if (mode == get_irn_mode(cnst)) { - /* mode was not changed */ - tp = get_Const_type(cnst); - if (tp == firm_unknown_type) - tp = ia32_get_prim_type(isa->types, mode); - } else - tp = ia32_get_prim_type(isa->types, mode); - - res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp); - - set_entity_ld_ident(res, get_entity_ident(res)); - set_entity_visibility(res, visibility_local); - set_entity_variability(res, variability_constant); - set_entity_allocation(res, allocation_static); - - /* we create a new entity here: It's initialization must resist on the - const code irg */ - rem = current_ir_graph; - current_ir_graph = get_const_code_irg(); - set_atomic_ent_value(res, new_Const_type(tv, tp)); - current_ir_graph = rem; - - pmap_insert(isa->tv_ent, key, res); - } else { - res = e->value; } + tp = ia32_get_prim_type(isa->types, mode); + res = new_entity(get_glob_type(), id_unique("C%u"), tp); + set_entity_ld_ident(res, get_entity_ident(res)); + set_entity_visibility(res, ir_visibility_private); + add_entity_linkage(res, IR_LINKAGE_CONSTANT); + + initializer = create_initializer_tarval(tv); + set_entity_initializer(res, initializer); + + pmap_insert(isa->tv_ent, tv, res); return res; } @@ -170,7 +131,7 @@ ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val) ir_node *start_block = get_irg_start_block(irg); ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst, symconst_sign, no_pic_adjust, val); - arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]); + arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]); return immediate; } @@ -184,9 +145,9 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber) /* TODO: construct a hashmap instead of doing linear search for clobber * register */ - for(c = 0; c < N_CLASSES; ++c) { + for (c = 0; c < N_IA32_CLASSES; ++c) { cls = & ia32_reg_classes[c]; - for(r = 0; r < cls->n_regs; ++r) { + for (r = 0; r < cls->n_regs; ++r) { const arch_register_t *temp_reg = arch_register_for_index(cls, r); if (strcmp(temp_reg->name, clobber) == 0 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) { @@ -201,7 +162,8 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber) return reg; } -int ia32_mode_needs_gp_reg(ir_mode *mode) { +int ia32_mode_needs_gp_reg(ir_mode *mode) +{ if (mode == mode_fpcw) return 0; if (get_mode_size_bits(mode) > 32) @@ -232,8 +194,8 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, /* TODO: improve error messages with node and source info. (As users can * easily hit these) */ - while(*c != 0) { - switch(*c) { + while (*c != 0) { + switch (*c) { case ' ': case '\t': case '\n': @@ -249,39 +211,39 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, ++c; break; case '#': - while(*c != 0 && *c != ',') + while (*c != 0 && *c != ',') ++c; break; case 'a': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX; + limited |= 1 << REG_GP_EAX; break; case 'b': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EBX; + limited |= 1 << REG_GP_EBX; break; case 'c': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_ECX; + limited |= 1 << REG_GP_ECX; break; case 'd': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EDX; + limited |= 1 << REG_GP_EDX; break; case 'D': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EDI; + limited |= 1 << REG_GP_EDI; break; case 'S': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_ESI; + limited |= 1 << REG_GP_ESI; break; case 'Q': case 'q': @@ -289,20 +251,20 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, * difference to Q for us (we only assign whole registers) */ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | - 1 << REG_EDX; + limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX | + 1 << REG_GP_EDX; break; case 'A': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EDX; + limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX; break; case 'l': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | - 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI | - 1 << REG_EBP; + limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX | + 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI | + 1 << REG_GP_EBP; break; case 'R': @@ -450,12 +412,26 @@ static bool can_match(const arch_register_req_t *in, return (*in->limited & *out->limited) != 0; } +static inline ir_node *get_new_node(ir_node *node) +{ +#ifdef FIRM_GRGEN_BE + if (be_transformer == TRANSFORMER_DEFAULT) { + return be_transform_node(node); + } else { + return node; + } +#else + return be_transform_node(node); +#endif +} + ir_node *gen_ASM(ir_node *node) { - ir_node *block = NULL; - ir_node *new_block = NULL; + ir_node *block = get_nodes_block(node); + ir_node *new_block = get_new_node(block); dbg_info *dbgi = get_irn_dbg_info(node); int i, arity; + int value_arity; int out_idx; ir_node **in; ir_node *new_node; @@ -471,28 +447,12 @@ ir_node *gen_ASM(ir_node *node) const ir_asm_constraint *out_constraints; ident **clobbers; int clobbers_flags = 0; - unsigned clobber_bits[N_CLASSES]; + unsigned clobber_bits[N_IA32_CLASSES]; int out_size; + backend_info_t *info; memset(&clobber_bits, 0, sizeof(clobber_bits)); - switch (be_transformer) { - case TRANSFORMER_DEFAULT: - block = get_nodes_block(node); - new_block = be_transform_node(block); - break; - -#ifdef FIRM_GRGEN_BE - case TRANSFORMER_PBQP: - case TRANSFORMER_RAND: - new_block = get_nodes_block(node); - break; -#endif - - default: - panic("invalid transformer"); - } - /* workaround for lots of buggy code out there as most people think volatile * asm is enough for everything and forget the flags (linux kernel, etc.) */ @@ -534,7 +494,7 @@ ir_node *gen_ASM(ir_node *node) reg_map_size = constraint->pos; } for (i = 0; i < arity; ++i) { - const ir_asm_constraint *constraint = &in_constraints[i]; + const ir_asm_constraint *constraint = &in_constraints[i]; if (constraint->pos > reg_map_size) reg_map_size = constraint->pos; } @@ -546,7 +506,7 @@ ir_node *gen_ASM(ir_node *node) /* construct output constraints */ out_size = out_arity + 1; - out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0])); + out_reg_reqs = OALLOCN(obst, const arch_register_req_t*, out_size); for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) { const ir_asm_constraint *constraint = &out_constraints[out_idx]; @@ -568,7 +528,7 @@ ir_node *gen_ASM(ir_node *node) } /* inputs + input constraints */ - in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0])); + in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, arity); for (i = 0; i < arity; ++i) { ir_node *pred = get_irn_n(node, i); const ir_asm_constraint *constraint = &in_constraints[i]; @@ -587,7 +547,7 @@ ir_node *gen_ASM(ir_node *node) if (r_clobber_bits != 0) { if (parsed_constraint.all_registers_allowed) { parsed_constraint.all_registers_allowed = 0; - be_abi_set_non_ignore_regs(env_cg->birg->abi, + be_set_allocatable_regs(current_ir_graph, parsed_constraint.cls, &parsed_constraint.allowed_registers); } @@ -605,22 +565,8 @@ ir_node *gen_ASM(ir_node *node) } if (input == NULL) { - ir_node *pred = NULL; - switch (be_transformer) { - case TRANSFORMER_DEFAULT: - pred = get_irn_n(node, i); - input = be_transform_node(pred); - break; - -#ifdef FIRM_GRGEN_BE - case TRANSFORMER_PBQP: - case TRANSFORMER_RAND: - input = get_irn_n(node, i); - break; -#endif - - default: panic("invalid transformer"); - } + ir_node *pred = get_irn_n(node, i); + input = get_new_node(pred); if (parsed_constraint.cls == NULL && parsed_constraint.same_as < 0) { @@ -651,7 +597,16 @@ ir_node *gen_ASM(ir_node *node) ++out_idx; } - /* Attempt to make ASM node register pressure faithfull. + /* count inputs which are real values (and not memory) */ + value_arity = 0; + for (i = 0; i < arity; ++i) { + ir_node *in = get_irn_n(node, i); + if (get_irn_mode(in) == mode_M) + continue; + ++value_arity; + } + + /* Attempt to make ASM node register pressure faithful. * (This does not work for complicated cases yet!) * * Algorithm: Check if there are fewer inputs or outputs (I will call this @@ -663,7 +618,7 @@ ir_node *gen_ASM(ir_node *node) * before... * FIXME: need to do this per register class... */ - if (out_arity <= arity) { + if (out_arity <= value_arity) { int orig_arity = arity; int in_size = arity; int o; @@ -696,8 +651,8 @@ ir_node *gen_ASM(ir_node *node) ir_node **new_in; in_size *= 2; - new_in_reg_reqs - = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0])); + new_in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, + in_size); memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0])); new_in = ALLOCANZ(ir_node*, in_size); memcpy(new_in, in, arity*sizeof(new_in[0])); @@ -745,7 +700,7 @@ ir_node *gen_ASM(ir_node *node) out_size *= 2; new_out_reg_reqs - = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0])); + = OALLOCN(obst, const arch_register_req_t*, out_size); memcpy(new_out_reg_reqs, out_reg_reqs, out_arity * sizeof(new_out_reg_reqs[0])); out_reg_reqs = new_out_reg_reqs; @@ -764,7 +719,7 @@ ir_node *gen_ASM(ir_node *node) out_size = out_arity + 1; new_out_reg_reqs - = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0])); + = OALLOCN(obst, const arch_register_req_t*, out_size); memcpy(new_out_reg_reqs, out_reg_reqs, out_arity * sizeof(new_out_reg_reqs[0])); out_reg_reqs = new_out_reg_reqs; @@ -780,51 +735,31 @@ ir_node *gen_ASM(ir_node *node) if (arity == 0) be_dep_on_frame(new_node); - set_ia32_out_req_all(new_node, out_reg_reqs); - set_ia32_in_req_all(new_node, in_reg_reqs); + info = be_get_info(new_node); + for (i = 0; i < out_arity; ++i) { + info->out_infos[i].req = out_reg_reqs[i]; + } + arch_set_in_register_reqs(new_node, in_reg_reqs); SET_IA32_ORIG_NODE(new_node, node); return new_node; } -ir_node *gen_CopyB(ir_node *node) { - ir_node *block = NULL; - ir_node *src = NULL; - ir_node *new_src = NULL; - ir_node *dst = NULL; - ir_node *new_dst = NULL; - ir_node *mem = NULL; - ir_node *new_mem = NULL; +ir_node *gen_CopyB(ir_node *node) +{ + ir_node *block = get_new_node(get_nodes_block(node)); + ir_node *src = get_CopyB_src(node); + ir_node *new_src = get_new_node(src); + ir_node *dst = get_CopyB_dst(node); + ir_node *new_dst = get_new_node(dst); + ir_node *mem = get_CopyB_mem(node); + ir_node *new_mem = get_new_node(mem); ir_node *res = NULL; dbg_info *dbgi = get_irn_dbg_info(node); int size = get_type_size_bytes(get_CopyB_type(node)); int rem; - switch (be_transformer) { - case TRANSFORMER_DEFAULT: - block = be_transform_node(get_nodes_block(node)); - src = get_CopyB_src(node); - new_src = be_transform_node(src); - dst = get_CopyB_dst(node); - new_dst = be_transform_node(dst); - mem = get_CopyB_mem(node); - new_mem = be_transform_node(mem); - break; - -#ifdef FIRM_GRGEN_BE - case TRANSFORMER_PBQP: - case TRANSFORMER_RAND: - block = get_nodes_block(node); - new_src = get_CopyB_src(node); - new_dst = get_CopyB_dst(node); - new_mem = get_CopyB_mem(node); - break; -#endif - - default: panic("invalid transformer"); - } - /* If we have to copy more than 32 bytes, we use REP MOVSx and */ /* then we need the size explicitly in ECX. */ if (size >= 32 * 4) { @@ -848,54 +783,38 @@ ir_node *gen_CopyB(ir_node *node) { return res; } -ir_node *gen_Proj_tls(ir_node *node) { - ir_node *block = NULL; - dbg_info *dbgi = NULL; - ir_node *res = NULL; - - switch (be_transformer) { - case TRANSFORMER_DEFAULT: - block = be_transform_node(get_nodes_block(node)); - break; - -#ifdef FIRM_GRGEN_BE - case TRANSFORMER_PBQP: - case TRANSFORMER_RAND: - block = get_nodes_block(node); - break; -#endif - - default: panic("invalid transformer"); - } +ir_node *gen_Proj_tls(ir_node *node) +{ + ir_node *block = get_new_node(get_nodes_block(node)); + ir_node *res = NULL; - res = new_bd_ia32_LdTls(dbgi, block, mode_Iu); + res = new_bd_ia32_LdTls(NULL, block, mode_Iu); return res; } ir_node *gen_Unknown(ir_node *node) { - ir_mode *mode = get_irn_mode(node); + ir_mode *mode = get_irn_mode(node); + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_irg_start_block(irg); + ir_node *res = NULL; if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) { - return ia32_new_Unknown_xmm(env_cg); + res = new_bd_ia32_xUnknown(dbgi, block); } else { - /* Unknown nodes are buggy in x87 simulator, use zero for now... */ - ir_graph *irg = current_ir_graph; - dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *block = get_irg_start_block(irg); - ir_node *ret = new_bd_ia32_vfldz(dbgi, block); - - be_dep_on_frame(ret); - return ret; + res = new_bd_ia32_vfldz(dbgi, block); } } else if (ia32_mode_needs_gp_reg(mode)) { - return ia32_new_Unknown_gp(env_cg); + res = new_bd_ia32_Unknown(dbgi, block); } else { panic("unsupported Unknown-Mode"); } - return NULL; + + be_dep_on_frame(res); + return res; } const arch_register_req_t *make_register_req(const constraint_t *constraint, @@ -913,10 +832,11 @@ const arch_register_req_t *make_register_req(const constraint_t *constraint, other_constr = out_reqs[same_as]; - req = obstack_alloc(obst, sizeof(req[0])); + req = OALLOC(obst, arch_register_req_t); *req = *other_constr; req->type |= arch_register_req_type_should_be_same; req->other_same = 1U << pos; + req->width = 1; /* switch constraints. This is because in firm we have same_as * constraints on the output constraints while in the gcc asm syntax @@ -927,14 +847,14 @@ const arch_register_req_t *make_register_req(const constraint_t *constraint, /* pure memory ops */ if (constraint->cls == NULL) { - return &no_register_req; + return arch_no_register_req; } if (constraint->allowed_registers != 0 && !constraint->all_registers_allowed) { unsigned *limited_ptr; - req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned)); + req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned)); memset(req, 0, sizeof(req[0])); limited_ptr = (unsigned*) (req+1); @@ -942,11 +862,11 @@ const arch_register_req_t *make_register_req(const constraint_t *constraint, *limited_ptr = constraint->allowed_registers; req->limited = limited_ptr; } else { - req = obstack_alloc(obst, sizeof(req[0])); - memset(req, 0, sizeof(req[0])); + req = OALLOCZ(obst, arch_register_req_t); req->type = arch_register_req_type_normal; } - req->cls = constraint->cls; + req->cls = constraint->cls; + req->width = 1; return req; } @@ -964,14 +884,14 @@ const arch_register_req_t *parse_clobber(const char *clobber) assert(reg->index < 32); - limited = obstack_alloc(obst, sizeof(limited[0])); + limited = OALLOC(obst, unsigned); *limited = 1 << reg->index; - req = obstack_alloc(obst, sizeof(req[0])); - memset(req, 0, sizeof(req[0])); + req = OALLOCZ(obst, arch_register_req_t); req->type = arch_register_req_type_limited; req->cls = arch_register_get_class(reg); req->limited = limited; + req->width = 1; return req; } @@ -1017,12 +937,8 @@ int prevents_AM(ir_node *const block, ir_node *const am_candidate, ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) { - int minus = 0; - tarval *offset = NULL; - int offset_sign = 0; long val = 0; ir_entity *symconst_ent = NULL; - int symconst_sign = 0; ir_mode *mode; ir_node *cnst = NULL; ir_node *symconst = NULL; @@ -1033,61 +949,34 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) return NULL; } - if (is_Minus(node)) { - minus = 1; - node = get_Minus_op(node); - } - if (is_Const(node)) { - cnst = node; - symconst = NULL; - offset_sign = minus; - } else if (is_SymConst(node)) { - cnst = NULL; - symconst = node; - symconst_sign = minus; + cnst = node; + symconst = NULL; + } else if (is_Global(node)) { + cnst = NULL; + symconst = node; } else if (is_Add(node)) { ir_node *left = get_Add_left(node); ir_node *right = get_Add_right(node); - if (is_Const(left) && is_SymConst(right)) { - cnst = left; - symconst = right; - symconst_sign = minus; - offset_sign = minus; - } else if (is_SymConst(left) && is_Const(right)) { - cnst = right; - symconst = left; - symconst_sign = minus; - offset_sign = minus; - } - } else if (is_Sub(node)) { - ir_node *left = get_Sub_left(node); - ir_node *right = get_Sub_right(node); - if (is_Const(left) && is_SymConst(right)) { - cnst = left; - symconst = right; - symconst_sign = !minus; - offset_sign = minus; - } else if (is_SymConst(left) && is_Const(right)) { - cnst = right; - symconst = left; - symconst_sign = minus; - offset_sign = !minus; + if (is_Const(left) && is_Global(right)) { + cnst = left; + symconst = right; + } else if (is_Global(left) && is_Const(right)) { + cnst = right; + symconst = left; } } else { return NULL; } if (cnst != NULL) { - offset = get_Const_tarval(cnst); - if (tarval_is_long(offset)) { - val = get_tarval_long(offset); - } else { - ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a " - "long?\n", cnst); + ir_tarval *offset = get_Const_tarval(cnst); + if (!tarval_is_long(offset)) { + ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst); return NULL; } + val = get_tarval_long(offset); if (!check_immediate_constraint(val, immediate_constraint_type)) return NULL; } @@ -1097,22 +986,11 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) return NULL; } - /* unfortunately the assembler/linker doesn't support -symconst */ - if (symconst_sign) - return NULL; - - if (get_SymConst_kind(symconst) != symconst_addr_ent) - return NULL; - symconst_ent = get_SymConst_entity(symconst); + symconst_ent = get_Global_entity(symconst); } if (cnst == NULL && symconst == NULL) return NULL; - if (offset_sign && offset != NULL) { - offset = tarval_neg(offset); - } - - new_node = ia32_create_Immediate(symconst_ent, symconst_sign, val); - + new_node = ia32_create_Immediate(symconst_ent, 0, val); return new_node; }