X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_common_transform.c;h=5b2276826f5a52f236f25329558838b5d69f6e8e;hb=ce6161a7e42a48f7422b7babcc64d8ace18e2687;hp=1aa217d77efa7e62546e86d94097e24a674a004a;hpb=1c551372962ff38bb7bda281616268e14ff4bde0;p=libfirm diff --git a/ir/be/ia32/ia32_common_transform.c b/ir/be/ia32/ia32_common_transform.c index 1aa217d77..5b2276826 100644 --- a/ir/be/ia32/ia32_common_transform.c +++ b/ir/be/ia32/ia32_common_transform.c @@ -31,6 +31,7 @@ #include "irprintf.h" #include "typerep.h" #include "bitset.h" +#include "heights.h" #include "../betranshlp.h" #include "../beirg.h" @@ -43,18 +44,7 @@ #include "gen_ia32_new_nodes.h" #include "gen_ia32_regalloc_if.h" -/** hold the current code generator during transformation */ -ia32_code_gen_t *env_cg = NULL; - -heights_t *heights = NULL; - -static const arch_register_req_t no_register_req = { - arch_register_req_type_none, - NULL, /* regclass */ - NULL, /* limit bitset */ - 0, /* same pos */ - 0 /* different pos */ -}; +ir_heights_t *heights = NULL; static int check_immediate_constraint(long val, char immediate_constraint_type) { @@ -74,90 +64,64 @@ static int check_immediate_constraint(long val, char immediate_constraint_type) } } -/* creates a unique ident by adding a number to a tag */ -ident *ia32_unique_id(const char *tag) -{ - static unsigned id = 0; - char str[256]; - - snprintf(str, sizeof(str), tag, ++id); - return new_id_from_str(str); -} - /** * Get a primitive type for a mode with alignment 16. */ static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode) { - pmap_entry *e = pmap_find(types, mode); - ir_type *res; + ir_type *res = (ir_type*)pmap_get(types, mode); + if (res != NULL) + return res; - if (! e) { - res = new_type_primitive(mode); - if (get_mode_size_bits(mode) >= 80) { - set_type_alignment_bytes(res, 16); - } - pmap_insert(types, mode, res); + res = new_type_primitive(mode); + if (get_mode_size_bits(mode) >= 80) { + set_type_alignment_bytes(res, 16); } - else - res = e->value; + pmap_insert(types, mode, res); return res; } ir_entity *create_float_const_entity(ir_node *cnst) { - ia32_isa_t *isa = env_cg->isa; - tarval *key = get_Const_tarval(cnst); - pmap_entry *e = pmap_find(isa->tv_ent, key); - ir_entity *res; - ir_graph *rem; - - if (e == NULL) { - tarval *tv = key; - ir_mode *mode = get_tarval_mode(tv); - ir_type *tp; - - if (! ia32_cg_config.use_sse2) { - /* try to reduce the mode to produce smaller sized entities */ - if (mode != mode_F) { - if (tarval_ieee754_can_conv_lossless(tv, mode_F)) { - mode = mode_F; + ir_graph *irg = get_irn_irg(cnst); + const arch_env_t *arch_env = be_get_irg_arch_env(irg); + ia32_isa_t *isa = (ia32_isa_t*) arch_env; + ir_tarval *tv = get_Const_tarval(cnst); + ir_entity *res = (ir_entity*)pmap_get(isa->tv_ent, tv); + ir_initializer_t *initializer; + ir_mode *mode; + ir_type *tp; + + if (res != NULL) + return res; + + mode = get_tarval_mode(tv); + + if (! ia32_cg_config.use_sse2) { + /* try to reduce the mode to produce smaller sized entities */ + if (mode != mode_F) { + if (tarval_ieee754_can_conv_lossless(tv, mode_F)) { + mode = mode_F; + tv = tarval_convert_to(tv, mode); + } else if (mode != mode_D) { + if (tarval_ieee754_can_conv_lossless(tv, mode_D)) { + mode = mode_D; tv = tarval_convert_to(tv, mode); - } else if (mode != mode_D) { - if (tarval_ieee754_can_conv_lossless(tv, mode_D)) { - mode = mode_D; - tv = tarval_convert_to(tv, mode); - } } } } + } - if (mode == get_irn_mode(cnst)) { - /* mode was not changed */ - tp = get_Const_type(cnst); - if (tp == firm_unknown_type) - tp = ia32_get_prim_type(isa->types, mode); - } else - tp = ia32_get_prim_type(isa->types, mode); - - res = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp); - - set_entity_ld_ident(res, get_entity_ident(res)); - set_entity_visibility(res, ir_visibility_local); - add_entity_linkage(res, IR_LINKAGE_CONSTANT); + tp = ia32_get_prim_type(isa->types, mode); + res = new_entity(get_glob_type(), id_unique("C%u"), tp); + set_entity_ld_ident(res, get_entity_ident(res)); + set_entity_visibility(res, ir_visibility_private); + add_entity_linkage(res, IR_LINKAGE_CONSTANT); - /* we create a new entity here: It's initialization must resist on the - const code irg */ - rem = current_ir_graph; - current_ir_graph = get_const_code_irg(); - set_atomic_ent_value(res, new_Const_type(tv, tp)); - current_ir_graph = rem; - - pmap_insert(isa->tv_ent, key, res); - } else { - res = e->value; - } + initializer = create_initializer_tarval(tv); + set_entity_initializer(res, initializer); + pmap_insert(isa->tv_ent, tv, res); return res; } @@ -167,7 +131,7 @@ ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val) ir_node *start_block = get_irg_start_block(irg); ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, symconst, symconst_sign, no_pic_adjust, val); - arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]); + arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]); return immediate; } @@ -181,7 +145,7 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber) /* TODO: construct a hashmap instead of doing linear search for clobber * register */ - for (c = 0; c < N_CLASSES; ++c) { + for (c = 0; c < N_IA32_CLASSES; ++c) { cls = & ia32_reg_classes[c]; for (r = 0; r < cls->n_regs; ++r) { const arch_register_t *temp_reg = arch_register_for_index(cls, r); @@ -254,32 +218,32 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, case 'a': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX; + limited |= 1 << REG_GP_EAX; break; case 'b': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EBX; + limited |= 1 << REG_GP_EBX; break; case 'c': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_ECX; + limited |= 1 << REG_GP_ECX; break; case 'd': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EDX; + limited |= 1 << REG_GP_EDX; break; case 'D': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EDI; + limited |= 1 << REG_GP_EDI; break; case 'S': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_ESI; + limited |= 1 << REG_GP_ESI; break; case 'Q': case 'q': @@ -287,20 +251,20 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c, * difference to Q for us (we only assign whole registers) */ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | - 1 << REG_EDX; + limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX | + 1 << REG_GP_EDX; break; case 'A': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EDX; + limited |= 1 << REG_GP_EAX | 1 << REG_GP_EDX; break; case 'l': assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]); cls = &ia32_reg_classes[CLASS_ia32_gp]; - limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX | - 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI | - 1 << REG_EBP; + limited |= 1 << REG_GP_EAX | 1 << REG_GP_EBX | 1 << REG_GP_ECX | + 1 << REG_GP_EDX | 1 << REG_GP_ESI | 1 << REG_GP_EDI | + 1 << REG_GP_EBP; break; case 'R': @@ -483,7 +447,7 @@ ir_node *gen_ASM(ir_node *node) const ir_asm_constraint *out_constraints; ident **clobbers; int clobbers_flags = 0; - unsigned clobber_bits[N_CLASSES]; + unsigned clobber_bits[N_IA32_CLASSES]; int out_size; backend_info_t *info; @@ -542,7 +506,7 @@ ir_node *gen_ASM(ir_node *node) /* construct output constraints */ out_size = out_arity + 1; - out_reg_reqs = obstack_alloc(obst, out_size * sizeof(out_reg_reqs[0])); + out_reg_reqs = OALLOCN(obst, const arch_register_req_t*, out_size); for (out_idx = 0; out_idx < n_out_constraints; ++out_idx) { const ir_asm_constraint *constraint = &out_constraints[out_idx]; @@ -564,7 +528,7 @@ ir_node *gen_ASM(ir_node *node) } /* inputs + input constraints */ - in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0])); + in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, arity); for (i = 0; i < arity; ++i) { ir_node *pred = get_irn_n(node, i); const ir_asm_constraint *constraint = &in_constraints[i]; @@ -583,7 +547,7 @@ ir_node *gen_ASM(ir_node *node) if (r_clobber_bits != 0) { if (parsed_constraint.all_registers_allowed) { parsed_constraint.all_registers_allowed = 0; - be_abi_set_non_ignore_regs(env_cg->birg->abi, + be_set_allocatable_regs(current_ir_graph, parsed_constraint.cls, &parsed_constraint.allowed_registers); } @@ -687,8 +651,8 @@ ir_node *gen_ASM(ir_node *node) ir_node **new_in; in_size *= 2; - new_in_reg_reqs - = obstack_alloc(obst, in_size*sizeof(in_reg_reqs[0])); + new_in_reg_reqs = OALLOCN(obst, const arch_register_req_t*, + in_size); memcpy(new_in_reg_reqs, in_reg_reqs, arity * sizeof(new_in_reg_reqs[0])); new_in = ALLOCANZ(ir_node*, in_size); memcpy(new_in, in, arity*sizeof(new_in[0])); @@ -736,7 +700,7 @@ ir_node *gen_ASM(ir_node *node) out_size *= 2; new_out_reg_reqs - = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0])); + = OALLOCN(obst, const arch_register_req_t*, out_size); memcpy(new_out_reg_reqs, out_reg_reqs, out_arity * sizeof(new_out_reg_reqs[0])); out_reg_reqs = new_out_reg_reqs; @@ -755,7 +719,7 @@ ir_node *gen_ASM(ir_node *node) out_size = out_arity + 1; new_out_reg_reqs - = obstack_alloc(obst, out_size*sizeof(out_reg_reqs[0])); + = OALLOCN(obst, const arch_register_req_t*, out_size); memcpy(new_out_reg_reqs, out_reg_reqs, out_arity * sizeof(new_out_reg_reqs[0])); out_reg_reqs = new_out_reg_reqs; @@ -775,7 +739,7 @@ ir_node *gen_ASM(ir_node *node) for (i = 0; i < out_arity; ++i) { info->out_infos[i].req = out_reg_reqs[i]; } - set_ia32_in_req_all(new_node, in_reg_reqs); + arch_set_in_register_reqs(new_node, in_reg_reqs); SET_IA32_ORIG_NODE(new_node, node); @@ -868,10 +832,11 @@ const arch_register_req_t *make_register_req(const constraint_t *constraint, other_constr = out_reqs[same_as]; - req = obstack_alloc(obst, sizeof(req[0])); + req = OALLOC(obst, arch_register_req_t); *req = *other_constr; req->type |= arch_register_req_type_should_be_same; req->other_same = 1U << pos; + req->width = 1; /* switch constraints. This is because in firm we have same_as * constraints on the output constraints while in the gcc asm syntax @@ -882,14 +847,14 @@ const arch_register_req_t *make_register_req(const constraint_t *constraint, /* pure memory ops */ if (constraint->cls == NULL) { - return &no_register_req; + return arch_no_register_req; } if (constraint->allowed_registers != 0 && !constraint->all_registers_allowed) { unsigned *limited_ptr; - req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned)); + req = (arch_register_req_t*)obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned)); memset(req, 0, sizeof(req[0])); limited_ptr = (unsigned*) (req+1); @@ -897,11 +862,11 @@ const arch_register_req_t *make_register_req(const constraint_t *constraint, *limited_ptr = constraint->allowed_registers; req->limited = limited_ptr; } else { - req = obstack_alloc(obst, sizeof(req[0])); - memset(req, 0, sizeof(req[0])); + req = OALLOCZ(obst, arch_register_req_t); req->type = arch_register_req_type_normal; } - req->cls = constraint->cls; + req->cls = constraint->cls; + req->width = 1; return req; } @@ -919,14 +884,14 @@ const arch_register_req_t *parse_clobber(const char *clobber) assert(reg->index < 32); - limited = obstack_alloc(obst, sizeof(limited[0])); + limited = OALLOC(obst, unsigned); *limited = 1 << reg->index; - req = obstack_alloc(obst, sizeof(req[0])); - memset(req, 0, sizeof(req[0])); + req = OALLOCZ(obst, arch_register_req_t); req->type = arch_register_req_type_limited; req->cls = arch_register_get_class(reg); req->limited = limited; + req->width = 1; return req; } @@ -1005,7 +970,7 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type) } if (cnst != NULL) { - tarval *offset = get_Const_tarval(cnst); + ir_tarval *offset = get_Const_tarval(cnst); if (!tarval_is_long(offset)) { ir_fprintf(stderr, "Optimisation Warning: tarval of %+F is not a long?\n", cnst); return NULL;