X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_architecture.c;h=bb6a82b485dd32e98fbc8ac588b001cfd1672d31;hb=7fc5212efdd0faf06fed3850760ca319bdc66afc;hp=6e3e141d7a8940e19a114203217b4539282a5233;hpb=39cb52264857d7c21c7141ba82bb55adaa78064d;p=libfirm diff --git a/ir/be/ia32/ia32_architecture.c b/ir/be/ia32/ia32_architecture.c index 6e3e141d7..bb6a82b48 100644 --- a/ir/be/ia32/ia32_architecture.c +++ b/ir/be/ia32/ia32_architecture.c @@ -33,6 +33,10 @@ #include "bearch_ia32_t.h" #include "ia32_architecture.h" +#ifdef _MSC_VER +#include +#endif + ia32_code_gen_config_t ia32_cg_config; /** @@ -93,7 +97,7 @@ enum cpu_arch_features { /** * CPU's. */ -enum cpu_support { +typedef enum cpu_support { cpu_generic = arch_generic32, /* intel CPUs */ @@ -127,7 +131,9 @@ enum cpu_support { cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow, cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow, cpu_c3_2 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */ -}; + + cpu_autodetect = 0, +} cpu_support; static int opt_size = 0; static int emit_machcode = 0; @@ -188,6 +194,8 @@ static const lc_opt_enum_int_items_t arch_items[] = { { "generic", cpu_generic }, { "generic32", cpu_generic }, + + { "native", cpu_autodetect }, { NULL, 0 } }; @@ -438,12 +446,13 @@ static void set_arch_costs(void) } /* Evaluate the costs of an instruction. */ -int ia32_evaluate_insn(insn_kind kind, tarval *tv) { +int ia32_evaluate_insn(insn_kind kind, const ir_mode *mode, ir_tarval *tv) +{ int cost; switch (kind) { case MUL: - cost = arch_costs->cost_mul_start; + cost = arch_costs->cost_mul_start; if (arch_costs->cost_mul_bit > 0) { char *bitstr = get_tarval_bitpattern(tv); int i; @@ -455,14 +464,27 @@ int ia32_evaluate_insn(insn_kind kind, tarval *tv) { } free(bitstr); } - return cost; + if (get_mode_size_bits(mode) <= 32) + return cost; + /* 64bit mul supported, approx 4times of a 32bit mul*/ + return 4 * cost; case LEA: - return arch_costs->lea_cost; + /* lea is only supported for 32 bit */ + if (get_mode_size_bits(mode) <= 32) + return arch_costs->lea_cost; + /* in 64bit mode, the Lea cost are at wort 2 shifts and one add */ + return 2 * arch_costs->add_cost + 2 * (2 * arch_costs->const_shf_cost); case ADD: case SUB: - return arch_costs->add_cost; + if (get_mode_size_bits(mode) <= 32) + return arch_costs->add_cost; + /* 64bit add/sub supported, double the cost */ + return 2 * arch_costs->add_cost; case SHIFT: - return arch_costs->const_shf_cost; + if (get_mode_size_bits(mode) <= 32) + return arch_costs->const_shf_cost; + /* 64bit shift supported, double the cost */ + return 2 * arch_costs->const_shf_cost; case ZERO: return arch_costs->add_cost; default: @@ -470,6 +492,256 @@ int ia32_evaluate_insn(insn_kind kind, tarval *tv) { } } +typedef struct cpu_info_t { + unsigned char cpu_stepping; + unsigned char cpu_model; + unsigned char cpu_family; + unsigned char cpu_type; + unsigned char cpu_ext_model; + unsigned char cpu_ext_family; + unsigned edx_features; + unsigned ecx_features; + unsigned add_features; +} cpu_info_t; + +static cpu_support auto_detect_Intel(cpu_info_t const *info) { + cpu_support auto_arch = cpu_generic; + + unsigned family = (info->cpu_ext_family << 4) | info->cpu_family; + unsigned model = (info->cpu_ext_model << 4) | info->cpu_model; + + switch (family) { + case 4: + auto_arch = arch_i486; + break; + case 5: + auto_arch = arch_pentium; + break; + case 6: + switch (model) { + case 0x01: /* PentiumPro */ + case 0x03: /* Pentium II Model 3 */ + case 0x05: /* Pentium II Model 5 */ + case 0x06: /* Celeron Model 6 */ + case 0x07: /* Pentium III Model 7 */ + case 0x08: /* Pentium III Model 8 */ + case 0x09: /* Pentium M Model 9 */ + case 0x0A: /* Pentium III Model 0A */ + case 0x0B: /* Pentium III Model 0B */ + case 0x0D: /* Pentium M Model 0D */ + auto_arch = arch_ppro; + break; + case 0x0E: /* Core Model 0E */ + auto_arch = arch_ppro; + break; + case 0x0F: /* Core2 Model 0F */ + case 0x15: /* Intel EP80579 */ + case 0x16: /* Celeron Model 16 */ + case 0x17: /* Core2 Model 17 */ + auto_arch = arch_core2; + break; + default: + /* unknown */ + break; + } + break; + case 15: + switch (model) { + case 0x00: /* Pentium 4 Model 00 */ + case 0x01: /* Pentium 4 Model 01 */ + case 0x02: /* Pentium 4 Model 02 */ + case 0x03: /* Pentium 4 Model 03 */ + case 0x04: /* Pentium 4 Model 04 */ + case 0x06: /* Pentium 4 Model 06 */ + auto_arch = arch_netburst; + break; + case 0x1A: /* Core i7 */ + auto_arch = arch_core2; + break; + case 0x1C: /* Atom */ + auto_arch = arch_atom; + break; + case 0x1D: /* Xeon MP */ + auto_arch = arch_core2; + break; + default: + /* unknown */ + break; + } + break; + default: + /* unknown */ + break; + } + + if (info->edx_features & (1<<23)) auto_arch |= arch_feature_mmx; + if (info->edx_features & (1<<25)) auto_arch |= arch_feature_sse1; + if (info->edx_features & (1<<26)) auto_arch |= arch_feature_sse2; + + if (info->ecx_features & (1<< 0)) auto_arch |= arch_feature_sse3; + if (info->ecx_features & (1<< 9)) auto_arch |= arch_feature_ssse3; + if (info->ecx_features & (1<<19)) auto_arch |= arch_feature_sse4_1; + if (info->ecx_features & (1<<20)) auto_arch |= arch_feature_sse4_2; + + return auto_arch; +} + +static cpu_support auto_detect_AMD(cpu_info_t const *info) { + cpu_support auto_arch = cpu_generic; + + unsigned family, model; + + if (info->cpu_family == 0x0F) { + family = (info->cpu_ext_family << 4) | info->cpu_family; + model = (info->cpu_ext_model << 4) | info->cpu_model; + } else { + family = info->cpu_family; + model = info->cpu_model; + } + + switch (family) { + case 0x04: + auto_arch = arch_i486; + break; + case 0x05: + case 0x06: // actually, 6 means K7 family + auto_arch = arch_k6; + break; + case 0x0F: + auto_arch = arch_k8; + break; + case 0x1F: + case 0x2F: + auto_arch = arch_k10; + break; + default: + /* unknown */ + break; + } + + if (info->edx_features & (1<<23)) auto_arch |= arch_feature_mmx; + if (info->edx_features & (1<<25)) auto_arch |= arch_feature_sse1; + if (info->edx_features & (1<<26)) auto_arch |= arch_feature_sse2; + + if (info->ecx_features & (1<< 0)) auto_arch |= arch_feature_sse3; + if (info->ecx_features & (1<< 9)) auto_arch |= arch_feature_ssse3; + if (info->ecx_features & (1<<19)) auto_arch |= arch_feature_sse4_1; + if (info->ecx_features & (1<<20)) auto_arch |= arch_feature_sse4_2; + + return auto_arch; +} + +typedef union { + struct { + unsigned eax; + unsigned ebx; + unsigned ecx; + unsigned edx; + } r; + int bulk[4]; +} cpuid_registers; + +static void x86_cpuid(cpuid_registers *regs, unsigned level) +{ +#if defined(__GNUC__) + /* 32bit requires ebx to be saved, and it doesn't hurt on 64 bit */ + __asm ("pushl %%ebx\n\t" + "cpuid\n\t" + "movl %%ebx, %1\n\t" + "popl %%ebx\n\t" + : "=a" (regs->r.eax), "=r" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx) + : "a" (level) + ); +#elif defined(_MSC_VER) + __cpuid(regs->bulk, level); +#endif +} + +static int x86_toogle_cpuid(void) +{ + unsigned eflags_before = 0, eflags_after = 0; + +#if defined(__GNUC__) +#ifdef __i386__ + /* If bit 21 of the EFLAGS register can be changed, the cpuid instruction is available */ + __asm__( + "pushf\n\t" + "popl %0\n\t" + "movl %0, %1\n\t" + "xorl $0x00200000, %1\n\t" + "pushl %1\n\t" + "popf\n\t" + "pushf\n\t" + "popl %1" + : "=r" (eflags_before), "=r" (eflags_after) :: "cc" + ); +#else + /* cpuid always available on 64bit */ + return true; +#endif +#elif defined(_MSC_VER) +#if defined(_M_IX86) + __asm { + pushfd + pop eax + mov eflags_before, eax + xor eax, 0x00200000 + push eax + popfd + pushfd + pop eax + mov eflags_after, eax + } +#else + return true; +#endif +#endif + return (eflags_before ^ eflags_after) & 0x00200000; +} + +static void autodetect_arch(void) +{ + cpu_support auto_arch = cpu_generic; + + /* We use the cpuid instruction to detect the CPU features */ + if (x86_toogle_cpuid()) { + cpuid_registers regs; + unsigned highest_level; + char vendorid[13]; + struct cpu_info_t cpu_info; + + /* get vendor ID */ + x86_cpuid(®s, 0); + highest_level = regs.r.eax; + memcpy(&vendorid[0], ®s.r.ebx, 4); + memcpy(&vendorid[4], ®s.r.edx, 4); + memcpy(&vendorid[8], ®s.r.ecx, 4); + vendorid[12] = '\0'; + + /* get processor info and feature bits */ + x86_cpuid(®s, 1); + + cpu_info.cpu_stepping = (regs.r.eax >> 0) & 0x0F; + cpu_info.cpu_model = (regs.r.eax >> 4) & 0x0F; + cpu_info.cpu_family = (regs.r.eax >> 8) & 0x0F; + cpu_info.cpu_type = (regs.r.eax >> 12) & 0x03; + cpu_info.cpu_ext_model = (regs.r.eax >> 16) & 0x0F; + cpu_info.cpu_ext_family = (regs.r.eax >> 20) & 0xFF; + cpu_info.edx_features = regs.r.edx; + cpu_info.ecx_features = regs.r.ecx; + cpu_info.add_features = regs.r.ebx; + + if (0 == strcmp(vendorid, "GenuineIntel")) { + auto_arch = auto_detect_Intel(&cpu_info); + } else if (0 == strcmp(vendorid, "AuthenticAMD")) { + auto_arch = auto_detect_AMD(&cpu_info); + } + } + + arch = auto_arch; + opt_arch = auto_arch; +} + void ia32_setup_cg_config(void) { ia32_code_gen_config_t *const c = &ia32_cg_config; @@ -477,6 +749,8 @@ void ia32_setup_cg_config(void) set_arch_costs(); + if (arch == 0) autodetect_arch(); + c->optimize_size = opt_size != 0; /* on newer intel cpus mov, pop is often faster than leave although it has a * longer opcode */