X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fia32_architecture.c;h=3501f249328e1a24b270dfa4e05e3b789ea24af3;hb=fef8dc3eff6468d7d65485af8e1ac9884c504e1a;hp=7bce4ab4de4043dae2faaf3e1c70dc459f0a8a0f;hpb=6538813a1436408b9d5547090dd181d25d820bf5;p=libfirm diff --git a/ir/be/ia32/ia32_architecture.c b/ir/be/ia32/ia32_architecture.c index 7bce4ab4d..3501f2493 100644 --- a/ir/be/ia32/ia32_architecture.c +++ b/ir/be/ia32/ia32_architecture.c @@ -21,10 +21,10 @@ * @file * @brief ia32 architecture variants * @author Michael Beck, Matthias Braun - * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $ */ #include "config.h" +#include #include "lc_opts.h" #include "lc_opts_enum.h" @@ -51,7 +51,7 @@ ia32_code_gen_config_t ia32_cg_config; /** * CPU architectures and features. */ -enum cpu_arch_features { +typedef enum cpu_arch_features { arch_generic32 = 0x00000001, /**< no specific architecture */ arch_i386 = 0x00000002, /**< i386 architecture */ @@ -98,44 +98,47 @@ enum cpu_arch_features { arch_sse4_2_insn = arch_feature_sse4_2 | arch_sse4_1_insn, /**< SSE4.2 instructions, include SSE4.1 */ arch_sse4a_insn = arch_feature_sse4a | arch_ssse3_insn, /**< SSE4a instructions, include SSSE3 */ - arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */ + arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */ arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */ arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */ -}; - -#define FLAGS(x, f) (((x) & (f)) != 0) -/** - * CPU's. - */ -typedef enum cpu_support { - cpu_generic = arch_generic32, + cpu_generic = arch_generic32, /* intel CPUs */ - cpu_i386 = arch_i386, - cpu_i486 = arch_i486, - cpu_pentium = arch_pentium, - cpu_pentium_mmx = arch_pentium | arch_mmx_insn, - cpu_pentium_pro = arch_ppro | arch_feature_cmov | arch_feature_p6_insn, - cpu_pentium_2 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_mmx_insn, - cpu_pentium_3 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse1_insn, - cpu_pentium_m = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse2_insn, - cpu_pentium_4 = arch_netburst | arch_feature_cmov | arch_feature_p6_insn | arch_sse2_insn, - cpu_prescott = arch_nocona | arch_feature_cmov | arch_feature_p6_insn | arch_sse3_insn, - cpu_nocona = arch_nocona | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn, - cpu_core2 = arch_core2 | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn, - cpu_penryn = arch_core2 | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn, + cpu_i386 = arch_i386, + cpu_i486 = arch_i486, + cpu_pentium = arch_pentium, + cpu_pentium_mmx = arch_pentium | arch_mmx_insn, + cpu_pentium_pro_generic = arch_ppro | arch_feature_p6_insn, + cpu_pentium_pro = arch_ppro | arch_feature_cmov | arch_feature_p6_insn, + cpu_pentium_2 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_mmx_insn, + cpu_pentium_3 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse1_insn, + cpu_pentium_m = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse2_insn, + cpu_netburst_generic = arch_netburst | arch_feature_p6_insn, + cpu_pentium_4 = arch_netburst | arch_feature_cmov | arch_feature_p6_insn | arch_sse2_insn, + cpu_prescott = arch_nocona | arch_feature_cmov | arch_feature_p6_insn | arch_sse3_insn, + cpu_nocona = arch_nocona | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn, + cpu_core2_generic = arch_core2 | arch_feature_p6_insn, + cpu_core2 = arch_core2 | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn, + cpu_penryn = arch_core2 | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn, + cpu_atom_generic = arch_atom | arch_feature_p6_insn, + cpu_atom = arch_atom | arch_feature_cmov | arch_feature_p6_insn | arch_ssse3_insn, /* AMD CPUs */ - cpu_k6 = arch_k6 | arch_mmx_insn, - cpu_k6_PLUS = arch_k6 | arch_3DNow_insn, - cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn, - cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn, - cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn, - cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn, - cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn, - cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn, - cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_feature_popcnt | arch_64bit_insn | arch_sse4a_insn, + cpu_k6_generic = arch_k6, + cpu_k6 = arch_k6 | arch_mmx_insn, + cpu_k6_PLUS = arch_k6 | arch_3DNow_insn, + cpu_geode_generic = arch_geode, + cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn, + cpu_athlon_generic = arch_athlon | arch_feature_p6_insn, + cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn, + cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn, + cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn, + cpu_k8_generic = arch_k8 | arch_feature_p6_insn, + cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn, + cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn, + cpu_k10_generic = arch_k10 | arch_feature_p6_insn, + cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_cmov | arch_feature_p6_insn | arch_feature_popcnt | arch_64bit_insn | arch_sse4a_insn, /* other CPUs */ cpu_winchip_c6 = arch_i486 | arch_feature_mmx, @@ -144,15 +147,16 @@ typedef enum cpu_support { cpu_c3_2 = arch_ppro | arch_feature_cmov | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */ cpu_autodetect = 0, -} cpu_support; +} cpu_arch_features; +ENUM_BITSET(cpu_arch_features) -static int opt_size = 0; -static int emit_machcode = 0; -static cpu_support arch = cpu_generic; -static cpu_support opt_arch = cpu_generic; -static int use_sse2 = 0; -static int opt_cc = 1; -static int opt_unsafe_floatconv = 0; +static int opt_size = 0; +static int emit_machcode = 0; +static cpu_arch_features arch = cpu_generic; +static cpu_arch_features opt_arch = cpu_generic; +static int fpu_arch = 0; +static int opt_cc = 1; +static int opt_unsafe_floatconv = 0; /* instruction set architectures. */ static const lc_opt_enum_int_items_t arch_items[] = { @@ -178,6 +182,7 @@ static const lc_opt_enum_int_items_t arch_items[] = { { "merom", cpu_core2 }, { "core2", cpu_core2 }, { "penryn", cpu_penryn }, + { "atom", cpu_atom }, { "k6", cpu_k6 }, { "k6-2", cpu_k6_PLUS }, @@ -222,29 +227,24 @@ static lc_opt_enum_int_var_t opt_arch_var = { }; static const lc_opt_enum_int_items_t fp_unit_items[] = { - { "x87" , 0 }, - { "sse2", 1 }, - { NULL, 0 } + { "x87" , IA32_FPU_ARCH_X87 }, + { "sse2", IA32_FPU_ARCH_SSE2 }, + { "softfloat", IA32_FPU_ARCH_SOFTFLOAT }, + { NULL, IA32_FPU_ARCH_NONE } }; static lc_opt_enum_int_var_t fp_unit_var = { - &use_sse2, fp_unit_items + &fpu_arch, fp_unit_items }; static const lc_opt_table_entry_t ia32_architecture_options[] = { - LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size), - LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", - &arch_var), - LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", - &opt_arch_var), - LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", - &fp_unit_var), - LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention", - &opt_cc, 1), - LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword " - "optimisations", &opt_unsafe_floatconv, 1), - LC_OPT_ENT_BOOL("machcode", "output machine code instead of assembler", - &emit_machcode), + LC_OPT_ENT_BOOL ("size", "optimize for size", &opt_size), + LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var), + LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var), + LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var), + LC_OPT_ENT_NEGBOOL ("nooptcc", "do not optimize calling convention", &opt_cc), + LC_OPT_ENT_BOOL ("unsafe_floatconv", "do unsafe floating point controlword optimisations", &opt_unsafe_floatconv), + LC_OPT_ENT_BOOL ("machcode", "output machine code instead of assembler", &emit_machcode), LC_OPT_LAST }; @@ -579,19 +579,19 @@ enum { CPUID_FEAT_EDX_PBE = 1 << 31 }; -static cpu_support auto_detect_Intel(x86_cpu_info_t const *info) +static cpu_arch_features auto_detect_Intel(x86_cpu_info_t const *info) { - cpu_support auto_arch = cpu_generic; + cpu_arch_features auto_arch = cpu_generic; - unsigned family = (info->cpu_ext_family << 4) | info->cpu_family; - unsigned model = (info->cpu_ext_model << 4) | info->cpu_model; + unsigned family = info->cpu_ext_family + info->cpu_family; + unsigned model = (info->cpu_ext_model << 4) | info->cpu_model; switch (family) { case 4: - auto_arch = arch_i486; + auto_arch = cpu_i486; break; case 5: - auto_arch = arch_pentium; + auto_arch = cpu_pentium; break; case 6: switch (model) { @@ -605,16 +605,14 @@ static cpu_support auto_detect_Intel(x86_cpu_info_t const *info) case 0x0A: /* Pentium III Model 0A */ case 0x0B: /* Pentium III Model 0B */ case 0x0D: /* Pentium M Model 0D */ - auto_arch = arch_ppro | arch_feature_p6_insn; - break; case 0x0E: /* Core Model 0E */ - auto_arch = arch_ppro | arch_feature_p6_insn; + auto_arch = cpu_pentium_pro_generic; break; case 0x0F: /* Core2 Model 0F */ case 0x15: /* Intel EP80579 */ case 0x16: /* Celeron Model 16 */ case 0x17: /* Core2 Model 17 */ - auto_arch = arch_core2 | arch_feature_p6_insn; + auto_arch = cpu_core2_generic; break; default: /* unknown */ @@ -629,16 +627,16 @@ static cpu_support auto_detect_Intel(x86_cpu_info_t const *info) case 0x03: /* Pentium 4 Model 03 */ case 0x04: /* Pentium 4 Model 04 */ case 0x06: /* Pentium 4 Model 06 */ - auto_arch = arch_netburst | arch_feature_p6_insn; + auto_arch = cpu_netburst_generic; break; case 0x1A: /* Core i7 */ - auto_arch = arch_core2 | arch_feature_p6_insn; + auto_arch = cpu_core2_generic; break; case 0x1C: /* Atom */ - auto_arch = arch_atom; + auto_arch = cpu_atom_generic; break; case 0x1D: /* Xeon MP */ - auto_arch = arch_core2 | arch_feature_p6_insn; + auto_arch = cpu_core2_generic; break; default: /* unknown */ @@ -653,14 +651,15 @@ static cpu_support auto_detect_Intel(x86_cpu_info_t const *info) return auto_arch; } -static cpu_support auto_detect_AMD(x86_cpu_info_t const *info) { - cpu_support auto_arch = cpu_generic; +static cpu_arch_features auto_detect_AMD(x86_cpu_info_t const *info) +{ + cpu_arch_features auto_arch = cpu_generic; unsigned family, model; if (info->cpu_family == 0x0F) { - family = (info->cpu_ext_family << 4) | info->cpu_family; - model = (info->cpu_ext_model << 4) | info->cpu_model; + family = info->cpu_ext_family + info->cpu_family; + model = (info->cpu_ext_model << 4) | info->cpu_model; } else { family = info->cpu_family; model = info->cpu_model; @@ -668,7 +667,7 @@ static cpu_support auto_detect_AMD(x86_cpu_info_t const *info) { switch (family) { case 0x04: - auto_arch = arch_i486; + auto_arch = cpu_i486; break; case 0x05: switch (model) { @@ -676,21 +675,21 @@ static cpu_support auto_detect_AMD(x86_cpu_info_t const *info) { case 0x01: /* K5 Model 1 */ case 0x02: /* K5 Model 2 */ case 0x03: /* K5 Model 3 */ - auto_arch = arch_pentium; + auto_arch = cpu_pentium; break; case 0x06: /* K6 Model 6 */ case 0x07: /* K6 Model 7 */ case 0x08: /* K6-2 Model 8 */ case 0x09: /* K6-III Model 9 */ case 0x0D: /* K6-2+ or K6-III+ */ - auto_arch = arch_k6; + auto_arch = cpu_k6_generic; break; case 0x0A: /* Geode LX */ - auto_arch = arch_geode; + auto_arch = cpu_geode_generic; break; default: /* unknown K6 */ - auto_arch = arch_k6; + auto_arch = cpu_k6_generic; break; } break; @@ -704,19 +703,20 @@ static cpu_support auto_detect_AMD(x86_cpu_info_t const *info) { case 0x07: /* Mobile Duron Model 7 */ case 0x08: /* Athlon (TH/AP core) including Geode NX */ case 0x0A: /* Athlon (BT core) */ - auto_arch = arch_athlon | arch_feature_p6_insn; - break; - default: - /* unknown K7 */ - auto_arch = arch_athlon | arch_feature_p6_insn;; + default: /* unknown K7 */ + auto_arch = cpu_athlon_generic; break; } break; case 0x0F: - auto_arch = arch_k8 | arch_feature_p6_insn;; + auto_arch = cpu_k8_generic; break; - case 0x1F: - auto_arch = arch_k10 | arch_feature_p6_insn;; + case 0x10: + case 0x11: /* AMD Family 11h */ + case 0x12: /* AMD Family 12h */ + case 0x14: /* AMD Family 14h */ + case 0x15: /* AMD Family 15h */ + auto_arch = cpu_k10_generic; break; default: /* unknown */ @@ -739,18 +739,32 @@ typedef union { static void x86_cpuid(cpuid_registers *regs, unsigned level) { #if defined(__GNUC__) +# if defined(__PIC__) && !defined(__amd64) // GCC cannot handle EBX in PIC + __asm ( + "pushl %%ebx\n\t" + "cpuid\n\t" + "movl %%ebx, %1\n\t" + "popl %%ebx" + : "=a" (regs->r.eax), "=r" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx) + : "a" (level) + ); +# else __asm ("cpuid\n\t" : "=a" (regs->r.eax), "=b" (regs->r.ebx), "=c" (regs->r.ecx), "=d" (regs->r.edx) : "a" (level) ); +# endif #elif defined(_MSC_VER) __cpuid(regs->bulk, level); +#else +# error CPUID is missing #endif } -static int x86_toogle_cpuid(void) +static bool x86_toogle_cpuid(void) { - unsigned eflags_before = 0, eflags_after = 0; + unsigned eflags_before = 0; + unsigned eflags_after = 0; #if defined(__GNUC__) #ifdef __i386__ @@ -767,8 +781,7 @@ static int x86_toogle_cpuid(void) : "=r" (eflags_before), "=r" (eflags_after) :: "cc" ); #else - /* cpuid always available on 64bit */ - return true; + eflags_after = 0x00200000; #endif #elif defined(_MSC_VER) #if defined(_M_IX86) @@ -784,7 +797,7 @@ static int x86_toogle_cpuid(void) mov eflags_after, eax } #else - return true; + eflags_after = 0x00200000; #endif #endif return (eflags_before ^ eflags_after) & 0x00200000; @@ -792,18 +805,16 @@ static int x86_toogle_cpuid(void) static void autodetect_arch(void) { - cpu_support auto_arch = cpu_generic; + cpu_arch_features auto_arch = cpu_generic; /* We use the cpuid instruction to detect the CPU features */ if (x86_toogle_cpuid()) { cpuid_registers regs; - unsigned highest_level; char vendorid[13]; x86_cpu_info_t cpu_info; /* get vendor ID */ x86_cpuid(®s, 0); - highest_level = regs.r.eax; memcpy(&vendorid[0], ®s.r.ebx, 4); memcpy(&vendorid[4], ®s.r.edx, 4); memcpy(&vendorid[8], ®s.r.ecx, 4); @@ -827,7 +838,7 @@ static void autodetect_arch(void) } else if (0 == strcmp(vendorid, "AuthenticAMD")) { auto_arch = auto_detect_AMD(&cpu_info); } else if (0 == strcmp(vendorid, "Geode by NSC")) { - auto_arch = arch_geode; + auto_arch = cpu_geode_generic; } if (cpu_info.edx_features & CPUID_FEAT_EDX_CMOV) @@ -856,6 +867,11 @@ static void autodetect_arch(void) } #endif /* NATIVE_X86 */ +static bool flags(cpu_arch_features features, cpu_arch_features flags) +{ + return (features & flags) != 0; +} + void ia32_setup_cg_config(void) { ia32_code_gen_config_t *const c = &ia32_cg_config; @@ -871,39 +887,39 @@ void ia32_setup_cg_config(void) c->optimize_size = opt_size != 0; /* on newer intel cpus mov, pop is often faster than leave although it has a * longer opcode */ - c->use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size; + c->use_leave = flags(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size; /* P4s don't like inc/decs because they only partially write the flags * register which produces false dependencies */ - c->use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size; - c->use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2); - c->use_ffreep = FLAGS(opt_arch, arch_athlon_plus); - c->use_ftst = !FLAGS(arch, arch_feature_p6_insn); + c->use_incdec = !flags(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size; + c->use_softfloat = (fpu_arch & IA32_FPU_ARCH_SOFTFLOAT) != 0; + c->use_sse2 = (fpu_arch & IA32_FPU_ARCH_SSE2) != 0 && flags(arch, arch_feature_sse2); + c->use_ffreep = flags(opt_arch, arch_athlon_plus); /* valgrind can't cope with femms yet and the usefulness of the optimization * is questionable anyway */ #if 0 - c->use_femms = FLAGS(opt_arch, arch_athlon_plus) && - FLAGS(arch, arch_feature_mmx | arch_all_amd); + c->use_femms = flags(opt_arch, arch_athlon_plus) && + flags(arch, arch_feature_mmx | arch_all_amd); #else c->use_femms = 0; #endif - c->use_fucomi = FLAGS(arch, arch_feature_p6_insn); - c->use_cmov = FLAGS(arch, arch_feature_cmov); - c->use_modeD_moves = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode); - c->use_add_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size; - c->use_add_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size; - c->use_sub_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size; - c->use_sub_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size; - c->use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size; - c->use_pxor = FLAGS(opt_arch, arch_netburst); - c->use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size; - c->use_short_sex_eax = !FLAGS(opt_arch, arch_k6) && !opt_size; - c->use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size; - c->use_bt = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size; - c->use_fisttp = FLAGS(opt_arch & arch, arch_feature_sse3); - c->use_sse_prefetch = FLAGS(arch, (arch_feature_3DNowE | arch_feature_sse1)); - c->use_3dnow_prefetch = FLAGS(arch, arch_feature_3DNow); - c->use_popcnt = FLAGS(arch, arch_feature_popcnt); - c->use_i486 = (arch & arch_mask) >= arch_i486; + c->use_fucomi = flags(arch, arch_feature_p6_insn); + c->use_cmov = flags(arch, arch_feature_cmov); + c->use_modeD_moves = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode); + c->use_add_esp_4 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size; + c->use_add_esp_8 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size; + c->use_sub_esp_4 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size; + c->use_sub_esp_8 = flags(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size; + c->use_imul_mem_imm32 = !flags(opt_arch, arch_k8 | arch_k10) || opt_size; + c->use_pxor = flags(opt_arch, arch_netburst); + c->use_mov_0 = flags(opt_arch, arch_k6) && !opt_size; + c->use_short_sex_eax = !flags(opt_arch, arch_k6) && !opt_size; + c->use_pad_return = flags(opt_arch, arch_athlon_plus) && !opt_size; + c->use_bt = flags(opt_arch, arch_core2 | arch_athlon_plus) || opt_size; + c->use_fisttp = flags(opt_arch & arch, arch_feature_sse3); + c->use_sse_prefetch = flags(arch, (arch_feature_3DNowE | arch_feature_sse1)); + c->use_3dnow_prefetch = flags(arch, arch_feature_3DNow); + c->use_popcnt = flags(arch, arch_feature_popcnt); + c->use_bswap = (arch & arch_mask) >= arch_i486; c->optimize_cc = opt_cc; c->use_unsafe_floatconv = opt_unsafe_floatconv; c->emit_machcode = emit_machcode; @@ -913,7 +929,7 @@ void ia32_setup_cg_config(void) c->label_alignment_max_skip = arch_costs->label_alignment_max_skip; c->label_alignment_factor = - FLAGS(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 : + flags(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 : opt_arch & arch_all_amd ? 3 : 2; }