X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32_t.h;h=f113001d6beb07483c7f37d24fdd379d9236c058;hb=9ed9f4495b1688416395fb6b8e575a77df52ebf1;hp=f3c20997972db7645cdba26f468c89dae6e82db8;hpb=97c79556e25a27333a20f9f8d1094e7b7b3792ec;p=libfirm diff --git a/ir/be/ia32/bearch_ia32_t.h b/ir/be/ia32/bearch_ia32_t.h index f3c209979..f113001d6 100644 --- a/ir/be/ia32/bearch_ia32_t.h +++ b/ir/be/ia32/bearch_ia32_t.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -49,70 +49,6 @@ typedef enum ia32_optimize_t ia32_optimize_t; typedef enum cpu_support cpu_support; typedef enum fp_support fp_support; -/** - * Bitmask for the backend optimization settings. - */ -enum ia32_optimize_t { - IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */ - IA32_OPT_DOAM = 2, /**< do address mode optimizations */ - IA32_OPT_LEA = 4, /**< optimize address calculations into LEAs */ - IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */ - IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */ - IA32_OPT_PUSHARGS = 32, /**< create pushs for function argument passing */ -}; - -/** - * Architectures. Clustered for easier macro implementation, - * do not change. - */ -enum cpu_support { - arch_i386, /**< i386 */ - arch_i486, /**< i486 */ - arch_pentium, /**< Pentium */ - arch_pentium_pro, /**< Pentium Pro */ - arch_pentium_mmx, /**< Pentium MMX */ - arch_pentium_2, /**< Pentium II */ - arch_pentium_3, /**< Pentium III */ - arch_pentium_4, /**< Pentium IV */ - arch_pentium_m, /**< Pentium M */ - arch_core, /**< Core */ - arch_k6, /**< K6 */ - arch_athlon, /**< Athlon */ - arch_athlon_64, /**< Athlon64 */ - arch_opteron, /**< Opteron */ -}; - -/** checks for l <= x <= h */ -#define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l))) - -/** returns true if it's Intel architecture */ -#define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core) - -/** returns true if it's AMD architecture */ -#define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron) - -#define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \ - _IN_RANGE((x), arch_athlon, arch_opteron)) - -/** floating point support */ -enum fp_support { - fp_none, /**< no floating point instructions are used */ - fp_x87, /**< use x87 instructions */ - fp_sse2 /**< use SSE2 instructions */ -}; - -/** Sets the used flag to the current floating point architecture. */ -#define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind) - -/** Returns non-zero if the current floating point architecture is SSE2. */ -#define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2) - -/** Returns non-zero if the current floating point architecture is x87. */ -#define USE_x87(cg) ((cg)->fp_kind == fp_x87) - -/** Sets the flag to enforce x87 simulation. */ -#define FORCE_x87(cg) ((cg)->force_sim = 1) - typedef struct ia32_isa_t ia32_isa_t; typedef struct ia32_code_gen_t ia32_code_gen_t; typedef struct ia32_irn_ops_t ia32_irn_ops_t; @@ -129,23 +65,20 @@ struct ia32_code_gen_t { ia32_isa_t *isa; /**< for fast access to the isa object */ be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */ ir_node **blk_sched; /**< an array containing the scheduled blocks */ - ia32_optimize_t opt; /**< contains optimization information */ - int arch; /**< instruction architecture */ - int opt_arch; /**< optimize for architecture */ - char fp_kind; /**< floating point kind */ - char used_fp; /**< which floating point unit used in this graph */ - char force_sim; /**< set to 1 if x87 simulation should be enforced */ - char dump; /**< set to 1 if graphs should be dumped */ - ir_node *unknown_gp; /**< unique Unknown_GP node */ - ir_node *unknown_vfp; /**< unique Unknown_VFP node */ - ir_node *unknown_xmm; /**< unique Unknown_XMM node */ - ir_node *noreg_gp; /**< unique NoReg_GP node */ - ir_node *noreg_vfp; /**< unique NoReg_VFP node */ - ir_node *noreg_xmm; /**< unique NoReg_XMM node */ - - ir_node *fpu_trunc_mode; /**< truncate fpu mode */ - - struct obstack *obst; + unsigned do_x87_sim:1; /**< set to 1 if x87 simulation should be enforced */ + unsigned dump:1; /**< set to 1 if graphs should be dumped */ + unsigned gprof:1; /**< set to 1 grof profiling is in use */ + ir_node *unknown_gp; /**< unique Unknown_GP node */ + ir_node *unknown_vfp; /**< unique Unknown_VFP node */ + ir_node *unknown_xmm; /**< unique Unknown_XMM node */ + ir_node *noreg_gp; /**< unique NoReg_GP node */ + ir_node *noreg_vfp; /**< unique NoReg_VFP node */ + ir_node *noreg_xmm; /**< unique NoReg_XMM node */ + + ir_node *fpu_trunc_mode; /**< truncate fpu mode */ + ir_node *get_eip; /**< get eip node */ + + struct obstack *obst; }; /** @@ -153,16 +86,11 @@ struct ia32_code_gen_t { */ struct ia32_isa_t { arch_isa_t arch_isa; /**< must be derived from arch_isa_t */ - be_emit_env_t emit; pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */ pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */ pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */ pmap *types; /**< A map of modes to primitive types */ pmap *tv_ent; /**< A map of entities that store const tarvals */ - ia32_optimize_t opt; /**< contains optimization information */ - int arch; /**< instruction architecture */ - int opt_arch; /**< optimize for architecture */ - int fp_kind; /**< floating point kind */ ia32_code_gen_t *cg; /**< the current code generator */ const be_machine_t *cpu; /**< the abstract machine */ #ifndef NDEBUG @@ -175,17 +103,29 @@ struct ia32_irn_ops_t { ia32_code_gen_t *cg; }; +/** + * A helper type collecting needed info for IA32 intrinsic lowering. + */ struct ia32_intrinsic_env_t { - ir_graph *irg; /**< the irg, these entities belong to */ - ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */ - ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */ - ir_entity *ll_d_conv; /**< entity for converts ll -> d */ - ir_entity *d_ll_conv; /**< entity for converts d -> ll */ + ia32_isa_t *isa; /**< the isa object */ + ir_graph *irg; /**< the irg, these entities belong to */ + ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */ + ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */ + ir_entity *ll_d_conv; /**< entity for converts ll -> d */ + ir_entity *d_ll_conv; /**< entity for converts d -> ll */ + ir_entity *divdi3; /**< entity for __divdi3 library call */ + ir_entity *moddi3; /**< entity for __moddi3 library call */ + ir_entity *udivdi3; /**< entity for __udivdi3 library call */ + ir_entity *umoddi3; /**< entity for __umoddi3 library call */ + tarval *u64_bias; /**< bias value for conversion from float to unsigned 64 */ }; -/** mode for the floating point control word */ +/** The mode for the floating point control word. */ extern ir_mode *mode_fpcw; +/** The current code generator. */ +extern ia32_code_gen_t *ia32_current_cg; + /** * Returns the unique per irg GP NoReg node. */ @@ -202,12 +142,7 @@ ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg); ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg); /** - * Returns the unique per irg FP NoReg node. - */ -ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg); - -/** - * Returns the uniqure per irg FPU truncation mode node. + * Returns the unique per irg FPU truncation mode node. */ ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);