X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32_t.h;h=110f2394ab2aa03fb1efb97d67173f9b58d4594f;hb=70141f1b87d770fc18c98948f1049dec758ff020;hp=f8bbe486452849e573f7d6cb41a6d0739cee9098;hpb=a671c6874460f3feada60125a0fd95b9427fac7d;p=libfirm diff --git a/ir/be/ia32/bearch_ia32_t.h b/ir/be/ia32/bearch_ia32_t.h index f8bbe4864..110f2394a 100644 --- a/ir/be/ia32/bearch_ia32_t.h +++ b/ir/be/ia32/bearch_ia32_t.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -26,8 +26,7 @@ #ifndef FIRM_BE_IA32_BEARCH_IA32_T_H #define FIRM_BE_IA32_BEARCH_IA32_T_H -#include "firm_config.h" - +#include "config.h" #include "pmap.h" #include "debug.h" #include "ia32_nodes_attr.h" @@ -41,7 +40,7 @@ #ifdef NDEBUG #define SET_IA32_ORIG_NODE(n, o) #else /* ! NDEBUG */ -#define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o); +#define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o) #endif /* NDEBUG */ /* some typedefs */ @@ -49,68 +48,6 @@ typedef enum ia32_optimize_t ia32_optimize_t; typedef enum cpu_support cpu_support; typedef enum fp_support fp_support; -/** - * Bitmask for the backend optimization settings. - */ -enum ia32_optimize_t { - IA32_OPT_INCDEC = 1 << 0, /**< optimize add/sub 1/-1 to inc/dec */ - IA32_OPT_CC = 1 << 1, -}; - -/** - * Architectures. Clustered for easier macro implementation, - * do not change. - */ -enum cpu_support { - arch_i386, - arch_i486, - arch_pentium, - arch_pentium_pro, - arch_pentium_mmx, - arch_pentium_2, - arch_pentium_3, - arch_pentium_4, - arch_pentium_m, - arch_core, - arch_k6, - arch_athlon, - arch_athlon_xp, - arch_athlon_64, - arch_opteron, - arch_generic -}; - -/** checks for l <= x <= h */ -#define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l))) - -/** returns true if it's Intel architecture */ -#define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core) - -/** returns true if it's AMD architecture */ -#define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron) - -/** return true if it's a Athlon/Opteron */ -#define ARCH_ATHLON(x) _IN_RANGE((x), arch_athlon, arch_opteron) - -/** return true if the CPU has MMX support */ -#define ARCH_MMX(x) _IN_RANGE((x), arch_pentium_mmx, arch_opteron) - -#define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \ - _IN_RANGE((x), arch_athlon, arch_opteron)) - -/** floating point support */ -enum fp_support { - fp_none, /**< no floating point instructions are used */ - fp_x87, /**< use x87 instructions */ - fp_sse2 /**< use SSE2 instructions */ -}; - -/** Returns non-zero if the current floating point architecture is SSE2. */ -#define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2) - -/** Returns non-zero if the current floating point architecture is x87. */ -#define USE_x87(cg) ((cg)->fp_kind == fp_x87) - typedef struct ia32_isa_t ia32_isa_t; typedef struct ia32_code_gen_t ia32_code_gen_t; typedef struct ia32_irn_ops_t ia32_irn_ops_t; @@ -122,43 +59,36 @@ typedef struct ia32_intrinsic_env_t ia32_intrinsic_env_t; struct ia32_code_gen_t { const arch_code_generator_if_t *impl; /**< implementation */ ir_graph *irg; /**< current irg */ - const arch_env_t *arch_env; /**< the arch env */ set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */ ia32_isa_t *isa; /**< for fast access to the isa object */ be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */ ir_node **blk_sched; /**< an array containing the scheduled blocks */ - ia32_optimize_t opt; /**< contains optimization information */ - int arch; /**< instruction architecture */ - int opt_arch; /**< optimize for architecture */ - char fp_kind; /**< floating point kind */ - char do_x87_sim; /**< set to 1 if x87 simulation should be enforced */ - char dump; /**< set to 1 if graphs should be dumped */ - ir_node *unknown_gp; /**< unique Unknown_GP node */ - ir_node *unknown_vfp; /**< unique Unknown_VFP node */ - ir_node *unknown_xmm; /**< unique Unknown_XMM node */ - ir_node *noreg_gp; /**< unique NoReg_GP node */ - ir_node *noreg_vfp; /**< unique NoReg_VFP node */ - ir_node *noreg_xmm; /**< unique NoReg_XMM node */ - - ir_node *fpu_trunc_mode; /**< truncate fpu mode */ - - struct obstack *obst; + unsigned do_x87_sim:1; /**< set to 1 if x87 simulation should be enforced */ + unsigned dump:1; /**< set to 1 if graphs should be dumped */ + unsigned gprof:1; /**< set to 1 grof profiling is in use */ + ir_node *unknown_gp; /**< unique Unknown_GP node */ + ir_node *unknown_vfp; /**< unique Unknown_VFP node */ + ir_node *unknown_xmm; /**< unique Unknown_XMM node */ + ir_node *noreg_gp; /**< unique NoReg_GP node */ + ir_node *noreg_vfp; /**< unique NoReg_VFP node */ + ir_node *noreg_xmm; /**< unique NoReg_XMM node */ + + ir_node *fpu_trunc_mode; /**< truncate fpu mode */ + ir_node *get_eip; /**< get eip node */ + + struct obstack *obst; }; /** * IA32 ISA object */ struct ia32_isa_t { - arch_isa_t arch_isa; /**< must be derived from arch_isa_t */ + arch_env_t arch_env; /**< must be derived from arch_env_t */ pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */ pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */ pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */ pmap *types; /**< A map of modes to primitive types */ pmap *tv_ent; /**< A map of entities that store const tarvals */ - ia32_optimize_t opt; /**< contains optimization information */ - int arch; /**< instruction architecture */ - int opt_arch; /**< optimize for architecture */ - int fp_kind; /**< floating point kind */ ia32_code_gen_t *cg; /**< the current code generator */ const be_machine_t *cpu; /**< the abstract machine */ #ifndef NDEBUG @@ -166,28 +96,34 @@ struct ia32_isa_t { #endif /* NDEBUG */ }; -struct ia32_irn_ops_t { - const arch_irn_ops_if_t *impl; - ia32_code_gen_t *cg; -}; - /** * A helper type collecting needed info for IA32 intrinsic lowering. */ struct ia32_intrinsic_env_t { ia32_isa_t *isa; /**< the isa object */ ir_graph *irg; /**< the irg, these entities belong to */ - ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */ - ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */ - ir_entity *ll_d_conv; /**< entity for converts ll -> d */ - ir_entity *d_ll_conv; /**< entity for converts d -> ll */ ir_entity *divdi3; /**< entity for __divdi3 library call */ ir_entity *moddi3; /**< entity for __moddi3 library call */ ir_entity *udivdi3; /**< entity for __udivdi3 library call */ ir_entity *umoddi3; /**< entity for __umoddi3 library call */ - tarval *u64_bias; /**< bias value for conversion from float to unsigned 64 */ }; +typedef enum transformer_t { + TRANSFORMER_DEFAULT, +#ifdef FIRM_GRGEN_BE + TRANSFORMER_PBQP, + TRANSFORMER_RAND +#endif +} transformer_t; + +#ifdef FIRM_GRGEN_BE +/** The selected transformer. */ +extern transformer_t be_transformer; + +#else +#define be_transformer TRANSFORMER_DEFAULT +#endif + /** The mode for the floating point control word. */ extern ir_mode *mode_fpcw; @@ -209,20 +145,16 @@ ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg); ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg); ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg); -/** - * Returns the unique per irg FP NoReg node. - */ -ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg); - /** * Returns the unique per irg FPU truncation mode node. */ ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg); /** - * Returns gp_noreg or fp_noreg, depending on input requirements. + * Split instruction with source AM into Load and separate instruction. + * @return result of the Load */ -ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos); +ir_node *turn_back_am(ir_node *node); /** * Maps all intrinsic calls that the backend support