X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32_t.h;h=08f9a340a4553d94002cf6ea0a3c287922f4e09e;hb=bed34693123e2d3567117c2abee7d23131c91226;hp=903118df25c79b6b83861834d89d7067b0d2af2e;hpb=08fe790a5784b31964a8783f6af1d14d62c366c4;p=libfirm diff --git a/ir/be/ia32/bearch_ia32_t.h b/ir/be/ia32/bearch_ia32_t.h index 903118df2..08f9a340a 100644 --- a/ir/be/ia32/bearch_ia32_t.h +++ b/ir/be/ia32/bearch_ia32_t.h @@ -3,6 +3,7 @@ #include "firm_config.h" +#include "pmap.h" #include "debug.h" #include "bearch_ia32.h" #include "ia32_nodes_attr.h" @@ -20,39 +21,64 @@ /** * Bitmask for the backend optimization settings. */ -typedef struct _ia32_optimize_t { - unsigned incdec : 1; /**< optimize add/sub 1/-1 to inc/dec */ - unsigned doam : 1; /**< do address mode optimizations */ - unsigned placecnst : 1; /**< place constants in the blocks where they are used */ - unsigned immops : 1; /**< create operations with immediate operands */ - unsigned extbb : 1; /**< do extended basic block scheduling */ +typedef enum _ia32_optimize_t { + IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */ + IA32_OPT_DOAM = 2, /**< do address mode optimizations */ + IA32_OPT_LEA = 4, /**< optimize address caluclations into LEAs */ + IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */ + IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */ + IA32_OPT_EXTBB = 32, /**< do extended basic block scheduling */ } ia32_optimize_t; -/** architectures */ +/** + * Architectures. Clustered for easier macro implementation, + * do not change. + */ typedef enum cpu_support { - arch_i386, /**< i386 */ - arch_i486, /**< i486 */ - arch_pentium, /**< Pentium */ - arch_pentium_pro, /**< Pentium Pro */ - arch_pentium_mmx, /**< Pentium MMX */ - arch_pentium_2, /**< Pentium II */ - arch_pentium_3, /**< Pentium III */ - arch_pentium_4, /**< Pentium IV */ - arch_pentium_m, /**< Pentium M */ - arch_core, /**< Core */ - arch_k6, /**< K6 */ - arch_athlon, /**< Athlon */ - arch_athlon_64, /**< Athlon64 */ - arch_opteron, /**< Opteron */ + arch_i386, /**< i386 */ + arch_i486, /**< i486 */ + arch_pentium, /**< Pentium */ + arch_pentium_pro, /**< Pentium Pro */ + arch_pentium_mmx, /**< Pentium MMX */ + arch_pentium_2, /**< Pentium II */ + arch_pentium_3, /**< Pentium III */ + arch_pentium_4, /**< Pentium IV */ + arch_pentium_m, /**< Pentium M */ + arch_core, /**< Core */ + arch_k6, /**< K6 */ + arch_athlon, /**< Athlon */ + arch_athlon_64, /**< Athlon64 */ + arch_opteron, /**< Opteron */ } cpu_support; +/** checks for l <= x <= h */ +#define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l))) + +/** returns true if it's Intel architecture */ +#define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core) + +/** returns true if it's AMD architecture */ +#define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron) + +#define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \ + _IN_RANGE((x), arch_athlon, arch_opteron)) + /** floating point support */ typedef enum fp_support { fp_none, /**< no floating point instructions are used */ - fp_x87, /**< use x87 instructions */ - fp_sse2 /**< use SSE2 instructions */ + fp_x87, /**< use x87 instructions */ + fp_sse2 /**< use SSE2 instructions */ } fp_support; +/** Sets the used flag to the current floating point architecture. */ +#define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind) + +/** Returns non-zero if the current floating point architecture is SSE2. */ +#define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2) + +/** Returns non-zero if the current floating point architecture is x87. */ +#define USE_x87(cg) ((cg)->fp_kind == fp_x87) + typedef struct _ia32_isa_t ia32_isa_t; /** @@ -63,11 +89,12 @@ typedef struct _ia32_code_gen_t { ir_graph *irg; /**< current irg */ const arch_env_t *arch_env; /**< the arch env */ set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */ - int emit_decls; /**< flag indicating if decls were already emitted */ ia32_isa_t *isa; /**< for fast access to the isa object */ const be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */ ir_node **blk_sched; /**< an array containing the scheduled blocks */ ia32_optimize_t opt; /**< contains optimization information */ + entity *fp_to_gp; /**< allocated entity for fp to gp conversion */ + entity *gp_to_fp; /**< allocated entity for gp to fp conversion */ int arch; /**< instruction architecture */ int opt_arch; /**< optimize for architecture */ int fp_kind; /**< floating point kind */ @@ -79,15 +106,12 @@ typedef struct _ia32_code_gen_t { * IA32 ISA object */ struct _ia32_isa_t { - const arch_isa_if_t *impl; - const arch_register_t *sp; /**< The stack pointer register. */ - const arch_register_t *bp; /**< The base pointer register. */ - const int stack_dir; /**< -1 for decreasing, 1 for increasing. */ - int num_codegens; /**< The number of code generator objects created so far */ + arch_isa_t arch_isa; /**< must be derived from arch_isa_t */ pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */ pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */ pmap *types; /**< A map of modes to primitive types */ pmap *tv_ent; /**< A map of entities that store const tarvals */ + ia32_optimize_t opt; /**< contains optimization information */ int arch; /**< instruction architecture */ int opt_arch; /**< optimize for architecture */ int fp_kind; /**< floating point kind */