X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=fdf9abf0473b6ecd45776a093a77cf34fba6ab52;hb=d51bc5156f1a0c202be8b40c4dd7667bd3a6933e;hp=1db15bf5b0a66ff46c95b909ebf5f9d9d55b755b;hpb=577e990a5c85673d69ff5eee46d438be2bf50f44;p=libfirm

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 1db15bf5b..fdf9abf04 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -410,15 +410,16 @@ static void ia32_abi_dont_save_regs(void *self, pset *s)
 /**
  * Generate the routine prologue.
  *
- * @param self    The callback object.
- * @param mem     A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param self       The callback object.
+ * @param mem        A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map    A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
  *
- * @return        The register which shall be used as a stack frame base.
+ * @return           The register which shall be used as a stack frame base.
  *
  * All nodes which define registers in @p reg_map must keep @p reg_map current.
  */
-static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
+static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
 {
 	ia32_abi_env_t   *env      = self;
 	ia32_code_gen_t  *cg       = ia32_current_cg;
@@ -444,6 +445,9 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
 		arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
 		set_ia32_flags(push, arch_irn_flags_ignore);
 
+		/* this modifies the stack bias, because we pushed 32bit */
+		*stack_bias -= 4;
+
 		/* move esp to ebp */
 		curr_bp  = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
 		be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
@@ -493,7 +497,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
 			ir_node *leave;
 
 			/* leave */
-			leave   = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
+			leave   = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
 			set_ia32_flags(leave, arch_irn_flags_ignore);
 			curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
 			curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
@@ -967,14 +971,13 @@ static void ia32_prepare_graph(void *self) {
 
 #ifdef FIRM_GRGEN_BE
 		case TRANSFORMER_PBQP:
+		case TRANSFORMER_RAND:
 			// disable CSE, because of two-step node-construction
 			set_opt_cse(0);
 
 			/* transform nodes into assembler instructions by PBQP magic */
 			ia32_transform_graph_by_pbqp(cg);
 
-			if (cg->dump)
-				be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
 			set_opt_cse(1);
 			break;
 #endif
@@ -1026,6 +1029,8 @@ static void turn_back_am(ir_node *node)
 	load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
 
 	ia32_copy_am_attrs(load, node);
+	if (is_ia32_is_reload(node))
+		set_ia32_is_reload(load);
 	set_irn_n(node, n_ia32_mem, new_NoMem());
 
 	switch (get_ia32_am_arity(node)) {
@@ -1114,8 +1119,6 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
 
 /**
  * Called before the register allocator.
- * Calculate a block schedule here. We need it for the x87
- * simulator and the emitter.
  */
 static void ia32_before_ra(void *self) {
 	ia32_code_gen_t *cg = self;
@@ -1169,6 +1172,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
 	set_ia32_ls_mode(new_op, spillmode);
 	set_ia32_frame_ent(new_op, ent);
 	set_ia32_use_frame(new_op);
+	set_ia32_is_reload(new_op);
 
 	DBG_OPT_RELOAD2LD(node, new_op);
 
@@ -1239,6 +1243,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
 	set_ia32_ls_mode(store, mode);
 	set_ia32_frame_ent(store, ent);
 	set_ia32_use_frame(store);
+	set_ia32_is_spill(store);
 	SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
 	DBG_OPT_SPILL2ST(node, store);
 
@@ -1658,7 +1663,7 @@ static ia32_isa_t ia32_isa_template = {
 		&ia32_gp_regs[REG_ESP],  /* stack pointer register */
 		&ia32_gp_regs[REG_EBP],  /* base pointer register */
 		-1,                      /* stack direction */
-		4,                       /* power of two stack alignment, 2^4 == 16 */
+		2,                       /* power of two stack alignment, 2^2 == 4 */
 		NULL,                    /* main environment */
 		7,                       /* costs for a spill instruction */
 		5,                       /* costs for a reload instruction */
@@ -2117,6 +2122,13 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
 	return NULL;
 }
 
+static void ia32_mark_remat(const void *self, ir_node *node) {
+	(void) self;
+	if (is_ia32_irn(node)) {
+		set_ia32_is_remat(node);
+	}
+}
+
 /**
  * Allows or disallows the creation of Psi nodes for the given Phi nodes.
  * @return 1 if allowed, 0 otherwise
@@ -2325,6 +2337,7 @@ static const lc_opt_enum_int_items_t transformer_items[] = {
 	{ "default", TRANSFORMER_DEFAULT },
 #ifdef FIRM_GRGEN_BE
 	{ "pbqp",    TRANSFORMER_PBQP    },
+	{ "random",  TRANSFORMER_RAND    },
 #endif
 	{ NULL,      0                   }
 };
@@ -2356,6 +2369,7 @@ const arch_isa_if_t ia32_isa_if = {
 	ia32_get_allowed_execution_units,
 	ia32_get_machine,
 	ia32_get_irg_list,
+	ia32_mark_remat,
 	ia32_parse_asm_constraint,
 	ia32_is_valid_clobber
 };