X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=f7bbde804d260d12e8f70a9963e05c2005b7e9b9;hb=4b33054acaa27b6fca74713bb0e1e79e6af3d9c4;hp=6574f4f0c591c13f54f51b61c6040688b4f71e04;hpb=affee2db04186e2f55072736a59abb9b72781e89;p=libfirm

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 6574f4f0c..f7bbde804 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -42,6 +42,7 @@
 #include "irgopt.h"
 #include "irbitset.h"
 #include "irgopt.h"
+#include "irdump.h"
 #include "pdeq.h"
 #include "pset.h"
 #include "debug.h"
@@ -50,12 +51,13 @@
 #include "irtools.h"
 #include "iroptimize.h"
 #include "instrument.h"
+#include "iropt_t.h"
 
 #include "../beabi.h"
-#include "../beirg_t.h"
-#include "../benode_t.h"
+#include "../beirg.h"
+#include "../benode.h"
 #include "../belower.h"
-#include "../besched_t.h"
+#include "../besched.h"
 #include "be.h"
 #include "../be_t.h"
 #include "../beirgmod.h"
@@ -69,6 +71,7 @@
 #include "../bestate.h"
 #include "../beflags.h"
 #include "../betranshlp.h"
+#include "../belistsched.h"
 
 #include "bearch_ia32_t.h"
 
@@ -95,12 +98,17 @@ transformer_t be_transformer = TRANSFORMER_DEFAULT;
 
 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
 
-/* TODO: ugly */
-static set *cur_reg_set = NULL;
-
 ir_mode         *mode_fpcw       = NULL;
 ia32_code_gen_t *ia32_current_cg = NULL;
 
+/** The current omit-fp state */
+static unsigned ia32_curr_fp_ommitted  = 0;
+static ir_type *omit_fp_between_type   = NULL;
+static ir_type *between_type           = NULL;
+static ir_entity *old_bp_ent           = NULL;
+static ir_entity *ret_addr_ent         = NULL;
+static ir_entity *omit_fp_ret_addr_ent = NULL;
+
 /**
  * The environment for the intrinsic mapping.
  */
@@ -116,13 +124,16 @@ static ia32_intrinsic_env_t intrinsic_env = {
 
 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
 
+/**
+ * Used to create per-graph unique pseudo nodes.
+ */
 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
                                     create_const_node_func func,
                                     const arch_register_t* reg)
 {
 	ir_node *block, *res;
 
-	if(*place != NULL)
+	if (*place != NULL)
 		return *place;
 
 	block = get_irg_start_block(cg->irg);
@@ -130,44 +141,30 @@ static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
 	arch_set_irn_register(res, reg);
 	*place = res;
 
-	add_irn_dep(get_irg_end(cg->irg), res);
-	/* add_irn_dep(get_irg_start(cg->irg), res); */
-
 	return res;
 }
 
 /* Creates the unique per irg GP NoReg node. */
-ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
+ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
+{
 	return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
 	                    &ia32_gp_regs[REG_GP_NOREG]);
 }
 
-ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
+ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
+{
 	return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
 	                    &ia32_vfp_regs[REG_VFP_NOREG]);
 }
 
-ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
+ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
+{
 	return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
 	                    &ia32_xmm_regs[REG_XMM_NOREG]);
 }
 
-ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
-	return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
-	                    &ia32_gp_regs[REG_GP_UKNWN]);
-}
-
-ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
-	return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
-	                    &ia32_vfp_regs[REG_VFP_UKNWN]);
-}
-
-ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
-	return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
-	                    &ia32_xmm_regs[REG_XMM_UKNWN]);
-}
-
-ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
+ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
+{
 	return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
                         &ia32_fp_cw_regs[REG_FPCW]);
 }
@@ -191,72 +188,20 @@ static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int
 	}
 }
 
-/**************************************************
- *                         _ _              _  __
- *                        | | |            (_)/ _|
- *  _ __ ___  __ _    __ _| | | ___   ___   _| |_
- * | '__/ _ \/ _` |  / _` | | |/ _ \ / __| | |  _|
- * | | |  __/ (_| | | (_| | | | (_) | (__  | | |
- * |_|  \___|\__, |  \__,_|_|_|\___/ \___| |_|_|
- *            __/ |
- *           |___/
- **************************************************/
 
-/**
- * Return register requirements for an ia32 node.
- * If the node returns a tuple (mode_T) then the proj's
- * will be asked for this information.
- */
-static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
-													   int pos)
+static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
+		const ir_node *node, int pos)
 {
-	ir_mode *mode = get_irn_mode(node);
-	long    node_pos;
-
-	if (mode == mode_X || is_Block(node)) {
-		return arch_no_register_req;
-	}
-
-	if (mode == mode_T && pos < 0) {
-		return arch_no_register_req;
-	}
-
-	node_pos = pos == -1 ? 0 : pos;
-	if (is_Proj(node)) {
-		if (mode == mode_M || pos >= 0) {
-			return arch_no_register_req;
-		}
-
-		node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
-		node     = skip_Proj_const(node);
-	}
-
-	if (is_ia32_irn(node)) {
-		const arch_register_req_t *req;
-		if (pos >= 0)
-			req = get_ia32_in_req(node, pos);
-		else
-			req = get_ia32_out_req(node, node_pos);
-
-		assert(req != NULL);
-
-		return req;
-	}
-
-	/* unknowns should be transformed already */
+	(void) node;
+	(void) pos;
 	return arch_no_register_req;
 }
 
-static arch_irn_class_t ia32_classify(const ir_node *irn) {
+static arch_irn_class_t ia32_classify(const ir_node *irn)
+{
 	arch_irn_class_t classification = 0;
 
-	irn = skip_Proj_const(irn);
-
-	if (is_cfop(irn))
-		classification |= arch_irn_class_branch;
-
-	if (! is_ia32_irn(irn))
-		return classification;
+	assert(is_ia32_irn(irn));
 
 	if (is_ia32_is_reload(irn))
 		classification |= arch_irn_class_reload;
@@ -279,11 +224,13 @@ typedef struct {
 	ir_graph *irg;                   /**< The associated graph. */
 } ia32_abi_env_t;
 
-static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
+static ir_entity *ia32_get_frame_entity(const ir_node *irn)
+{
 	return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
 }
 
-static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
+static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent)
+{
 	set_ia32_frame_ent(irn, ent);
 }
 
@@ -293,9 +240,9 @@ static void ia32_set_frame_offset(ir_node *irn, int bias)
 		return;
 
 	if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
-		ia32_code_gen_t *cg = ia32_current_cg;
-		int omit_fp = be_abi_omit_fp(cg->birg->abi);
-		if (omit_fp) {
+		ir_graph          *irg     = get_irn_irg(irn);
+		be_stack_layout_t *layout  = be_get_irg_stack_layout(irg);
+		if (layout->sp_relative) {
 			/* Pop nodes modify the stack pointer before calculating the
 			 * destination address, so fix this here
 			 */
@@ -337,9 +284,9 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
 	ia32_code_gen_t  *cg       = ia32_current_cg;
 	const arch_env_t *arch_env = env->aenv;
 
+	ia32_curr_fp_ommitted = env->flags.try_omit_fp;
 	if (! env->flags.try_omit_fp) {
-		ir_graph *irg     = env->irg;
-		ir_node  *bl      = get_irg_start_block(irg);
+		ir_node  *bl      = get_irg_start_block(env->irg);
 		ir_node  *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
 		ir_node  *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
 		ir_node  *noreg   = ia32_new_NoReg_gp(cg);
@@ -351,8 +298,8 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
 
 		/* push ebp */
 		push    = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
-		curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
-		*mem    = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
+		curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
+		*mem    = new_r_Proj(push, mode_M, pn_ia32_Push_M);
 
 		/* the push must have SP out register */
 		arch_set_irn_register(curr_sp, arch_env->sp);
@@ -361,12 +308,12 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
 		*stack_bias -= 4;
 
 		/* move esp to ebp */
-		curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
+		curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
 		be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
 		                             arch_register_req_type_ignore);
 
 		/* beware: the copy must be done before any other sp use */
-		curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
+		curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
 		be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
 				                     arch_register_req_type_produces_sp);
 
@@ -395,11 +342,10 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
 	const arch_env_t *arch_env = env->aenv;
 	ir_node          *curr_sp  = be_abi_reg_map_get(reg_map, arch_env->sp);
 	ir_node          *curr_bp  = be_abi_reg_map_get(reg_map, arch_env->bp);
-	ir_graph         *irg      = env->irg;
 
 	if (env->flags.try_omit_fp) {
 		/* simply remove the stack frame here */
-		curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
+		curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
 	} else {
 		ir_mode *mode_bp = arch_env->bp->reg_class->mode;
 
@@ -408,8 +354,8 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
 
 			/* leave */
 			leave   = new_bd_ia32_Leave(NULL, bl, curr_bp);
-			curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
-			curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
+			curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
+			curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
 		} else {
 			ir_node *pop;
 
@@ -418,17 +364,17 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
 			kill_node(curr_sp);
 
 			/* copy ebp to esp */
-			curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
+			curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
 			arch_set_irn_register(curr_sp, arch_env->sp);
 			be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
 				                         arch_register_req_type_ignore);
 
 			/* pop ebp */
 			pop     = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
-			curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
-			curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
+			curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
+			curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
 
-			*mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
+			*mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
 		}
 		arch_set_irn_register(curr_sp, arch_env->sp);
 		arch_set_irn_register(curr_bp, arch_env->bp);
@@ -459,30 +405,20 @@ static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir
  * Destroy the callback object.
  * @param self The callback object.
  */
-static void ia32_abi_done(void *self) {
+static void ia32_abi_done(void *self)
+{
 	free(self);
 }
 
 /**
- * Produces the type which sits between the stack args and the locals on the stack.
- * it will contain the return address and space to store the old base pointer.
- * @return The Firm type modeling the ABI between type.
+ * Build the between type and entities if not already build.
  */
-static ir_type *ia32_abi_get_between_type(void *self)
+static void ia32_build_between_type(void)
 {
 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
-	static ir_type *omit_fp_between_type = NULL;
-	static ir_type *between_type         = NULL;
-
-	ia32_abi_env_t *env = self;
-
 	if (! between_type) {
-		ir_entity *old_bp_ent;
-		ir_entity *ret_addr_ent;
-		ir_entity *omit_fp_ret_addr_ent;
-
-		ir_type *old_bp_type   = new_type_primitive(IDENT("bp"), mode_Iu);
-		ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
+		ir_type *old_bp_type   = new_type_primitive(mode_Iu);
+		ir_type *ret_addr_type = new_type_primitive(mode_Iu);
 
 		between_type           = new_type_struct(IDENT("ia32_between_type"));
 		old_bp_ent             = new_entity(between_type, IDENT("old_bp"), old_bp_type);
@@ -500,9 +436,38 @@ static ir_type *ia32_abi_get_between_type(void *self)
 		set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
 		set_type_state(omit_fp_between_type, layout_fixed);
 	}
+#undef IDENT
+}
+
+/**
+ * Produces the type which sits between the stack args and the locals on the stack.
+ * it will contain the return address and space to store the old base pointer.
+ * @return The Firm type modeling the ABI between type.
+ */
+static ir_type *ia32_abi_get_between_type(void *self)
+{
+	ia32_abi_env_t *env = self;
 
+	ia32_build_between_type();
 	return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
-#undef IDENT
+}
+
+/**
+ * Return the stack entity that contains the return address.
+ */
+ir_entity *ia32_get_return_address_entity(void)
+{
+	ia32_build_between_type();
+	return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
+}
+
+/**
+ * Return the stack entity that contains the frame address.
+ */
+ir_entity *ia32_get_frame_address_entity(void)
+{
+	ia32_build_between_type();
+	return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
 }
 
 /**
@@ -564,7 +529,15 @@ static int ia32_get_op_estimated_cost(const ir_node *irn)
  * @param obstack   The obstack to use for allocation of the returned nodes array
  * @return          The inverse operation or NULL if operation invertible
  */
-static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
+static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
+{
+	(void) irn;
+	(void) i;
+	(void) inverse;
+	(void) obst;
+	return NULL;
+
+#if 0
 	ir_mode  *mode;
 	ir_mode  *irn_mode;
 	ir_node  *block, *noreg, *nomem;
@@ -677,11 +650,12 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
 	}
 
 	return inverse;
+#endif
 }
 
 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
 {
-	if(mode_is_float(mode))
+	if (mode_is_float(mode))
 		return mode_D;
 
 	return mode_Iu;
@@ -810,10 +784,30 @@ static const be_abi_callbacks_t ia32_abi_callbacks = {
 	ia32_abi_epilogue
 };
 
-/* fill register allocator interface */
-
+/* register allocator interface */
 static const arch_irn_ops_t ia32_irn_ops = {
-	ia32_get_irn_reg_req,
+	get_ia32_in_req,
+	ia32_classify,
+	ia32_get_frame_entity,
+	ia32_set_frame_entity,
+	ia32_set_frame_offset,
+	ia32_get_sp_bias,
+	ia32_get_inverse,
+	ia32_get_op_estimated_cost,
+	ia32_possible_memory_operand,
+	ia32_perform_memory_operand,
+};
+
+/* special register allocator interface for SwitchJmp
+   as it possibly has a WIDE range of Proj numbers.
+   We don't want to allocate output for register constraints for
+   all these. */
+static const arch_irn_ops_t ia32_SwitchJmp_irn_ops = {
+	/* Note: we also use SwitchJmp_out_req for the inputs too:
+	   This is because the bearch API has a conceptual problem at the moment.
+	   Querying for negative proj numbers which can happen for switchs
+	   isn't possible and will result in inputs getting queried */
+	get_ia32_SwitchJmp_out_req,
 	ia32_classify,
 	ia32_get_frame_entity,
 	ia32_set_frame_entity,
@@ -825,22 +819,13 @@ static const arch_irn_ops_t ia32_irn_ops = {
 	ia32_perform_memory_operand,
 };
 
-/**************************************************
- *                _                         _  __
- *               | |                       (_)/ _|
- *   ___ ___   __| | ___  __ _  ___ _ __    _| |_
- *  / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \  | |  _|
- * | (_| (_) | (_| |  __/ (_| |  __/ | | | | | |
- *  \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
- *                        __/ |
- *                       |___/
- **************************************************/
 
 static ir_entity *mcount = NULL;
 
 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
 
-static void ia32_before_abi(void *self) {
+static void ia32_before_abi(void *self)
+{
 	lower_mode_b_config_t lower_mode_b_config = {
 		mode_Iu,  /* lowered mode */
 		mode_Bu,  /* preferred mode for set */
@@ -850,14 +835,15 @@ static void ia32_before_abi(void *self) {
 
 	ir_lower_mode_b(cg->irg, &lower_mode_b_config);
 	if (cg->dump)
-		be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
+		dump_ir_graph(cg->irg, "lower_modeb");
+
 	if (cg->gprof) {
 		if (mcount == NULL) {
-			ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
+			ir_type *tp = new_type_method(0, 0);
 			mcount = new_entity(get_glob_type(), ID("mcount"), tp);
 			/* FIXME: enter the right ld_ident here */
 			set_entity_ld_ident(mcount, get_entity_ident(mcount));
-			set_entity_visibility(mcount, visibility_external_allocated);
+			set_entity_visibility(mcount, ir_visibility_external);
 		}
 		instrument_initcall(cg->irg, mcount);
 	}
@@ -869,51 +855,33 @@ static void ia32_before_abi(void *self) {
  */
 static void ia32_prepare_graph(void *self)
 {
-	ia32_code_gen_t *cg  = self;
-	ir_graph        *irg = cg->irg;
-
-	/* do local optimizations */
-	optimize_graph_df(irg);
-
-	/* we have to do cfopt+remove_critical_edges as we can't have Bad-blocks
-	 * or critical edges in the backend */
-	optimize_cf(irg);
-	remove_critical_cf_edges(irg);
-
-	/* TODO: we often have dead code reachable through out-edges here. So for
-	 * now we rebuild edges (as we need correct user count for code selection)
-	 */
-#if 1
-	edges_deactivate(cg->irg);
-	edges_activate(cg->irg);
-#endif
-
-	if (cg->dump)
-		be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
+	ia32_code_gen_t *cg = self;
 
+#ifdef FIRM_GRGEN_BE
 	switch (be_transformer) {
 	case TRANSFORMER_DEFAULT:
 		/* transform remaining nodes into assembler instructions */
 		ia32_transform_graph(cg);
 		break;
 
-#ifdef FIRM_GRGEN_BE
 	case TRANSFORMER_PBQP:
 	case TRANSFORMER_RAND:
 		/* transform nodes into assembler instructions by PBQP magic */
 		ia32_transform_graph_by_pbqp(cg);
 		break;
-#endif
 
 	default:
 		panic("invalid transformer");
 	}
+#else
+	ia32_transform_graph(cg);
+#endif
 
 	/* do local optimizations (mainly CSE) */
 	optimize_graph_df(cg->irg);
 
 	if (cg->dump)
-		be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
+		dump_ir_graph(cg->irg, "transformed");
 
 	/* optimize address mode */
 	ia32_optimize_graph(cg);
@@ -922,12 +890,11 @@ static void ia32_prepare_graph(void *self)
 	place_code(cg->irg);
 
 	if (cg->dump)
-		be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
+		dump_ir_graph(cg->irg, "place");
 }
 
 ir_node *turn_back_am(ir_node *node)
 {
-	ir_graph *irg   = current_ir_graph;
 	dbg_info *dbgi  = get_irn_dbg_info(node);
 	ir_node  *block = get_nodes_block(node);
 	ir_node  *base  = get_irn_n(node, n_ia32_base);
@@ -936,7 +903,7 @@ ir_node *turn_back_am(ir_node *node)
 	ir_node  *noreg;
 
 	ir_node  *load     = new_bd_ia32_Load(dbgi, block, base, index, mem);
-	ir_node  *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
+	ir_node  *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
 
 	ia32_copy_am_attrs(load, node);
 	if (is_ia32_is_reload(node))
@@ -1024,14 +991,15 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
 /**
  * Called before the register allocator.
  */
-static void ia32_before_ra(void *self) {
+static void ia32_before_ra(void *self)
+{
 	ia32_code_gen_t *cg = self;
 
 	/* setup fpu rounding modes */
 	ia32_setup_fpu_mode(cg);
 
 	/* fixup flags */
-	be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
+	be_sched_fix_flags(cg->irg, &ia32_reg_classes[CLASS_ia32_flags],
 	                   &flags_remat);
 
 	ia32_add_missing_keeps(cg);
@@ -1041,7 +1009,8 @@ static void ia32_before_ra(void *self) {
 /**
  * Transforms a be_Reload into a ia32 Load.
  */
-static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
+static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
+{
 	ir_graph *irg        = get_irn_irg(node);
 	dbg_info *dbg        = get_irn_dbg_info(node);
 	ir_node *block       = get_nodes_block(node);
@@ -1080,7 +1049,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
 
 	DBG_OPT_RELOAD2LD(node, new_op);
 
-	proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
+	proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
 
 	if (sched_point) {
 		sched_add_after(sched_point, new_op);
@@ -1099,7 +1068,8 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
 /**
  * Transforms a be_Spill node into a ia32 Store.
  */
-static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
+static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
+{
 	ir_graph *irg  = get_irn_irg(node);
 	dbg_info *dbg  = get_irn_dbg_info(node);
 	ir_node *block = get_nodes_block(node);
@@ -1117,18 +1087,6 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
 		sched_point = sched_prev(node);
 	}
 
-	/* No need to spill unknown values... */
-	if(is_ia32_Unknown_GP(val) ||
-		is_ia32_Unknown_VFP(val) ||
-		is_ia32_Unknown_XMM(val)) {
-		store = nomem;
-		if(sched_point)
-			sched_remove(node);
-
-		exchange(node, store);
-		return;
-	}
-
 	if (mode_is_float(mode)) {
 		if (ia32_cg_config.use_sse2)
 			store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
@@ -1159,7 +1117,8 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
 	exchange(node, store);
 }
 
-static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
+static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
+{
 	dbg_info *dbg = get_irn_dbg_info(node);
 	ir_node *block = get_nodes_block(node);
 	ir_node *noreg = ia32_new_NoReg_gp(cg);
@@ -1178,11 +1137,12 @@ static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpo
 	return push;
 }
 
-static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
+static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
+{
 	dbg_info *dbg = get_irn_dbg_info(node);
 	ir_node *block = get_nodes_block(node);
 	ir_node *noreg = ia32_new_NoReg_gp(cg);
-	ir_graph *irg = get_irn_irg(node);
+	ir_graph *irg  = get_irn_irg(node);
 	ir_node *frame = get_irg_frame(irg);
 
 	ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
@@ -1200,14 +1160,12 @@ static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoi
 
 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
 {
-	ir_graph *irg = get_irn_irg(node);
 	dbg_info *dbg = get_irn_dbg_info(node);
-	ir_node *block = get_nodes_block(node);
 	ir_mode *spmode = mode_Iu;
 	const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
 	ir_node *sp;
 
-	sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
+	sp = new_rd_Proj(dbg, pred, spmode, pos);
 	arch_set_irn_register(sp, spreg);
 
 	return sp;
@@ -1220,9 +1178,8 @@ static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
  */
 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 {
-	ir_graph        *irg   = get_irn_irg(node);
 	ir_node         *block = get_nodes_block(node);
-	ir_node         *sp    = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
+	ir_node         *sp    = be_abi_get_ignore_irn(be_get_irg_abi(cg->irg), &ia32_gp_regs[REG_ESP]);
 	int              arity = be_get_MemPerm_entity_arity(node);
 	ir_node        **pops  = ALLOCAN(ir_node*, arity);
 	ir_node         *in[1];
@@ -1232,7 +1189,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 	const ir_edge_t *next;
 
 	/* create Pushs */
-	for(i = 0; i < arity; ++i) {
+	for (i = 0; i < arity; ++i) {
 		ir_entity *inent = be_get_MemPerm_in_entity(node, i);
 		ir_entity *outent = be_get_MemPerm_out_entity(node, i);
 		ir_type *enttype = get_entity_type(inent);
@@ -1242,13 +1199,13 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 		ir_node *push;
 
 		/* work around cases where entities have different sizes */
-		if(entsize2 < entsize)
+		if (entsize2 < entsize)
 			entsize = entsize2;
 		assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
 
 		push = create_push(cg, node, node, sp, mem, inent);
 		sp = create_spproj(node, push, pn_ia32_Push_stack);
-		if(entsize == 8) {
+		if (entsize == 8) {
 			/* add another push after the first one */
 			push = create_push(cg, node, node, sp, mem, inent);
 			add_ia32_am_offs_int(push, 4);
@@ -1259,7 +1216,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 	}
 
 	/* create pops */
-	for(i = arity - 1; i >= 0; --i) {
+	for (i = arity - 1; i >= 0; --i) {
 		ir_entity *inent = be_get_MemPerm_in_entity(node, i);
 		ir_entity *outent = be_get_MemPerm_out_entity(node, i);
 		ir_type *enttype = get_entity_type(outent);
@@ -1268,13 +1225,13 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 		ir_node *pop;
 
 		/* work around cases where entities have different sizes */
-		if(entsize2 < entsize)
+		if (entsize2 < entsize)
 			entsize = entsize2;
 		assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
 
 		pop = create_pop(cg, node, node, sp, outent);
 		sp = create_spproj(node, pop, pn_ia32_Pop_stack);
-		if(entsize == 8) {
+		if (entsize == 8) {
 			add_ia32_am_offs_int(pop, 4);
 
 			/* add another pop after the first one */
@@ -1286,7 +1243,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 	}
 
 	in[0] = sp;
-	keep  = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+	keep  = be_new_Keep(block, 1, in);
 	sched_add_before(node, keep);
 
 	/* exchange memprojs */
@@ -1302,7 +1259,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 
 	/* remove memperm */
 	arity = get_irn_arity(node);
-	for(i = 0; i < arity; ++i) {
+	for (i = 0; i < arity; ++i) {
 		set_irn_n(node, i, new_Bad());
 	}
 	sched_remove(node);
@@ -1311,7 +1268,8 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 /**
  * Block-Walker: Calls the transform functions Spill and Reload.
  */
-static void ia32_after_ra_walker(ir_node *block, void *env) {
+static void ia32_after_ra_walker(ir_node *block, void *env)
+{
 	ir_node *node, *prev;
 	ia32_code_gen_t *cg = env;
 
@@ -1407,10 +1365,11 @@ need_stackent:
  * We transform Spill and Reload here. This needs to be done before
  * stack biasing otherwise we would miss the corrected offset for these nodes.
  */
-static void ia32_after_ra(void *self) {
+static void ia32_after_ra(void *self)
+{
 	ia32_code_gen_t *cg = self;
 	ir_graph *irg = cg->irg;
-	be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
+	be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->irg);
 
 	/* create and coalesce frame entities */
 	irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
@@ -1425,7 +1384,8 @@ static void ia32_after_ra(void *self) {
  * virtual with real x87 instructions, creating a block schedule and peephole
  * optimisations.
  */
-static void ia32_finish(void *self) {
+static void ia32_finish(void *self)
+{
 	ia32_code_gen_t *cg = self;
 	ir_graph        *irg = cg->irg;
 
@@ -1433,7 +1393,7 @@ static void ia32_finish(void *self) {
 
 	/* we might have to rewrite x87 virtual registers */
 	if (cg->do_x87_sim) {
-		x87_simulate_graph(cg->birg);
+		x87_simulate_graph(cg->irg);
 	}
 
 	/* do peephole optimisations */
@@ -1441,20 +1401,23 @@ static void ia32_finish(void *self) {
 
 	/* create block schedule, this also removes empty blocks which might
 	 * produce critical edges */
-	cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
+	cg->blk_sched = be_create_block_schedule(irg);
 }
 
 /**
  * Emits the code, closes the output file and frees
  * the code generator interface.
  */
-static void ia32_codegen(void *self) {
+static void ia32_codegen(void *self)
+{
 	ia32_code_gen_t *cg = self;
 	ir_graph        *irg = cg->irg;
 
-	ia32_gen_routine(cg, irg);
-
-	cur_reg_set = NULL;
+	if (ia32_cg_config.emit_machcode) {
+		ia32_gen_binary_routine(cg, irg);
+	} else {
+		ia32_gen_routine(cg, irg);
+	}
 
 	/* remove it from the isa */
 	cg->isa->cg = NULL;
@@ -1463,14 +1426,14 @@ static void ia32_codegen(void *self) {
 	ia32_current_cg = NULL;
 
 	/* de-allocate code generator */
-	del_set(cg->reg_set);
 	free(cg);
 }
 
 /**
  * Returns the node representing the PIC base.
  */
-static ir_node *ia32_get_pic_base(void *self) {
+static ir_node *ia32_get_pic_base(void *self)
+{
 	ir_node         *block;
 	ia32_code_gen_t *cg      = self;
 	ir_node         *get_eip = cg->get_eip;
@@ -1485,7 +1448,7 @@ static ir_node *ia32_get_pic_base(void *self) {
 	return get_eip;
 }
 
-static void *ia32_cg_init(be_irg_t *birg);
+static void *ia32_cg_init(ir_graph *irg);
 
 static const arch_code_generator_if_t ia32_code_gen_if = {
 	ia32_cg_init,
@@ -1502,22 +1465,21 @@ static const arch_code_generator_if_t ia32_code_gen_if = {
 /**
  * Initializes a IA32 code generator.
  */
-static void *ia32_cg_init(be_irg_t *birg) {
-	ia32_isa_t      *isa = (ia32_isa_t *)birg->main_env->arch_env;
+static void *ia32_cg_init(ir_graph *irg)
+{
+	ia32_isa_t      *isa = (ia32_isa_t *)be_get_irg_arch_env(irg);
 	ia32_code_gen_t *cg  = XMALLOCZ(ia32_code_gen_t);
 
 	cg->impl      = &ia32_code_gen_if;
-	cg->irg       = birg->irg;
-	cg->reg_set   = new_set(ia32_cmp_irn_reg_assoc, 1024);
+	cg->irg       = irg;
 	cg->isa       = isa;
-	cg->birg      = birg;
 	cg->blk_sched = NULL;
-	cg->dump      = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
-	cg->gprof     = (birg->main_env->options->gprof) ? 1 : 0;
+	cg->dump      = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
+	cg->gprof     = (be_get_irg_options(irg)->gprof) ? 1 : 0;
 
 	if (cg->gprof) {
 		/* Linux gprof implementation needs base pointer */
-		birg->main_env->options->omit_fp = 0;
+		be_get_irg_options(irg)->omit_fp = 0;
 	}
 
 	/* enter it */
@@ -1530,8 +1492,6 @@ static void *ia32_cg_init(be_irg_t *birg) {
 	}
 #endif /* NDEBUG */
 
-	cur_reg_set = cg->reg_set;
-
 	assert(ia32_current_cg == NULL);
 	ia32_current_cg = cg;
 
@@ -1539,17 +1499,6 @@ static void *ia32_cg_init(be_irg_t *birg) {
 }
 
 
-
-/*****************************************************************
- *  ____             _                  _   _____  _____
- * |  _ \           | |                | | |_   _|/ ____|  /\
- * | |_) | __ _  ___| | _____ _ __   __| |   | | | (___   /  \
- * |  _ < / _` |/ __| |/ / _ \ '_ \ / _` |   | |  \___ \ / /\ \
- * | |_) | (_| | (__|   <  __/ | | | (_| |  _| |_ ____) / ____ \
- * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/    \_\
- *
- *****************************************************************/
-
 /**
  * Set output modes for GCC
  */
@@ -1586,11 +1535,13 @@ static ia32_isa_t ia32_isa_template = {
 		&ia32_isa_if,            /* isa interface implementation */
 		&ia32_gp_regs[REG_ESP],  /* stack pointer register */
 		&ia32_gp_regs[REG_EBP],  /* base pointer register */
+		&ia32_reg_classes[CLASS_ia32_gp],  /* static link pointer register class */
 		-1,                      /* stack direction */
 		2,                       /* power of two stack alignment, 2^2 == 4 */
 		NULL,                    /* main environment */
 		7,                       /* costs for a spill instruction */
 		5,                       /* costs for a reload instruction */
+		false,                   /* no custom abi handling */
 	},
 	NULL,                    /* 16bit register names */
 	NULL,                    /* 8bit register names */
@@ -1654,7 +1605,8 @@ static void init_asm_constraints(void)
 /**
  * Initializes the backend ISA.
  */
-static arch_env_t *ia32_init(FILE *file_handle) {
+static arch_env_t *ia32_init(FILE *file_handle)
+{
 	static int inited = 0;
 	ia32_isa_t *isa;
 	int        i, n;
@@ -1668,12 +1620,14 @@ static arch_env_t *ia32_init(FILE *file_handle) {
 	isa = XMALLOC(ia32_isa_t);
 	memcpy(isa, &ia32_isa_template, sizeof(*isa));
 
-	if(mode_fpcw == NULL) {
+	if (mode_fpcw == NULL) {
 		mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
 	}
 
 	ia32_register_init();
 	ia32_create_opcodes(&ia32_irn_ops);
+	/* special handling for SwitchJmp */
+	op_ia32_SwitchJmp->ops.be_ops = &ia32_SwitchJmp_irn_ops;
 
 	be_emit_init(file_handle);
 	isa->regs_16bit     = pmap_create();
@@ -1705,15 +1659,9 @@ static arch_env_t *ia32_init(FILE *file_handle) {
 
 	/* needed for the debug support */
 	be_gas_emit_switch_section(GAS_SECTION_TEXT);
-	be_emit_cstring(".Ltext0:\n");
+	be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
 	be_emit_write_line();
 
-	/* we mark referenced global entities, so we can only emit those which
-	 * are actually referenced. (Note: you mustn't use the type visited flag
-	 * elsewhere in the backend)
-	 */
-	inc_master_type_visited();
-
 	return &isa->arch_env;
 }
 
@@ -1722,11 +1670,12 @@ static arch_env_t *ia32_init(FILE *file_handle) {
 /**
  * Closes the output file and frees the ISA structure.
  */
-static void ia32_done(void *self) {
+static void ia32_done(void *self)
+{
 	ia32_isa_t *isa = self;
 
 	/* emit now all global declarations */
-	be_gas_emit_decls(isa->arch_env.main_env, 1);
+	be_gas_emit_decls(isa->arch_env.main_env);
 
 	pmap_destroy(isa->regs_16bit);
 	pmap_destroy(isa->regs_8bit);
@@ -1752,18 +1701,16 @@ static void ia32_done(void *self) {
  *  - the virtual floating point registers
  *  - the SSE vector register set
  */
-static unsigned ia32_get_n_reg_class(const void *self) {
-	(void) self;
+static unsigned ia32_get_n_reg_class(void)
+{
 	return N_CLASSES;
 }
 
 /**
  * Return the register class for index i.
  */
-static const arch_register_class_t *ia32_get_reg_class(const void *self,
-                                                       unsigned i)
+static const arch_register_class_t *ia32_get_reg_class(unsigned i)
 {
-	(void) self;
 	assert(i < N_CLASSES);
 	return &ia32_reg_classes[i];
 }
@@ -1774,11 +1721,8 @@ static const arch_register_class_t *ia32_get_reg_class(const void *self,
  * @param mode The mode in question.
  * @return A register class which can hold values of the given mode.
  */
-const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
-		const ir_mode *mode)
+static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
 {
-	(void) self;
-
 	if (mode_is_float(mode)) {
 		return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
 	}
@@ -1786,6 +1730,88 @@ const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
 		return &ia32_reg_classes[CLASS_ia32_gp];
 }
 
+/**
+ * Returns the register for parameter nr.
+ */
+static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
+                                                    const ir_mode *mode)
+{
+	static const arch_register_t *gpreg_param_reg_fastcall[] = {
+		&ia32_gp_regs[REG_ECX],
+		&ia32_gp_regs[REG_EDX],
+		NULL
+	};
+	static const unsigned MAXNUM_GPREG_ARGS = 3;
+
+	static const arch_register_t *gpreg_param_reg_regparam[] = {
+		&ia32_gp_regs[REG_EAX],
+		&ia32_gp_regs[REG_EDX],
+		&ia32_gp_regs[REG_ECX]
+	};
+
+	static const arch_register_t *gpreg_param_reg_this[] = {
+		&ia32_gp_regs[REG_ECX],
+		NULL,
+		NULL
+	};
+
+	static const arch_register_t *fpreg_sse_param_reg_std[] = {
+		&ia32_xmm_regs[REG_XMM0],
+		&ia32_xmm_regs[REG_XMM1],
+		&ia32_xmm_regs[REG_XMM2],
+		&ia32_xmm_regs[REG_XMM3],
+		&ia32_xmm_regs[REG_XMM4],
+		&ia32_xmm_regs[REG_XMM5],
+		&ia32_xmm_regs[REG_XMM6],
+		&ia32_xmm_regs[REG_XMM7]
+	};
+
+	static const arch_register_t *fpreg_sse_param_reg_this[] = {
+		NULL,  /* in case of a "this" pointer, the first parameter must not be a float */
+	};
+	static const unsigned MAXNUM_SSE_ARGS = 8;
+
+	if ((cc & cc_this_call) && nr == 0)
+		return gpreg_param_reg_this[0];
+
+	if (! (cc & cc_reg_param))
+		return NULL;
+
+	if (mode_is_float(mode)) {
+		if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
+			return NULL;
+		if (nr >= MAXNUM_SSE_ARGS)
+			return NULL;
+
+		if (cc & cc_this_call) {
+			return fpreg_sse_param_reg_this[nr];
+		}
+		return fpreg_sse_param_reg_std[nr];
+	} else if (mode_is_int(mode) || mode_is_reference(mode)) {
+		unsigned num_regparam;
+
+		if (get_mode_size_bits(mode) > 32)
+			return NULL;
+
+		if (nr >= MAXNUM_GPREG_ARGS)
+			return NULL;
+
+		if (cc & cc_this_call) {
+			return gpreg_param_reg_this[nr];
+		}
+		num_regparam = cc & ~cc_bits;
+		if (num_regparam == 0) {
+			/* default fastcall */
+			return gpreg_param_reg_fastcall[nr];
+		}
+		if (nr < num_regparam)
+			return gpreg_param_reg_regparam[nr];
+		return NULL;
+	}
+
+	panic("unknown argument mode");
+}
+
 /**
  * Get the ABI restrictions for procedure calls.
  * @param self        The this pointer.
@@ -1809,25 +1835,25 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 	call_flags.bits.store_args_sequential = 0;
 	/* call_flags.bits.try_omit_fp                 not changed: can handle both settings */
 	call_flags.bits.fp_free               = 0;  /* the frame pointer is fixed in IA32 */
-	call_flags.bits.call_has_imm          = 0;  /* No call immediates, we handle this by ourselves */
+	call_flags.bits.call_has_imm          = 0;  /* No call immediate, we handle this by ourselves */
 
 	/* set parameter passing style */
 	be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
 
+	cc = get_method_calling_convention(method_type);
 	if (get_method_variadicity(method_type) == variadicity_variadic) {
 		/* pass all parameters of a variadic function on the stack */
-		cc = cc_cdecl_set;
+		cc = cc_cdecl_set | (cc & cc_this_call);
 	} else {
-		cc = get_method_calling_convention(method_type);
 		if (get_method_additional_properties(method_type) & mtp_property_private &&
 		    ia32_cg_config.optimize_cc) {
-			/* set the calling conventions to register parameter */
-			cc = (cc & ~cc_bits) | cc_reg_param;
+			/* set the fast calling conventions (allowing up to 3) */
+			cc = SET_FASTCALL(cc) | 3;
 		}
 	}
 
 	/* we have to pop the shadow parameter ourself for compound calls */
-	if( (get_method_calling_convention(method_type) & cc_compound_ret)
+	if ( (get_method_calling_convention(method_type) & cc_compound_ret)
 			&& !(cc & cc_reg_param)) {
 		pop_amount += get_mode_size_bytes(mode_P_data);
 	}
@@ -1843,7 +1869,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 			reg  = ia32_get_RegParam_reg(cc, regnum, mode);
 		}
 		if (reg != NULL) {
-			be_abi_call_param_reg(abi, i, reg);
+			be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
 			++regnum;
 		} else {
 			/* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
@@ -1860,7 +1886,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 				if (size < 4) load_mode = mode_Iu;
 			}
 
-			be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
+			be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
 		}
 	}
 
@@ -1883,8 +1909,8 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 
 		assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
 
-		be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
-		be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
+		be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
+		be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
 	}
 	else if (n == 1) {
 		const arch_register_t *reg;
@@ -1895,22 +1921,20 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 
 		reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
 
-		be_abi_call_res_reg(abi, 0, reg);
+		be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
 	}
 }
 
-int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
+static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
 {
 	(void) block_env;
 
-	if(!is_ia32_irn(irn)) {
+	if (!is_ia32_irn(irn)) {
 		return -1;
 	}
 
-	if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
-		|| is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
-		|| is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
-		|| is_ia32_Immediate(irn))
+	if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
+	    || is_ia32_ChangeCW(irn) || is_ia32_Immediate(irn))
 		return 0;
 
 	return 1;
@@ -1928,7 +1952,8 @@ static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
 /**
  * Returns the estimated execution time of an ia32 irn.
  */
-static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
+static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
+{
 	(void) env;
 	return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
 }
@@ -1957,12 +1982,10 @@ static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
 /**
  * Returns the necessary byte alignment for storing a register of given class.
  */
-static int ia32_get_reg_class_alignment(const void *self,
-                                        const arch_register_class_t *cls)
+static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
 {
 	ir_mode *mode = arch_register_class_mode(cls);
 	int bytes     = get_mode_size_bytes(mode);
-	(void) self;
 
 	if (mode_is_float(mode) && bytes > 8)
 		return 16;
@@ -1970,7 +1993,7 @@ static int ia32_get_reg_class_alignment(const void *self,
 }
 
 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
-		const void *self, const ir_node *irn)
+		const ir_node *irn)
 {
 	static const be_execution_unit_t *_allowed_units_BRANCH[] = {
 		&ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
@@ -2004,7 +2027,6 @@ static const be_execution_unit_t ***ia32_get_allowed_execution_units(
 		NULL
 	};
 	const be_execution_unit_t ***ret;
-	(void) self;
 
 	if (is_ia32_irn(irn)) {
 		ret = get_ia32_exec_units(irn);
@@ -2027,7 +2049,8 @@ static const be_execution_unit_t ***ia32_get_allowed_execution_units(
 /**
  * Return the abstract ia32 machine.
  */
-static const be_machine_t *ia32_get_machine(const void *self) {
+static const be_machine_t *ia32_get_machine(const void *self)
+{
 	const ia32_isa_t *isa = self;
 	return isa->cpu;
 }
@@ -2042,248 +2065,255 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
 	return NULL;
 }
 
-static void ia32_mark_remat(const void *self, ir_node *node) {
-	(void) self;
+static void ia32_mark_remat(ir_node *node)
+{
 	if (is_ia32_irn(node)) {
 		set_ia32_is_remat(node);
 	}
 }
 
 /**
- * Check for Abs or -Abs.
+ * Check if Mux(sel, t, f) would represent an Abs (or -Abs).
  */
-static int psi_is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
-	ir_node *l, *r;
+static bool mux_is_abs(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
+{
+	ir_node *cmp_left;
+	ir_node *cmp_right;
+	ir_node *cmp;
 	pn_Cmp  pnc;
 
-	if (cmp == NULL)
-		return 0;
+	if (!is_Proj(sel))
+		return false;
+	cmp = get_Proj_pred(sel);
+	if (!is_Cmp(cmp))
+		return false;
 
 	/* must be <, <=, >=, > */
 	pnc = get_Proj_proj(sel);
-	if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
-		pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
-		return 0;
+	switch (pnc) {
+	case pn_Cmp_Ge:
+	case pn_Cmp_Gt:
+	case pn_Cmp_Le:
+	case pn_Cmp_Lt:
+	case pn_Cmp_Uge:
+	case pn_Cmp_Ug:
+	case pn_Cmp_Ul:
+	case pn_Cmp_Ule:
+		break;
+	default:
+		return false;
+	}
 
-	l = get_Cmp_left(cmp);
-	r = get_Cmp_right(cmp);
+	if (!is_negated_value(mux_true, mux_false))
+		return false;
 
 	/* must be x cmp 0 */
-	if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
+	cmp_right = get_Cmp_right(cmp);
+	if (!is_Const(cmp_right) || !is_Const_null(cmp_right))
 		return 0;
 
-	if ((!is_Minus(t) || get_Minus_op(t) != f) &&
-		(!is_Minus(f) || get_Minus_op(f) != t))
-		return 0;
-	return 1;
+	cmp_left = get_Cmp_left(cmp);
+	if (cmp_left != mux_true && cmp_left != mux_false)
+		return false;
+
+	return true;
 }
 
 /**
- * Check for Abs only
+ * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
  */
-static int psi_is_Abs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
-	ir_node *l, *r;
+static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
+                                 ir_node *mux_false)
+{
+	ir_node *cmp_l;
+	ir_node *cmp_r;
+	ir_node *cmp;
 	pn_Cmp  pnc;
 
-	if (cmp == NULL)
-		return 0;
-
-	/* must be <, <=, >=, > */
+	if (!is_Proj(sel))
+		return false;
+	cmp = get_Proj_pred(sel);
+	if (!is_Cmp(cmp))
+		return false;
+
+	cmp_l = get_Cmp_left(cmp);
+	cmp_r = get_Cmp_right(cmp);
+	if (!mode_is_float(get_irn_mode(cmp_l)))
+		return false;
+
+	/* check for min/max. They're defined as (C-Semantik):
+	 *  min(a, b) = a < b ? a : b
+	 *  or min(a, b) = a <= b ? a : b
+	 *  max(a, b) = a > b ? a : b
+	 *  or max(a, b) = a >= b ? a : b
+	 * (Note we only handle float min/max here)
+	 */
 	pnc = get_Proj_proj(sel);
-	if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
-		pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
-		return 0;
+	switch (pnc) {
+	case pn_Cmp_Ge:
+	case pn_Cmp_Gt:
+		/* this is a max */
+		if (cmp_l == mux_true && cmp_r == mux_false)
+			return true;
+		break;
+	case pn_Cmp_Le:
+	case pn_Cmp_Lt:
+		/* this is a min */
+		if (cmp_l == mux_true && cmp_r == mux_false)
+			return true;
+		break;
+	case pn_Cmp_Uge:
+	case pn_Cmp_Ug:
+		/* this is a min */
+		if (cmp_l == mux_false && cmp_r == mux_true)
+			return true;
+		break;
+	case pn_Cmp_Ule:
+	case pn_Cmp_Ul:
+		/* this is a max */
+		if (cmp_l == mux_false && cmp_r == mux_true)
+			return true;
+		break;
 
-	l = get_Cmp_left(cmp);
-	r = get_Cmp_right(cmp);
+	default:
+		break;
+	}
 
-	/* must be x cmp 0 */
-	if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
-		return 0;
+	return false;
+}
 
-	if ((!is_Minus(t) || get_Minus_op(t) != f) &&
-		(!is_Minus(f) || get_Minus_op(f) != t))
-		return 0;
+static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
+{
+	ir_mode *mode = get_irn_mode(mux_true);
+	(void) sel;
 
-	if (pnc & pn_Cmp_Gt) {
-		/* x >= 0 ? -x : x is NABS */
-		if (is_Minus(t))
-			return 0;
-	} else {
-		/* x < 0 ? x : -x is NABS */
-		if (is_Minus(f))
-			return 0;
+	if (!mode_is_int(mode) && !mode_is_reference(mode)
+			&& mode != mode_b)
+		return false;
+
+	if (is_Const(mux_true) && is_Const(mux_false)) {
+		/* we can create a set plus up two 3 instructions for any combination of constants */
+		return true;
 	}
-	return 1;
+
+	return false;
 }
 
+static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
+                                     ir_node *mux_false)
+{
+	(void) sel;
 
-/**
- * Allows or disallows the creation of Psi nodes for the given Phi nodes.
- *
- * @param sel        A selector of a Cond.
- * @param phi_list   List of Phi nodes about to be converted (linked via get_Phi_next() field)
- * @param i          First data predecessor involved in if conversion
- * @param j          Second data predecessor involved in if conversion
- *
- * @return 1 if allowed, 0 otherwise
- */
-static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
+	if (!mode_is_float(get_irn_mode(mux_true)))
+		return false;
+
+	return is_Const(mux_true) && is_Const(mux_false);
+}
+
+static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
 {
-	ir_node *phi;
 	ir_node *cmp;
-	pn_Cmp  pn;
-	ir_node *cl, *cr;
-
-	/* we can't handle Psis with 64bit compares yet */
-	if (is_Proj(sel)) {
-		cmp = get_Proj_pred(sel);
-		if (is_Cmp(cmp)) {
-			ir_node *left     = get_Cmp_left(cmp);
-			ir_mode *cmp_mode = get_irn_mode(left);
-			if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) {
-				/* 64bit Abs IS supported */
-				for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
-					ir_node *t = get_Phi_pred(phi, i);
-					ir_node *f = get_Phi_pred(phi, j);
-
-					if (! psi_is_Abs(cmp, sel, t, f))
-						return 0;
-				}
-				return 1;
-			}
-		} else {
-			/* we do not support nodes without Cmp yet */
-			return 0;
-		}
-	} else {
-		/* we do not support nodes without Cmp yet */
-		return 0;
+	ir_node *cmp_left;
+	ir_node *cmp_right;
+	ir_mode *mode;
+	long     pn;
+
+	if (!is_Proj(sel))
+		return false;
+
+	cmp = get_Proj_pred(sel);
+	if (!is_Cmp(cmp))
+		return false;
+
+	mode = get_irn_mode(mux_true);
+	if (mode_is_signed(mode) || mode_is_float(mode))
+		return false;
+
+	pn        = get_Proj_proj(sel);
+	cmp_left  = get_Cmp_left(cmp);
+	cmp_right = get_Cmp_right(cmp);
+	if ((pn & pn_Cmp_Gt) &&
+		is_Const(mux_false) && is_Const_null(mux_false) && is_Sub(mux_true) &&
+		get_Sub_left(mux_true) == cmp_left &&
+		get_Sub_right(mux_true) == cmp_right) {
+		/* Mux(a >=u b, a - b, 0) unsigned Doz */
+		return true;
+	}
+	if ((pn & pn_Cmp_Lt) &&
+		is_Const(mux_true) && is_Const_null(mux_true) && is_Sub(mux_false) &&
+		get_Sub_left(mux_false) == cmp_left &&
+		get_Sub_right(mux_false) == cmp_right) {
+		/* Mux(a <=u b, 0, a - b) unsigned Doz */
+		return true;
 	}
 
-	pn = get_Proj_proj(sel);
-	cl = get_Cmp_left(cmp);
-	cr = get_Cmp_right(cmp);
-
-	if (ia32_cg_config.use_cmov) {
-		if (ia32_cg_config.use_sse2) {
-			/* check the Phi nodes: no 64bit and no floating point cmov */
-			for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
-				ir_mode *mode = get_irn_mode(phi);
-
-				if (mode_is_float(mode)) {
-					/* check for Min, Max */
-					ir_node *t = get_Phi_pred(phi, i);
-					ir_node *f = get_Phi_pred(phi, j);
-
-					/* SSE2 supports Min & Max */
-					if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
-						if (cl == t && cr == f) {
-							/* Psi(a <=/>= b, a, b) => MIN, MAX */
-							continue;
-						} else if (cl == f && cr == t) {
-							/* Psi(a <=/>= b, b, a) => MAX, MIN */
-							continue;
-						}
-					}
-					return 0;
-				} else if (get_mode_size_bits(mode) > 32) {
-					/* no 64bit cmov */
-					return 0;
-				}
-			}
-		} else {
-			/* check the Phi nodes: no 64bit and no floating point cmov */
-			for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
-				ir_mode *mode = get_irn_mode(phi);
-
-				if (mode_is_float(mode)) {
-					ir_node *t = get_Phi_pred(phi, i);
-					ir_node *f = get_Phi_pred(phi, j);
-
-					/* always support Psi(!float, C1, C2) */
-					if (is_Const(t) && is_Const(f) && !mode_is_float(get_irn_mode(cl)))
-						continue;
-					/* only abs or nabs supported */
-					if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
-						return 0;
-				} else if (get_mode_size_bits(mode) > 32)
-					return 0;
-			}
-		}
+	return false;
+}
 
-		return 1;
-	} else { /* No Cmov, only some special cases */
+static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
+                               ir_node *mux_true)
+{
+	ir_mode *mode;
+
+	/* we can handle Abs for all modes and compares */
+	if (mux_is_abs(sel, mux_true, mux_false))
+		return true;
+	/* we can handle Set for all modes and compares */
+	if (mux_is_set(sel, mux_true, mux_false))
+		return true;
+	/* SSE has own min/max operations */
+	if (ia32_cg_config.use_sse2
+			&& mux_is_float_min_max(sel, mux_true, mux_false))
+		return true;
+	/* we can handle Mux(?, Const[f], Const[f]) */
+	if (mux_is_float_const_const(sel, mux_true, mux_false)) {
+#ifdef FIRM_GRGEN_BE
+		/* well, some code selectors can't handle it */
+		if (be_transformer != TRANSFORMER_PBQP
+				|| be_transformer != TRANSFORMER_RAND)
+			return true;
+#else
+		return true;
+#endif
+	}
 
-		/* Now some supported cases here */
-		for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
-			ir_mode *mode = get_irn_mode(phi);
-			ir_node *t, *f;
+	/* no support for 64bit inputs to cmov */
+	mode = get_irn_mode(mux_true);
+	if (get_mode_size_bits(mode) > 32)
+		return false;
+	/* we can't handle MuxF yet */
+	if (mode_is_float(mode))
+		return false;
 
-			t = get_Phi_pred(phi, i);
-			f = get_Phi_pred(phi, j);
+	if (mux_is_doz(sel, mux_true, mux_false))
+		return true;
 
-			if (mode_is_float(mode)) {
-				/* always support Psi(!float, C1, C2) */
-				if (is_Const(t) && is_Const(f) && !mode_is_float(get_irn_mode(cl)))
-					continue;
-				/* only abs or nabs supported */
-				if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
-					return 0;
-			} else if (get_mode_size_bits(mode) > 32) {
-				/* no 64bit yet */
-				return 0;
-			}
+	/* Check Cmp before the node */
+	if (is_Proj(sel)) {
+		ir_node *cmp = get_Proj_pred(sel);
+		if (is_Cmp(cmp)) {
+			ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
 
-			if (is_Const(t) && is_Const(f)) {
-				if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
-					/* always support Psi(x, C1, C2) */
-					continue;
-				}
-			} else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
-#if 0
-				if (cl == t && cr == f) {
-					/* Psi(a <=/>= b, a, b) => Min, Max */
-					continue;
-				}
-				if (cl == f && cr == t) {
-					/* Psi(a <=/>= b, b, a) => Max, Min */
-					continue;
-				}
-#endif
-				if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
-				    is_Const(f) && is_Const_null(f) && is_Sub(t) &&
-				    get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
-					/* Psi(a >=u b, a - b, 0) unsigned Doz */
-					continue;
-				}
-				if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
-				    is_Const(t) && is_Const_null(t) && is_Sub(f) &&
-				    get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
-					/* Psi(a <=u b, 0, a - b) unsigned Doz */
-					continue;
-				}
-				if (is_Const(cr) && is_Const_null(cr)) {
-					if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
-						/* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
-						continue;
-					} else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
-						/* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
-						continue;
-					}
-				}
-			}
-			return 0;
+			/* we can't handle 64bit compares */
+			if (get_mode_size_bits(cmp_mode) > 32)
+				return false;
+
+			/* we can't handle float compares */
+			if (mode_is_float(cmp_mode))
+				return false;
 		}
-		/* all checks passed */
-		return 1;
 	}
-	return 0;
+
+	/* did we disable cmov generation? */
+	if (!ia32_cg_config.use_cmov)
+		return false;
+
+	/* we can use a cmov */
+	return true;
 }
 
-static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
+static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
 {
-	(void) self;
 	(void) c;
 
 	/* we already added all our simple flags to the flags modifier list in
@@ -2291,10 +2321,8 @@ static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const
 	return ASM_CONSTRAINT_FLAG_INVALID;
 }
 
-static int ia32_is_valid_clobber(const void *self, const char *clobber)
+static int ia32_is_valid_clobber(const char *clobber)
 {
-	(void) self;
-
 	return ia32_get_clobber_register(clobber) != NULL;
 }
 
@@ -2303,24 +2331,23 @@ static int ia32_is_valid_clobber(const void *self, const char *clobber)
  */
 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
 {
-	ir_graph *irg    = get_Block_irg(block);
 	ir_node  *st, *p = trampoline;
 	ir_mode *mode    = get_irn_mode(p);
 
 	/* mov  ecx,<env> */
-	st  = new_r_Store(irg, block, mem, p, new_Const_long(mode_Bu, 0xb9));
-	mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M);
-	p   = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 1), mode);
-	st  = new_r_Store(irg, block, mem, p, env);
-	mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M);
-	p   = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 4), mode);
+	st  = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
+	mem = new_r_Proj(st, mode_M, pn_Store_M);
+	p   = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
+	st  = new_r_Store(block, mem, p, env, 0);
+	mem = new_r_Proj(st, mode_M, pn_Store_M);
+	p   = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
 	/* jmp  <callee> */
-	st  = new_r_Store(irg, block, mem, p, new_Const_long(mode_Bu, 0xe9));
-	mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M);
-	p   = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 1), mode);
-	st  = new_r_Store(irg, block, mem, p, callee);
-	mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M);
-	p   = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 4), mode);
+	st  = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
+	mem = new_r_Proj(st, mode_M, pn_Store_M);
+	p   = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
+	st  = new_r_Store(block, mem, p, callee, 0);
+	mem = new_r_Proj(st, mode_M, pn_Store_M);
+	p   = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
 
 	return mem;
 }
@@ -2328,10 +2355,11 @@ static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node
 /**
  * Returns the libFirm configuration parameter for this backend.
  */
-static const backend_params *ia32_get_libfirm_params(void) {
+static const backend_params *ia32_get_libfirm_params(void)
+{
 	static const ir_settings_if_conv_t ifconv = {
-		4,                    /* maxdepth, doesn't matter for Psi-conversion */
-		ia32_is_psi_allowed   /* allows or disallows Psi creation for given selector */
+		4,                    /* maxdepth, doesn't matter for Mux-conversion */
+		ia32_is_mux_allowed   /* allows or disallows Mux creation for given selector */
 	};
 	static const ir_settings_arch_dep_t ad = {
 		1,                   /* also use subs */
@@ -2349,10 +2377,12 @@ static const backend_params *ia32_get_libfirm_params(void) {
 		NULL,  /* will be set later */
 		ia32_create_intrinsic_fkt,
 		&intrinsic_env,  /* context for ia32_create_intrinsic_fkt */
-		NULL,  /* will be set below */
+		NULL,  /* ifconv info will be set below */
+		NULL,  /* float arithmetic mode, will be set below */
 		12,    /* size of trampoline code */
 		4,     /* alignment of trampoline code */
 		ia32_create_trampoline_fkt,
+		4      /* alignment of stack parameter */
 	};
 
 	ia32_setup_cg_config();
@@ -2363,19 +2393,20 @@ static const backend_params *ia32_get_libfirm_params(void) {
 
 	p.dep_param    = &ad;
 	p.if_conv_info = &ifconv;
+	if (! ia32_cg_config.use_sse2)
+		p.mode_float_arithmetic = mode_E;
 	return &p;
 }
 
 static const lc_opt_enum_int_items_t gas_items[] = {
-	{ "elf",     GAS_FLAVOUR_ELF },
-	{ "mingw",   GAS_FLAVOUR_MINGW  },
-	{ "yasm",    GAS_FLAVOUR_YASM   },
-	{ "macho",   GAS_FLAVOUR_MACH_O },
-	{ NULL,      0 }
+	{ "elf",   OBJECT_FILE_FORMAT_ELF    },
+	{ "mingw", OBJECT_FILE_FORMAT_COFF   },
+	{ "macho", OBJECT_FILE_FORMAT_MACH_O },
+	{ NULL,    0 }
 };
 
 static lc_opt_enum_int_var_t gas_var = {
-	(int*) &be_gas_flavour, gas_items
+	(int*) &be_gas_object_file_format, gas_items
 };
 
 #ifdef FIRM_GRGEN_BE
@@ -2422,6 +2453,7 @@ const arch_isa_if_t ia32_isa_if = {
 	ia32_is_valid_clobber
 };
 
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
 void be_init_arch_ia32(void)
 {
 	lc_opt_entry_t *be_grp   = lc_opt_get_grp(firm_opt_get_root(), "be");
@@ -2439,5 +2471,3 @@ void be_init_arch_ia32(void)
 	ia32_init_x87();
 	ia32_init_architecture();
 }
-
-BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);