X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=f6b4eeeccb83a4c1420fb0c59d2d44ef0db37c0f;hb=e3b765fcef0e337f4fe2e17d57d2fbaf1912ec79;hp=ab9d2fb822d001c9d08720fb8f2deb5c594f2c76;hpb=ea40997bb109173b1ba75d01a958a3cf05a771c3;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index ab9d2fb82..f6b4eeecc 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -53,28 +53,30 @@ #include "iropt_t.h" #include "lower_dw.h" #include "lower_calls.h" +#include "lower_mode_b.h" #include "lower_softfloat.h" -#include "../beabi.h" -#include "../beirg.h" -#include "../benode.h" -#include "../belower.h" -#include "../besched.h" +#include "beabi.h" +#include "beirg.h" +#include "benode.h" +#include "belower.h" +#include "besched.h" #include "be.h" -#include "../be_t.h" -#include "../beirgmod.h" -#include "../be_dbgout.h" -#include "../beblocksched.h" -#include "../bemachine.h" -#include "../bespillslots.h" -#include "../bemodule.h" -#include "../begnuas.h" -#include "../bestate.h" -#include "../beflags.h" -#include "../betranshlp.h" -#include "../belistsched.h" -#include "../beabihelper.h" -#include "../bestack.h" +#include "be_t.h" +#include "beirgmod.h" +#include "be_dbgout.h" +#include "beblocksched.h" +#include "bemachine.h" +#include "bespillutil.h" +#include "bespillslots.h" +#include "bemodule.h" +#include "begnuas.h" +#include "bestate.h" +#include "beflags.h" +#include "betranshlp.h" +#include "belistsched.h" +#include "beabihelper.h" +#include "bestack.h" #include "bearch_ia32_t.h" @@ -97,7 +99,9 @@ transformer_t be_transformer = TRANSFORMER_DEFAULT; #endif -ir_mode *ia32_mode_fpcw = NULL; +ir_mode *ia32_mode_fpcw; +ir_mode *ia32_mode_E; +ir_type *ia32_type_E; /** The current omit-fp state */ static ir_type *omit_fp_between_type = NULL; @@ -177,7 +181,7 @@ ir_node *ia32_new_Fpu_truncate(ir_graph *irg) static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos) { ir_graph *irg = get_irn_irg(irn); - const arch_register_req_t *req = arch_get_register_req(irn, pos); + const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos); assert(req != NULL && "Missing register requirements"); if (req->cls == &ia32_reg_classes[CLASS_ia32_gp]) @@ -566,7 +570,7 @@ static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) /* we can't swap left/right for limited registers * (As this (currently) breaks constraint handling copies) */ - req = arch_get_in_register_req(irn, n_ia32_binary_left); + req = arch_get_irn_register_req_in(irn, n_ia32_binary_left); if (req->type & arch_register_req_type_limited) return 0; break; @@ -690,6 +694,8 @@ static void ia32_prepare_graph(ir_graph *irg) /* do local optimizations (mainly CSE) */ optimize_graph_df(irg); + /* backend code expects that outedges are always enabled */ + edges_assure(irg); if (irg_data->dump) dump_ir_graph(irg, "transformed"); @@ -699,6 +705,8 @@ static void ia32_prepare_graph(ir_graph *irg) /* do code placement, to optimize the position of constants */ place_code(irg); + /* backend code expects that outedges are always enabled */ + edges_assure(irg); if (irg_data->dump) dump_ir_graph(irg, "place"); @@ -1277,10 +1285,10 @@ static void introduce_prolog_epilog(ir_graph *irg) sched_add_after(start, push); /* move esp to ebp */ - curr_bp = be_new_Copy(bp->reg_class, block, curr_sp); + curr_bp = be_new_Copy(block, curr_sp); sched_add_after(push, curr_bp); be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore); - curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp); + curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp); sched_add_after(curr_bp, curr_sp); be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp); edges_reroute(initial_bp, curr_bp); @@ -1291,6 +1299,13 @@ static void introduce_prolog_epilog(ir_graph *irg) set_irn_n(push, n_ia32_Push_stack, initial_sp); sched_add_after(curr_sp, incsp); + /* make sure the initial IncSP is really used by someone */ + if (get_irn_n_edges(incsp) <= 1) { + ir_node *in[] = { incsp }; + ir_node *keep = be_new_Keep(block, 1, in); + sched_add_after(incsp, keep); + } + layout->initial_bias = -4; } else { ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0); @@ -1453,7 +1468,6 @@ static ia32_isa_t ia32_isa_template = { 5, /* costs for a reload instruction */ false, /* no custom abi handling */ }, - NULL, /* types */ NULL, /* tv_ents */ NULL, /* abstract machine */ IA32_FPU_ARCH_X87, /* FPU architecture */ @@ -1518,14 +1532,13 @@ static arch_env_t *ia32_init(FILE *file_handle) *isa = ia32_isa_template; if (ia32_mode_fpcw == NULL) { - ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0); + ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0); } ia32_register_init(); ia32_create_opcodes(&ia32_irn_ops); be_emit_init(file_handle); - isa->types = pmap_create(); isa->tv_ent = pmap_create(); isa->cpu = ia32_init_machine_description(); @@ -1548,7 +1561,6 @@ static void ia32_done(void *self) be_gas_emit_decls(isa->base.main_env); pmap_destroy(isa->tv_ent); - pmap_destroy(isa->types); be_emit_exit(); @@ -1930,6 +1942,9 @@ static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false, { ir_mode *mode; + /* middleend can handle some things */ + if (ir_is_optimizable_mux(sel, mux_false, mux_true)) + return true; /* we can handle Set for all modes and compares */ if (mux_is_set(sel, mux_true, mux_false)) return true; @@ -1954,7 +1969,7 @@ static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false, if (get_mode_size_bits(mode) > 32) return false; /* we can handle Abs for all modes and compares (except 64bit) */ - if (ir_mux_is_abs(sel, mux_true, mux_false) != 0) + if (ir_mux_is_abs(sel, mux_false, mux_true) != 0) return true; /* we can't handle MuxF yet */ if (mode_is_float(mode)) @@ -1998,22 +2013,9 @@ static int ia32_is_valid_clobber(const char *clobber) return ia32_get_clobber_register(clobber) != NULL; } -static ir_node *ia32_create_set(ir_node *cond) -{ - /* ia32-set function produces 8-bit results which have to be converted */ - ir_node *set = ir_create_mux_set(cond, mode_Bu); - ir_node *block = get_nodes_block(set); - return new_r_Conv(block, set, mode_Iu); -} - static void ia32_lower_for_target(void) { size_t i, n_irgs = get_irp_n_irgs(); - lower_mode_b_config_t lower_mode_b_config = { - mode_Iu, /* lowered mode */ - ia32_create_set, - 0, /* don't lower direct compares */ - }; /* perform doubleword lowering */ lwrdw_param_t lower_dw_params = { @@ -2023,8 +2025,16 @@ static void ia32_lower_for_target(void) &intrinsic_env, }; - /* lower compound param handling */ - lower_calls_with_compounds(LF_RETURN_HIDDEN); + ia32_create_opcodes(&ia32_irn_ops); + + /* lower compound param handling + * Note: we lower compound arguments ourself, since on ia32 we don't + * have hidden parameters but know where to find the structs on the stack. + * (This also forces us to always allocate space for the compound arguments + * on the callframe and we can't just use an arbitrary position on the + * stackframe) + */ + lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS); /* replace floating point operations by function calls */ if (ia32_cg_config.use_softfloat) { @@ -2037,10 +2047,18 @@ static void ia32_lower_for_target(void) for (i = 0; i < n_irgs; ++i) { ir_graph *irg = get_irp_irg(i); /* lower for mode_b stuff */ - ir_lower_mode_b(irg, &lower_mode_b_config); + ir_lower_mode_b(irg, mode_Iu); /* break up switches with wide ranges */ lower_switch(irg, 4, 256, false); } + + for (i = 0; i < n_irgs; ++i) { + ir_graph *irg = get_irp_irg(i); + /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs, + * so we can generate rep movs later, and turn all big CopyBs into + * memcpy calls. */ + lower_CopyB(irg, 64, 8193, true); + } } /** @@ -2048,25 +2066,27 @@ static void ia32_lower_for_target(void) */ static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee) { - ir_graph *irg = get_irn_irg(block); - ir_node *p = trampoline; - ir_mode *mode = get_irn_mode(p); - ir_node *st; + ir_graph *const irg = get_irn_irg(block); + ir_node * p = trampoline; + ir_mode *const mode = get_irn_mode(p); + ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu)); + ir_node *const four = new_r_Const_long(irg, mode_Iu, 4); + ir_node * st; /* mov ecx, */ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none); mem = new_r_Proj(st, mode_M, pn_Store_M); - p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode); + p = new_r_Add(block, p, one, mode); st = new_r_Store(block, mem, p, env, cons_none); mem = new_r_Proj(st, mode_M, pn_Store_M); - p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode); + p = new_r_Add(block, p, four, mode); /* jmp */ st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none); mem = new_r_Proj(st, mode_M, pn_Store_M); - p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode); + p = new_r_Add(block, p, one, mode); st = new_r_Store(block, mem, p, callee, cons_none); mem = new_r_Proj(st, mode_M, pn_Store_M); - p = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode); + p = new_r_Add(block, p, four, mode); return mem; } @@ -2104,13 +2124,21 @@ static const backend_params *ia32_get_libfirm_params(void) ia32_create_trampoline_fkt, 4 /* alignment of stack parameter */ }; + + if (ia32_mode_E == NULL) { + /* note mantissa is 64bit but with explicitely encoded 1 so the really + * usable part as counted by firm is only 63 bits */ + ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63); + ia32_type_E = new_type_primitive(ia32_mode_E); + set_type_size_bytes(ia32_type_E, 12); + set_type_alignment_bytes(ia32_type_E, 16); + } + ir_mode *mode_long_long - = new_ir_mode("long long", irms_int_number, 64, 1, irma_twos_complement, - 64); + = new_int_mode("long long", irma_twos_complement, 64, 1, 64); ir_type *type_long_long = new_type_primitive(mode_long_long); ir_mode *mode_unsigned_long_long - = new_ir_mode("unsigned long long", irms_int_number, 64, 0, - irma_twos_complement, 64); + = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64); ir_type *type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long); @@ -2127,13 +2155,8 @@ static const backend_params *ia32_get_libfirm_params(void) p.mode_float_arithmetic = NULL; p.type_long_double = NULL; } else { - p.mode_float_arithmetic = mode_E; - ir_mode *mode = new_ir_mode("long double", irms_float_number, 80, 1, - irma_ieee754, 0); - ir_type *type = new_type_primitive(mode); - set_type_size_bytes(type, 12); - set_type_alignment_bytes(type, 4); - p.type_long_double = type; + p.mode_float_arithmetic = ia32_mode_E; + p.type_long_double = ia32_type_E; } return &p; } @@ -2235,6 +2258,8 @@ const arch_isa_if_t ia32_isa_if = { ia32_finish, /* called before codegen */ ia32_emit, /* emit && done */ ia32_register_saved_by, + be_new_spill, + be_new_reload }; BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)