X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=eddb79f2764401894f0f2650f743fe709d095f81;hb=7f5fdce6e97b8c30069e9620bac5ec0b7c6d934f;hp=51fdb66161177078f81101921628af0b5f9ac6a7;hpb=df442858765f35e3715f262c8c130426a9294536;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 51fdb6616..eddb79f27 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -23,9 +23,7 @@ * @author Christian Wuerdig * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include "lc_opts.h" #include "lc_opts_enum.h" @@ -70,6 +68,7 @@ #include "../begnuas.h" #include "../bestate.h" #include "../beflags.h" +#include "../betranshlp.h" #include "bearch_ia32_t.h" @@ -90,6 +89,8 @@ #ifdef FIRM_GRGEN_BE #include "ia32_pbqp_transform.h" + +transformer_t be_transformer = TRANSFORMER_DEFAULT; #endif DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) @@ -120,7 +121,7 @@ static ia32_intrinsic_env_t intrinsic_env = { typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block); -static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, +static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, create_const_node_func func, const arch_register_t* reg) { @@ -131,7 +132,7 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, block = get_irg_start_block(cg->irg); res = func(NULL, cg->irg, block); - arch_set_irn_register(cg->arch_env, res, reg); + arch_set_irn_register(res, reg); *place = res; add_irn_dep(get_irg_end(cg->irg), res); @@ -180,10 +181,10 @@ ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) { /** * Returns the admissible noreg register node for input register pos of node irn. */ -ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) { - const arch_register_req_t *req; +static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) +{ + const arch_register_req_t *req = arch_get_register_req(irn, pos); - req = arch_get_register_req(cg->arch_env, irn, pos); assert(req != NULL && "Missing register requirements"); if (req->cls == &ia32_reg_classes[CLASS_ia32_gp]) return ia32_new_NoReg_gp(cg); @@ -278,10 +279,8 @@ static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg) static const arch_register_t *ia32_get_irn_reg(const ir_node *irn) { int pos = 0; - const arch_register_t *reg = NULL; if (is_Proj(irn)) { - if (get_irn_mode(irn) == mode_X) { return NULL; } @@ -291,19 +290,16 @@ static const arch_register_t *ia32_get_irn_reg(const ir_node *irn) } if (is_ia32_irn(irn)) { - const arch_register_t **slots; - slots = get_ia32_slots(irn); + const arch_register_t **slots = get_ia32_slots(irn); assert(pos < get_ia32_n_res(irn)); - reg = slots[pos]; + return slots[pos]; } else { - reg = ia32_get_firm_reg(irn, cur_reg_set); + return ia32_get_firm_reg(irn, cur_reg_set); } - - return reg; } static arch_irn_class_t ia32_classify(const ir_node *irn) { - arch_irn_class_t classification = arch_irn_class_normal; + arch_irn_class_t classification = 0; irn = skip_Proj_const(irn); @@ -311,16 +307,16 @@ static arch_irn_class_t ia32_classify(const ir_node *irn) { classification |= arch_irn_class_branch; if (! is_ia32_irn(irn)) - return classification & ~arch_irn_class_normal; + return classification; - if (is_ia32_Ld(irn)) - classification |= arch_irn_class_load; + if (is_ia32_is_reload(irn)) + classification |= arch_irn_class_reload; - if (is_ia32_St(irn)) - classification |= arch_irn_class_store; + if (is_ia32_is_spill(irn)) + classification |= arch_irn_class_spill; - if (is_ia32_need_stackent(irn)) - classification |= arch_irn_class_reload; + if (is_ia32_is_remat(irn)) + classification |= arch_irn_class_remat; return classification; } @@ -385,6 +381,9 @@ static void ia32_set_frame_offset(ir_node *irn, int bias) static int ia32_get_sp_bias(const ir_node *node) { + if (is_ia32_Call(node)) + return -(int)get_ia32_call_attr_const(node)->pop; + if (is_ia32_Push(node)) return 4; @@ -410,15 +409,16 @@ static void ia32_abi_dont_save_regs(void *self, pset *s) /** * Generate the routine prologue. * - * @param self The callback object. - * @param mem A pointer to the mem node. Update this if you define new memory. - * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes. + * @param self The callback object. + * @param mem A pointer to the mem node. Update this if you define new memory. + * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes. + * @param stack_bias Points to the current stack bias, can be modified if needed. * - * @return The register which shall be used as a stack frame base. + * @return The register which shall be used as a stack frame base. * * All nodes which define registers in @p reg_map must keep @p reg_map current. */ -static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map) +static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) { ia32_abi_env_t *env = self; ia32_code_gen_t *cg = ia32_current_cg; @@ -441,19 +441,22 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M); /* the push must have SP out register */ - arch_set_irn_register(arch_env, curr_sp, arch_env->sp); + arch_set_irn_register(curr_sp, arch_env->sp); set_ia32_flags(push, arch_irn_flags_ignore); + /* this modifies the stack bias, because we pushed 32bit */ + *stack_bias -= 4; + /* move esp to ebp */ curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp); be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp); - arch_set_irn_register(arch_env, curr_bp, arch_env->bp); + arch_set_irn_register(curr_bp, arch_env->bp); be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore); /* beware: the copy must be done before any other sp use */ curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp)); be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp); - arch_set_irn_register(arch_env, curr_sp, arch_env->sp); + arch_set_irn_register(curr_sp, arch_env->sp); be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore); be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp); @@ -493,7 +496,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ ir_node *leave; /* leave */ - leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp); + leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp); set_ia32_flags(leave, arch_irn_flags_ignore); curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame); curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack); @@ -506,7 +509,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ /* copy ebp to esp */ curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp); - arch_set_irn_register(arch_env, curr_sp, arch_env->sp); + arch_set_irn_register(curr_sp, arch_env->sp); be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore); /* pop ebp */ @@ -517,8 +520,8 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M); } - arch_set_irn_register(arch_env, curr_sp, arch_env->sp); - arch_set_irn_register(arch_env, curr_bp, arch_env->bp); + arch_set_irn_register(curr_sp, arch_env->sp); + arch_set_irn_register(curr_bp, arch_env->bp); } be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp); @@ -534,8 +537,8 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ */ static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg) { - ia32_abi_env_t *env = xmalloc(sizeof(env[0])); - be_abi_call_flags_t fl = be_abi_call_get_flags(call); + ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t); + be_abi_call_flags_t fl = be_abi_call_get_flags(call); env->flags = fl.bits; env->irg = irg; env->aenv = aenv; @@ -791,48 +794,69 @@ static ir_mode *get_spill_mode(const ir_node *node) */ static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode) { - if(mode_is_float(mode)) { - return mode == spillmode; - } else { - return 1; - } + return !mode_is_float(mode) || mode == spillmode; } /** * Check if irn can load its operand at position i from memory (source addressmode). - * @param self Pointer to irn ops itself * @param irn The irn to be checked * @param i The operands position * @return Non-Zero if operand can be loaded */ -static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) { - ir_node *op = get_irn_n(irn, i); - const ir_mode *mode = get_irn_mode(op); +static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) +{ + ir_node *op = get_irn_n(irn, i); + const ir_mode *mode = get_irn_mode(op); const ir_mode *spillmode = get_spill_mode(op); - if ( - (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */ - ! is_ia32_irn(irn) || /* must be an ia32 irn */ - get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */ - get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */ - ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */ - ! ia32_is_spillmode_compatible(mode, spillmode) || - is_ia32_use_frame(irn)) /* must not already use frame */ + if (!is_ia32_irn(irn) || /* must be an ia32 irn */ + get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */ + !ia32_is_spillmode_compatible(mode, spillmode) || + is_ia32_use_frame(irn)) /* must not already use frame */ return 0; - if (i == n_ia32_binary_left) { - const arch_register_req_t *req; - if(!is_ia32_commutative(irn)) - return 0; - /* we can't swap left/right for limited registers - * (As this (currently) breaks constraint handling copies) - */ - req = get_ia32_in_req(irn, n_ia32_binary_left); - if (req->type & arch_register_req_type_limited) { + switch (get_ia32_am_support(irn)) { + case ia32_am_none: return 0; - } + + case ia32_am_unary: + if (i != n_ia32_unary_op) + return 0; + break; + + case ia32_am_binary: + switch (i) { + case n_ia32_binary_left: { + const arch_register_req_t *req; + if (!is_ia32_commutative(irn)) + return 0; + + /* we can't swap left/right for limited registers + * (As this (currently) breaks constraint handling copies) + */ + req = get_ia32_in_req(irn, n_ia32_binary_left); + if (req->type & arch_register_req_type_limited) + return 0; + break; + } + + case n_ia32_binary_right: + break; + + default: + return 0; + } + break; + + default: + panic("Unknown AM type"); } + /* HACK: must not already use "real" memory. + * This can happen for Call and Div */ + if (!is_NoMem(get_irn_n(irn, n_ia32_mem))) + return 0; + return 1; } @@ -842,14 +866,8 @@ static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill, ir_mode *load_mode; ir_mode *dest_op_mode; - ia32_code_gen_t *cg = ia32_current_cg; - assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change"); - if (i == n_ia32_binary_left) { - ia32_swap_left_right(irn); - } - set_ia32_op_type(irn, ia32_AddrModeS); load_mode = get_irn_mode(get_irn_n(irn, i)); @@ -860,15 +878,20 @@ static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill, set_ia32_use_frame(irn); set_ia32_need_stackent(irn); - set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn))); - set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right)); - set_irn_n(irn, n_ia32_mem, spill); - set_ia32_is_reload(irn); - - /* immediates are only allowed on the right side */ - if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) { + if (i == n_ia32_binary_left && + get_ia32_am_support(irn) == ia32_am_binary && + /* immediates are only allowed on the right side */ + !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) { ia32_swap_left_right(irn); + i = n_ia32_binary_right; } + + assert(is_NoMem(get_irn_n(irn, n_ia32_mem))); + + set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn))); + set_irn_n(irn, n_ia32_mem, spill); + set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i)); + set_ia32_is_reload(irn); } static const be_abi_callbacks_t ia32_abi_callbacks = { @@ -916,7 +939,7 @@ static ir_entity *mcount = NULL; static void ia32_before_abi(void *self) { lower_mode_b_config_t lower_mode_b_config = { mode_Iu, /* lowered mode */ - mode_Bu, /* prefered mode for set */ + mode_Bu, /* preferred mode for set */ 0, /* don't lower direct compares */ }; ia32_code_gen_t *cg = self; @@ -936,8 +959,6 @@ static void ia32_before_abi(void *self) { } } -transformer_t be_transformer = TRANSFORMER_DEFAULT; - /** * Transforms the standard firm graph into * an ia32 firm graph @@ -960,24 +981,21 @@ static void ia32_prepare_graph(void *self) { be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched); switch (be_transformer) { - case TRANSFORMER_DEFAULT: - /* transform remaining nodes into assembler instructions */ - ia32_transform_graph(cg); - break; + case TRANSFORMER_DEFAULT: + /* transform remaining nodes into assembler instructions */ + ia32_transform_graph(cg); + break; #ifdef FIRM_GRGEN_BE - case TRANSFORMER_PBQP: - // disable CSE, because of two-step node-construction - set_opt_cse(0); - - /* transform nodes into assembler instructions by PBQP magic */ - ia32_transform_graph_by_pbqp(cg); - - set_opt_cse(1); - break; + case TRANSFORMER_PBQP: + case TRANSFORMER_RAND: + /* transform nodes into assembler instructions by PBQP magic */ + ia32_transform_graph_by_pbqp(cg); + break; #endif - default: panic("invalid transformer"); + default: + panic("invalid transformer"); } /* do local optimizations (mainly CSE) */ @@ -989,9 +1007,6 @@ static void ia32_prepare_graph(void *self) { /* optimize address mode */ ia32_optimize_graph(cg); - if (cg->dump) - be_dump(cg->irg, "-am", dump_ir_block_graph_sched); - /* do code placement, to optimize the position of constants */ place_code(cg->irg); @@ -999,14 +1014,7 @@ static void ia32_prepare_graph(void *self) { be_dump(cg->irg, "-place", dump_ir_block_graph_sched); } -/** - * Dummy functions for hooks we don't need but which must be filled. - */ -static void ia32_before_sched(void *self) { - (void) self; -} - -static void turn_back_am(ir_node *node) +ir_node *turn_back_am(ir_node *node) { ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); @@ -1014,40 +1022,34 @@ static void turn_back_am(ir_node *node) ir_node *base = get_irn_n(node, n_ia32_base); ir_node *index = get_irn_n(node, n_ia32_index); ir_node *mem = get_irn_n(node, n_ia32_mem); - ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg); - ir_node *load; - ir_node *load_res; - ir_node *mem_proj; - const ir_edge_t *edge; + ir_node *noreg; - load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); - load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); + ir_node *load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); + ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); ia32_copy_am_attrs(load, node); + if (is_ia32_is_reload(node)) + set_ia32_is_reload(load); set_irn_n(node, n_ia32_mem, new_NoMem()); - switch (get_ia32_am_arity(node)) { + switch (get_ia32_am_support(node)) { case ia32_am_unary: set_irn_n(node, n_ia32_unary_op, load_res); break; case ia32_am_binary: - if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) { - assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) || - is_ia32_Test(node) || is_ia32_Test8Bit(node)); + if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) { set_irn_n(node, n_ia32_binary_left, load_res); } else { set_irn_n(node, n_ia32_binary_right, load_res); } break; - case ia32_am_ternary: - set_irn_n(node, n_ia32_binary_right, load_res); - break; - - default: break; + default: + panic("Unknown AM type"); } - set_irn_n(node, n_ia32_base, noreg); + noreg = ia32_new_NoReg_gp(ia32_current_cg); + set_irn_n(node, n_ia32_base, noreg); set_irn_n(node, n_ia32_index, noreg); set_ia32_am_offs_int(node, 0); set_ia32_am_sc(node, NULL); @@ -1056,24 +1058,22 @@ static void turn_back_am(ir_node *node) /* rewire mem-proj */ if (get_irn_mode(node) == mode_T) { - mem_proj = NULL; + const ir_edge_t *edge; foreach_out_edge(node, edge) { ir_node *out = get_edge_src_irn(edge); - if(get_irn_mode(out) == mode_M) { - assert(mem_proj == NULL); - mem_proj = out; + if (get_irn_mode(out) == mode_M) { + set_Proj_pred(out, load); + set_Proj_proj(out, pn_ia32_Load_M); + break; } } - - if(mem_proj != NULL) { - set_Proj_pred(mem_proj, load); - set_Proj_proj(mem_proj, pn_ia32_Load_M); - } } set_ia32_op_type(node, ia32_Normal); if (sched_is_scheduled(node)) sched_add_before(node, load); + + return load_res; } static ir_node *flags_remat(ir_node *node, ir_node *after) @@ -1112,8 +1112,6 @@ static ir_node *flags_remat(ir_node *node, ir_node *after) /** * Called before the register allocator. - * Calculate a block schedule here. We need it for the x87 - * simulator and the emitter. */ static void ia32_before_ra(void *self) { ia32_code_gen_t *cg = self; @@ -1167,6 +1165,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { set_ia32_ls_mode(new_op, spillmode); set_ia32_frame_ent(new_op, ent); set_ia32_use_frame(new_op); + set_ia32_is_reload(new_op); DBG_OPT_RELOAD2LD(node, new_op); @@ -1178,8 +1177,8 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { } /* copy the register from the old node to the new Load */ - reg = arch_get_irn_register(cg->arch_env, node); - arch_set_irn_register(cg->arch_env, new_op, reg); + reg = arch_get_irn_register(node); + arch_set_irn_register(new_op, reg); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); @@ -1237,6 +1236,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) { set_ia32_ls_mode(store, mode); set_ia32_frame_ent(store, ent); set_ia32_use_frame(store); + set_ia32_is_spill(store); SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node)); DBG_OPT_SPILL2ST(node, store); @@ -1261,6 +1261,7 @@ static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpo set_ia32_use_frame(push); set_ia32_op_type(push, ia32_AddrModeS); set_ia32_ls_mode(push, mode_Is); + set_ia32_is_spill(push); sched_add_before(schedpoint, push); return push; @@ -1279,13 +1280,15 @@ static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoi set_ia32_use_frame(pop); set_ia32_op_type(pop, ia32_AddrModeD); set_ia32_ls_mode(pop, mode_Is); + set_ia32_is_reload(pop); sched_add_before(schedpoint, pop); return pop; } -static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) { +static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos) +{ ir_graph *irg = get_irn_irg(node); dbg_info *dbg = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); @@ -1294,7 +1297,7 @@ static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, ir_node *sp; sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos); - arch_set_irn_register(cg->arch_env, sp, spreg); + arch_set_irn_register(sp, spreg); return sp; } @@ -1334,12 +1337,12 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) { assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit"); push = create_push(cg, node, node, sp, mem, inent); - sp = create_spproj(cg, node, push, pn_ia32_Push_stack); + sp = create_spproj(node, push, pn_ia32_Push_stack); if(entsize == 8) { /* add another push after the first one */ push = create_push(cg, node, node, sp, mem, inent); add_ia32_am_offs_int(push, 4); - sp = create_spproj(cg, node, push, pn_ia32_Push_stack); + sp = create_spproj(node, push, pn_ia32_Push_stack); } set_irn_n(node, i, new_Bad()); @@ -1360,13 +1363,13 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) { assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit"); pop = create_pop(cg, node, node, sp, outent); - sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack); + sp = create_spproj(node, pop, pn_ia32_Pop_stack); if(entsize == 8) { add_ia32_am_offs_int(pop, 4); /* add another pop after the first one */ pop = create_pop(cg, node, node, sp, outent); - sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack); + sp = create_spproj(node, pop, pn_ia32_Pop_stack); } pops[i] = pop; @@ -1421,52 +1424,73 @@ static void ia32_after_ra_walker(ir_node *block, void *env) { */ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) { - be_fec_env_t *env = data; + be_fec_env_t *env = data; + const ir_mode *mode; + int align; if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) { - const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node)); - int align = get_mode_size_bytes(mode); - be_node_needs_frame_entity(env, node, mode, align); - } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL - && is_ia32_use_frame(node)) { - if (is_ia32_need_stackent(node) || is_ia32_Load(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - const ia32_attr_t *attr = get_ia32_attr_const(node); - int align; - - if (is_ia32_is_reload(node)) { - mode = get_spill_mode_mode(mode); + mode = get_spill_mode_mode(get_irn_mode(node)); + align = get_mode_size_bytes(mode); + } else if (is_ia32_irn(node) && + get_ia32_frame_ent(node) == NULL && + is_ia32_use_frame(node)) { + if (is_ia32_need_stackent(node)) + goto need_stackent; + + switch (get_ia32_irn_opcode(node)) { +need_stackent: + case iro_ia32_Load: { + const ia32_attr_t *attr = get_ia32_attr_const(node); + + if (attr->data.need_32bit_stackent) { + mode = mode_Is; + } else if (attr->data.need_64bit_stackent) { + mode = mode_Ls; + } else { + mode = get_ia32_ls_mode(node); + if (is_ia32_is_reload(node)) + mode = get_spill_mode_mode(mode); + } + align = get_mode_size_bytes(mode); + break; } - if(attr->data.need_64bit_stackent) { - mode = mode_Ls; + case iro_ia32_vfild: + case iro_ia32_vfld: + case iro_ia32_xLoad: { + mode = get_ia32_ls_mode(node); + align = 4; + break; } - if(attr->data.need_32bit_stackent) { - mode = mode_Is; + + case iro_ia32_FldCW: { + /* although 2 byte would be enough 4 byte performs best */ + mode = mode_Iu; + align = 4; + break; } - align = get_mode_size_bytes(mode); - be_node_needs_frame_entity(env, node, mode, align); - } else if (is_ia32_vfild(node) || is_ia32_xLoad(node) - || is_ia32_vfld(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - int align = 4; - be_node_needs_frame_entity(env, node, mode, align); - } else if(is_ia32_FldCW(node)) { - /* although 2 byte would be enough 4 byte performs best */ - const ir_mode *mode = mode_Iu; - int align = 4; - be_node_needs_frame_entity(env, node, mode, align); - } else { + + default: #ifndef NDEBUG - assert(is_ia32_St(node) || - is_ia32_xStoreSimple(node) || - is_ia32_vfst(node) || - is_ia32_vfist(node) || - is_ia32_vfisttp(node) || - is_ia32_FnstCW(node)); + panic("unexpected frame user while collection frame entity nodes"); + + case iro_ia32_FnstCW: + case iro_ia32_Store8Bit: + case iro_ia32_Store: + case iro_ia32_fst: + case iro_ia32_fstp: + case iro_ia32_vfist: + case iro_ia32_vfisttp: + case iro_ia32_vfst: + case iro_ia32_xStore: + case iro_ia32_xStoreSimple: #endif + return; } + } else { + return; } + be_node_needs_frame_entity(env, node, mode, align); } /** @@ -1499,7 +1523,7 @@ static void ia32_finish(void *self) { /* we might have to rewrite x87 virtual registers */ if (cg->do_x87_sim) { - x87_simulate_graph(cg->arch_env, cg->birg); + x87_simulate_graph(cg->birg); } /* do peephole optimisations */ @@ -1547,8 +1571,7 @@ static ir_node *ia32_get_pic_base(void *self) { get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block); cg->get_eip = get_eip; - add_irn_dep(get_eip, get_irg_frame(cg->irg)); - + be_dep_on_frame(get_eip); return get_eip; } @@ -1560,7 +1583,6 @@ static const arch_code_generator_if_t ia32_code_gen_if = { ia32_before_abi, /* before abi introduce hook */ ia32_prepare_graph, NULL, /* spill */ - ia32_before_sched, /* before scheduling hook */ ia32_before_ra, /* before register allocation hook */ ia32_after_ra, /* after register allocation hook */ ia32_finish, /* called before codegen */ @@ -1572,13 +1594,12 @@ static const arch_code_generator_if_t ia32_code_gen_if = { */ static void *ia32_cg_init(be_irg_t *birg) { ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env; - ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg)); + ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t); cg->impl = &ia32_code_gen_if; cg->irg = birg->irg; cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024); cg->isa = isa; - cg->arch_env = birg->main_env->arch_env; cg->birg = birg; cg->blk_sched = NULL; cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; @@ -1656,7 +1677,7 @@ static ia32_isa_t ia32_isa_template = { &ia32_gp_regs[REG_ESP], /* stack pointer register */ &ia32_gp_regs[REG_EBP], /* base pointer register */ -1, /* stack direction */ - 4, /* power of two stack alignment, 2^4 == 16 */ + 2, /* power of two stack alignment, 2^2 == 4 */ NULL, /* main environment */ 7, /* costs for a spill instruction */ 5, /* costs for a reload instruction */ @@ -1734,7 +1755,7 @@ static arch_env_t *ia32_init(FILE *file_handle) { set_tarval_output_modes(); - isa = xmalloc(sizeof(*isa)); + isa = XMALLOC(ia32_isa_t); memcpy(isa, &ia32_isa_template, sizeof(*isa)); if(mode_fpcw == NULL) { @@ -1757,7 +1778,7 @@ static arch_env_t *ia32_init(FILE *file_handle) { ia32_build_8bit_reg_map_high(isa->regs_8bit_high); #ifndef NDEBUG - isa->name_obst = xmalloc(sizeof(*isa->name_obst)); + isa->name_obst = XMALLOC(struct obstack); obstack_init(isa->name_obst); #endif /* NDEBUG */ @@ -1879,7 +1900,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, call_flags.bits.store_args_sequential = 0; /* call_flags.bits.try_omit_fp not changed: can handle both settings */ call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */ - call_flags.bits.call_has_imm = 1; /* No call immediates, we handle this by ourselves */ + call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */ /* set parameter passing style */ be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks); @@ -2078,16 +2099,13 @@ static const be_execution_unit_t ***ia32_get_allowed_execution_units( if (is_ia32_irn(irn)) { ret = get_ia32_exec_units(irn); - } - else if (is_be_node(irn)) { - if (be_is_Call(irn) || be_is_Return(irn)) { + } else if (is_be_node(irn)) { + if (be_is_Return(irn)) { ret = _units_callret; - } - else if (be_is_Barrier(irn)) { + } else if (be_is_Barrier(irn)) { ret = _units_dummy; - } - else { - ret = _units_other; + } else { + ret = _units_other; } } else { @@ -2115,6 +2133,13 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) return NULL; } +static void ia32_mark_remat(const void *self, ir_node *node) { + (void) self; + if (is_ia32_irn(node)) { + set_ia32_is_remat(node); + } +} + /** * Allows or disallows the creation of Psi nodes for the given Phi nodes. * @return 1 if allowed, 0 otherwise @@ -2319,21 +2344,24 @@ static lc_opt_enum_int_var_t gas_var = { (int*) &be_gas_flavour, gas_items }; +#ifdef FIRM_GRGEN_BE static const lc_opt_enum_int_items_t transformer_items[] = { { "default", TRANSFORMER_DEFAULT }, -#ifdef FIRM_GRGEN_BE { "pbqp", TRANSFORMER_PBQP }, -#endif + { "random", TRANSFORMER_RAND }, { NULL, 0 } }; static lc_opt_enum_int_var_t transformer_var = { (int*)&be_transformer, transformer_items }; +#endif static const lc_opt_table_entry_t ia32_options[] = { LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var), +#ifdef FIRM_GRGEN_BE LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var), +#endif LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls", &ia32_isa_template.arch_env.stack_alignment), LC_OPT_LAST @@ -2354,6 +2382,7 @@ const arch_isa_if_t ia32_isa_if = { ia32_get_allowed_execution_units, ia32_get_machine, ia32_get_irg_list, + ia32_mark_remat, ia32_parse_asm_constraint, ia32_is_valid_clobber };