X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=d7749f42bc23ecc8a993a49e169ecda6d4bb18e3;hb=d9ebcc506768b24fb6378dc7cae91002be410eec;hp=88d89c182521c7180a960edab32afb217da5c860;hpb=b24c359be385d38d535efe35df5a937a8ee9cc0c;p=libfirm

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 88d89c182..d7749f42b 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -97,7 +97,7 @@ transformer_t be_transformer = TRANSFORMER_DEFAULT;
 
 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
 
-ir_mode         *mode_fpcw       = NULL;
+ir_mode         *ia32_mode_fpcw       = NULL;
 
 /** The current omit-fp state */
 static unsigned ia32_curr_fp_ommitted  = 0;
@@ -193,7 +193,7 @@ static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
 
 static arch_irn_class_t ia32_classify(const ir_node *irn)
 {
-	arch_irn_class_t classification = 0;
+	arch_irn_class_t classification = arch_irn_class_none;
 
 	assert(is_ia32_irn(irn));
 
@@ -276,7 +276,7 @@ static int ia32_get_sp_bias(const ir_node *node)
  */
 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
 {
-	ia32_abi_env_t   *env      = self;
+	ia32_abi_env_t   *env      = (ia32_abi_env_t*)self;
 	ir_graph         *irg      = env->irg;
 	const arch_env_t *arch_env = be_get_irg_arch_env(irg);
 
@@ -334,7 +334,7 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
  */
 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
 {
-	ia32_abi_env_t   *env      = self;
+	ia32_abi_env_t   *env      = (ia32_abi_env_t*)self;
 	const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
 	ir_node          *curr_sp  = be_abi_reg_map_get(reg_map, arch_env->sp);
 	ir_node          *curr_bp  = be_abi_reg_map_get(reg_map, arch_env->bp);
@@ -440,7 +440,7 @@ static void ia32_build_between_type(void)
  */
 static ir_type *ia32_abi_get_between_type(void *self)
 {
-	ia32_abi_env_t *env = self;
+	ia32_abi_env_t *env = (ia32_abi_env_t*)self;
 
 	ia32_build_between_type();
 	return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
@@ -851,7 +851,7 @@ static void ia32_prepare_graph(ir_graph *irg)
 		dump_ir_graph(irg, "place");
 }
 
-ir_node *turn_back_am(ir_node *node)
+ir_node *ia32_turn_back_am(ir_node *node)
 {
 	dbg_info *dbgi  = get_irn_dbg_info(node);
 	ir_graph *irg   = get_irn_irg(node);
@@ -929,7 +929,7 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
 	type = get_ia32_op_type(node);
 	switch (type) {
 		case ia32_AddrModeS:
-			turn_back_am(node);
+			ia32_turn_back_am(node);
 			break;
 
 		case ia32_AddrModeD:
@@ -1250,7 +1250,7 @@ static void ia32_after_ra_walker(ir_node *block, void *env)
  */
 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
 {
-	be_fec_env_t  *env = data;
+	be_fec_env_t  *env = (be_fec_env_t*)data;
 	const ir_mode *mode;
 	int            align;
 
@@ -1348,7 +1348,7 @@ static void ia32_finish(ir_graph *irg)
 
 	/* we might have to rewrite x87 virtual registers */
 	if (irg_data->do_x87_sim) {
-		x87_simulate_graph(irg);
+		ia32_x87_simulate_graph(irg);
 	}
 
 	/* do peephole optimisations */
@@ -1434,7 +1434,7 @@ static void set_tarval_output_modes(void)
 	}
 }
 
-const arch_isa_if_t ia32_isa_if;
+extern const arch_isa_if_t ia32_isa_if;
 
 /**
  * The template that generates a new ISA object.
@@ -1446,6 +1446,8 @@ static ia32_isa_t ia32_isa_template = {
 		&ia32_isa_if,            /* isa interface implementation */
 		N_IA32_REGISTERS,
 		ia32_registers,
+		N_IA32_CLASSES,
+		ia32_reg_classes,
 		&ia32_registers[REG_ESP],  /* stack pointer register */
 		&ia32_registers[REG_EBP],  /* base pointer register */
 		&ia32_reg_classes[CLASS_ia32_gp],  /* static link pointer register class */
@@ -1516,30 +1518,21 @@ static void init_asm_constraints(void)
  */
 static arch_env_t *ia32_init(FILE *file_handle)
 {
-	static int inited = 0;
-	ia32_isa_t *isa;
+	ia32_isa_t *isa = XMALLOC(ia32_isa_t);
 	int        i, n;
 
-	if (inited)
-		return NULL;
-	inited = 1;
-
 	set_tarval_output_modes();
 
-	isa = XMALLOC(ia32_isa_t);
 	memcpy(isa, &ia32_isa_template, sizeof(*isa));
 
-	if (mode_fpcw == NULL) {
-		mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+	if (ia32_mode_fpcw == NULL) {
+		ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
 	}
 
 	ia32_register_init();
 	ia32_create_opcodes(&ia32_irn_ops);
 
 	be_emit_init(file_handle);
-	isa->regs_16bit     = pmap_create();
-	isa->regs_8bit      = pmap_create();
-	isa->regs_8bit_high = pmap_create();
 	isa->types          = pmap_create();
 	isa->tv_ent         = pmap_create();
 	isa->cpu            = ia32_init_machine_description();
@@ -1574,14 +1567,11 @@ static arch_env_t *ia32_init(FILE *file_handle)
  */
 static void ia32_done(void *self)
 {
-	ia32_isa_t *isa = self;
+	ia32_isa_t *isa = (ia32_isa_t*)self;
 
 	/* emit now all global declarations */
 	be_gas_emit_decls(isa->base.main_env);
 
-	pmap_destroy(isa->regs_16bit);
-	pmap_destroy(isa->regs_8bit);
-	pmap_destroy(isa->regs_8bit_high);
 	pmap_destroy(isa->tv_ent);
 	pmap_destroy(isa->types);
 
@@ -1591,28 +1581,6 @@ static void ia32_done(void *self)
 }
 
 
-/**
- * Return the number of register classes for this architecture.
- * We report always these:
- *  - the general purpose registers
- *  - the SSE floating point register set
- *  - the virtual floating point registers
- *  - the SSE vector register set
- */
-static unsigned ia32_get_n_reg_class(void)
-{
-	return N_IA32_CLASSES;
-}
-
-/**
- * Return the register class for index i.
- */
-static const arch_register_class_t *ia32_get_reg_class(unsigned i)
-{
-	assert(i < N_IA32_CLASSES);
-	return &ia32_reg_classes[i];
-}
-
 /**
  * Get the register class which shall be used to store a value of a given mode.
  * @param self The this pointer.
@@ -1882,7 +1850,7 @@ static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
 	 *  or max(a, b) = a >= b ? a : b
 	 * (Note we only handle float min/max here)
 	 */
-	pnc = get_Proj_proj(sel);
+	pnc = get_Proj_pn_cmp(sel);
 	switch (pnc) {
 	case pn_Cmp_Ge:
 	case pn_Cmp_Gt:
@@ -2118,17 +2086,17 @@ static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node
 	ir_node  *st;
 
 	/* mov  ecx,<env> */
-	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), 0);
+	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
 	mem = new_r_Proj(st, mode_M, pn_Store_M);
 	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
-	st  = new_r_Store(block, mem, p, env, 0);
+	st  = new_r_Store(block, mem, p, env, cons_none);
 	mem = new_r_Proj(st, mode_M, pn_Store_M);
 	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
 	/* jmp  <callee> */
-	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), 0);
+	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
 	mem = new_r_Proj(st, mode_M, pn_Store_M);
 	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
-	st  = new_r_Store(block, mem, p, callee, 0);
+	st  = new_r_Store(block, mem, p, callee, cons_none);
 	mem = new_r_Proj(st, mode_M, pn_Store_M);
 	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
 
@@ -2143,7 +2111,7 @@ static const backend_params *ia32_get_libfirm_params(void)
 	static const ir_settings_arch_dep_t ad = {
 		1,                   /* also use subs */
 		4,                   /* maximum shifts */
-		31,                  /* maximum shift amount */
+		63,                  /* maximum shift amount */
 		ia32_evaluate_insn,  /* evaluate the instruction sequence */
 
 		1,  /* allow Mulhs */
@@ -2214,8 +2182,6 @@ const arch_isa_if_t ia32_isa_if = {
 	ia32_init,
 	ia32_done,
 	ia32_handle_intrinsics,
-	ia32_get_n_reg_class,
-	ia32_get_reg_class,
 	ia32_get_reg_class_for_mode,
 	ia32_get_call_abi,
 	ia32_get_reg_class_alignment,