X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=b107c43ebd741d3de9a395b9df435d34ae825186;hb=f98934273a33986d27bb93ca8ef3ee32580f2705;hp=96b19317bd5b2b864e5266a65d33fbd09956b9c6;hpb=97c79556e25a27333a20f9f8d1094e7b7b3792ec;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 96b19317b..b107c43eb 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -27,12 +27,13 @@ #include "config.h" #endif -#include -#include +#include "lc_opts.h" +#include "lc_opts_enum.h" #include #include "pseudo_irg.h" +#include "irarch.h" #include "irgwalk.h" #include "irprog.h" #include "irprintf.h" @@ -42,11 +43,15 @@ #include "irgopt.h" #include "irbitset.h" #include "irgopt.h" +#include "irdump_grgen.h" #include "pdeq.h" #include "pset.h" #include "debug.h" #include "error.h" #include "xmalloc.h" +#include "irtools.h" +#include "iroptimize.h" +#include "instrument.h" #include "../beabi.h" #include "../beirg_t.h" @@ -64,6 +69,7 @@ #include "../bemodule.h" #include "../begnuas.h" #include "../bestate.h" +#include "../beflags.h" #include "bearch_ia32_t.h" @@ -79,13 +85,37 @@ #include "ia32_finish.h" #include "ia32_util.h" #include "ia32_fpu.h" +#include "ia32_architecture.h" + +#ifdef FIRM_GRGEN_BE +#include "ia32_pbqp_transform.h" +#endif DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) /* TODO: ugly */ static set *cur_reg_set = NULL; -ir_mode *mode_fpcw = NULL; +ir_mode *mode_fpcw = NULL; +ia32_code_gen_t *ia32_current_cg = NULL; + +/** + * The environment for the intrinsic mapping. + */ +static ia32_intrinsic_env_t intrinsic_env = { + NULL, /* the isa */ + NULL, /* the irg, these entities belong to */ + NULL, /* entity for first div operand (move into FPU) */ + NULL, /* entity for second div operand (move into FPU) */ + NULL, /* entity for converts ll -> d */ + NULL, /* entity for converts d -> ll */ + NULL, /* entity for __divdi3 library call */ + NULL, /* entity for __moddi3 library call */ + NULL, /* entity for __udivdi3 library call */ + NULL, /* entity for __umoddi3 library call */ + NULL, /* bias value for conversion from float to unsigned 64 */ +}; + typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block); @@ -125,11 +155,6 @@ ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) { &ia32_xmm_regs[REG_XMM_NOREG]); } -/* Creates the unique per irg FP NoReg node. */ -ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) { - return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg); -} - ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) { return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP, &ia32_gp_regs[REG_GP_UKNWN]); @@ -162,7 +187,11 @@ ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) { if (req->cls == &ia32_reg_classes[CLASS_ia32_gp]) return ia32_new_NoReg_gp(cg); - return ia32_new_NoReg_fp(cg); + if (ia32_cg_config.use_sse2) { + return ia32_new_NoReg_xmm(cg); + } else { + return ia32_new_NoReg_vfp(cg); + } } /************************************************** @@ -183,9 +212,11 @@ ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) { */ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, const ir_node *node, - int pos) { + int pos) +{ long node_pos = pos == -1 ? 0 : pos; ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node); + (void) self; if (is_Block(node) || mode == mode_X) { return arch_no_register_req; @@ -225,8 +256,11 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, return arch_no_register_req; } -static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) { +static void ia32_set_irn_reg(const void *self, ir_node *irn, + const arch_register_t *reg) +{ int pos = 0; + (void) self; if (get_irn_mode(irn) == mode_X) { return; @@ -247,9 +281,12 @@ static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register } } -static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) { +static const arch_register_t *ia32_get_irn_reg(const void *self, + const ir_node *irn) +{ int pos = 0; const arch_register_t *reg = NULL; + (void) self; if (is_Proj(irn)) { @@ -264,6 +301,7 @@ static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node * if (is_ia32_irn(irn)) { const arch_register_t **slots; slots = get_ia32_slots(irn); + assert(pos < get_ia32_n_res(irn)); reg = slots[pos]; } else { reg = ia32_get_firm_reg(irn, cur_reg_set); @@ -274,6 +312,7 @@ static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node * static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) { arch_irn_class_t classification = arch_irn_class_normal; + (void) self; irn = skip_Proj_const(irn); @@ -283,9 +322,6 @@ static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) { if (! is_ia32_irn(irn)) return classification & ~arch_irn_class_normal; - if (is_ia32_Cnst(irn)) - classification |= arch_irn_class_const; - if (is_ia32_Ld(irn)) classification |= arch_irn_class_load; @@ -300,6 +336,7 @@ static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) { static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) { arch_irn_flags_t flags = arch_irn_flags_none; + (void) self; if (is_Unknown(irn)) return arch_irn_flags_ignore; @@ -332,47 +369,43 @@ typedef struct { } ia32_abi_env_t; static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) { + (void) self; return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL; } static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) { + (void) self; set_ia32_frame_ent(irn, ent); } -static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) { +static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) +{ const ia32_irn_ops_t *ops = self; - if (get_ia32_frame_ent(irn)) { - ia32_am_flavour_t am_flav; + if (get_ia32_frame_ent(irn) == NULL) + return; - if (is_ia32_Pop(irn)) { - int omit_fp = be_abi_omit_fp(ops->cg->birg->abi); - if (omit_fp) { - /* Pop nodes modify the stack pointer before calculating the destination - * address, so fix this here - */ - bias -= 4; - } + if (is_ia32_Pop(irn)) { + int omit_fp = be_abi_omit_fp(ops->cg->birg->abi); + if (omit_fp) { + /* Pop nodes modify the stack pointer before calculating the + * destination address, so fix this here + */ + bias -= 4; } - - am_flav = get_ia32_am_flavour(irn); - am_flav |= ia32_O; - set_ia32_am_flavour(irn, am_flav); - - add_ia32_am_offs_int(irn, bias); } + add_ia32_am_offs_int(irn, bias); } -static int ia32_get_sp_bias(const void *self, const ir_node *irn) { - if(is_Proj(irn)) { - long proj = get_Proj_proj(irn); - ir_node *pred = get_Proj_pred(irn); +static int ia32_get_sp_bias(const void *self, const ir_node *node) +{ + (void) self; - if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack) - return 4; - if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack) - return -4; - } + if (is_ia32_Push(node)) + return 4; + + if (is_ia32_Pop(node)) + return -4; return 0; } @@ -418,7 +451,7 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore); /* push ebp */ - push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem); + push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp); curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack); *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M); @@ -465,36 +498,39 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ if (env->flags.try_omit_fp) { /* simply remove the stack frame here */ - curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK); + curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0); add_irn_dep(curr_sp, *mem); } else { - const ia32_isa_t *isa = (ia32_isa_t *)env->isa; - ia32_code_gen_t *cg = isa->cg; - ir_mode *mode_bp = env->isa->bp->reg_class->mode; + ir_mode *mode_bp = env->isa->bp->reg_class->mode; + ir_graph *irg = current_ir_graph; - /* gcc always emits a leave at the end of a routine */ - if (1 || ARCH_AMD(isa->opt_arch)) { + if (ia32_cg_config.use_leave) { ir_node *leave; /* leave */ - leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp); + leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp); set_ia32_flags(leave, arch_irn_flags_ignore); - curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame); - curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack); + curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame); + curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack); } else { - ir_node *noreg = ia32_new_NoReg_gp(cg); ir_node *pop; + /* the old SP is not needed anymore (kill the proj) */ + assert(is_Proj(curr_sp)); + be_kill_node(curr_sp); + /* copy ebp to esp */ - curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem); + curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp); + arch_set_irn_register(env->aenv, curr_sp, env->isa->sp); + be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore); /* pop ebp */ - pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem); + pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp); set_ia32_flags(pop, arch_irn_flags_ignore); - curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res); - curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack); + curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res); + curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack); - *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M); + *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M); } arch_set_irn_register(env->aenv, curr_sp, env->isa->sp); arch_set_irn_register(env->aenv, curr_bp, env->isa->bp); @@ -582,9 +618,9 @@ static ir_type *ia32_abi_get_between_type(void *self) */ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn) { - int cost; + int cost; ia32_op_type_t op_tp; - const ia32_irn_ops_t *ops = self; + (void) self; if (is_Proj(irn)) return 0; @@ -598,22 +634,25 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn) if (is_ia32_CopyB(irn)) { cost = 250; - if (ARCH_INTEL(ops->cg->arch)) - cost += 150; } else if (is_ia32_CopyB_i(irn)) { - int size = get_tarval_long(get_ia32_Immop_tarval(irn)); + int size = get_ia32_copyb_size(irn); cost = 20 + (int)ceil((4/3) * size); - if (ARCH_INTEL(ops->cg->arch)) - cost += 150; } /* in case of address mode operations add additional cycles */ else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) { /* - In case of stack access add 5 cycles (we assume stack is in cache), - other memory operations cost 20 cycles. + In case of stack access and access to fixed addresses add 5 cycles + (we assume they are in cache), other memory operations cost 20 + cycles. */ - cost += is_ia32_use_frame(irn) ? 5 : 20; + if(is_ia32_use_frame(irn) || + (is_ia32_NoReg_GP(get_irn_n(irn, 0)) && + is_ia32_NoReg_GP(get_irn_n(irn, 1)))) { + cost += 5; + } else { + cost += 20; + } } return cost; @@ -634,19 +673,25 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in ir_mode *irn_mode; ir_node *block, *noreg, *nomem; dbg_info *dbg; + (void) self; /* we cannot invert non-ia32 irns */ if (! is_ia32_irn(irn)) return NULL; /* operand must always be a real operand (not base, index or mem) */ - if (i != 2 && i != 3) + if (i != n_ia32_binary_left && i != n_ia32_binary_right) return NULL; /* we don't invert address mode operations */ if (get_ia32_op_type(irn) != ia32_Normal) return NULL; + /* TODO: adjust for new immediates... */ + ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n", + irn); + return NULL; + irg = get_irn_irg(irn); block = get_nodes_block(irn); mode = get_irn_mode(irn); @@ -662,10 +707,11 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in switch (get_ia32_irn_opcode(irn)) { case iro_ia32_Add: +#if 0 if (get_ia32_immop_type(irn) == ia32_ImmConst) { /* we have an add with a const here */ /* invers == add with negated const */ - inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem); + inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); inverse->costs += 1; copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn); set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn))); @@ -674,55 +720,60 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) { /* we have an add with a symconst here */ /* invers == sub with const */ - inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem); + inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); inverse->costs += 2; copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn); } else { /* normal add: inverse == sub */ - inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem); + inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1)); inverse->costs += 2; } +#endif break; case iro_ia32_Sub: +#if 0 if (get_ia32_immop_type(irn) != ia32_ImmNone) { /* we have a sub with a const/symconst here */ /* invers == add with this const */ - inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem); + inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1; copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn); } else { /* normal sub */ - if (i == 2) { - inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem); + if (i == n_ia32_binary_left) { + inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3)); } else { - inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem); + inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn); } inverse->costs += 1; } +#endif break; case iro_ia32_Xor: +#if 0 if (get_ia32_immop_type(irn) != ia32_ImmNone) { /* xor with const: inverse = xor */ - inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem); + inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1; copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn); } else { /* normal xor */ - inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem); + inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i)); inverse->costs += 1; } +#endif break; case iro_ia32_Not: { - inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem); + inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn); inverse->costs += 1; break; } case iro_ia32_Neg: { - inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem); + inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn); inverse->costs += 1; break; } @@ -752,7 +803,7 @@ static ir_mode *get_spill_mode(const ir_node *node) } /** - * Checks wether an addressmode reload for a node with mode mode is compatible + * Checks whether an addressmode reload for a node with mode mode is compatible * with a spillslot of mode spill_mode */ static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode) @@ -765,7 +816,7 @@ static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spil } /** - * Check if irn can load it's operand at position i from memory (source addressmode). + * Check if irn can load its operand at position i from memory (source addressmode). * @param self Pointer to irn ops itself * @param irn The irn to be checked * @param i The operands position @@ -775,44 +826,58 @@ static int ia32_possible_memory_operand(const void *self, const ir_node *irn, un ir_node *op = get_irn_n(irn, i); const ir_mode *mode = get_irn_mode(op); const ir_mode *spillmode = get_spill_mode(op); - - if (! is_ia32_irn(irn) || /* must be an ia32 irn */ - get_irn_arity(irn) != 5 || /* must be a binary operation */ - get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */ - ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */ - ! ia32_is_spillmode_compatible(mode, spillmode) || - (i != 2 && i != 3) || /* a "real" operand position must be requested */ - (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */ - is_ia32_use_frame(irn)) /* must not already use frame */ + (void) self; + + if (! is_ia32_irn(irn) || /* must be an ia32 irn */ + get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */ + get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */ + ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */ + ! ia32_is_spillmode_compatible(mode, spillmode) || + (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */ + is_ia32_use_frame(irn)) /* must not already use frame */ return 0; + if (i == n_ia32_binary_left) { + const arch_register_req_t *req; + if(!is_ia32_commutative(irn)) + return 0; + /* we can't swap left/right for limited registers + * (As this (currently) breaks constraint handling copies) + */ + req = get_ia32_in_req(irn, n_ia32_binary_left); + if(req->type & arch_register_req_type_limited) { + return 0; + } + } + return 1; } -static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) { +static void ia32_perform_memory_operand(const void *self, ir_node *irn, + ir_node *spill, unsigned int i) +{ const ia32_irn_ops_t *ops = self; ia32_code_gen_t *cg = ops->cg; assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change"); - if (i == 2) { - ir_node *tmp = get_irn_n(irn, 3); - set_irn_n(irn, 3, get_irn_n(irn, 2)); - set_irn_n(irn, 2, tmp); + if (i == n_ia32_binary_left) { + ia32_swap_left_right(irn); } - set_ia32_am_support(irn, ia32_am_Source); set_ia32_op_type(irn, ia32_AddrModeS); - set_ia32_am_flavour(irn, ia32_B); set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i))); set_ia32_use_frame(irn); set_ia32_need_stackent(irn); - set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn))); - set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3)); - set_irn_n(irn, 4, spill); + set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn))); + set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right)); + set_irn_n(irn, n_ia32_mem, spill); - //FIXME DBG_OPT_AM_S(reload, irn); + /* immediates are only allowed on the right side */ + if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) { + ia32_swap_left_right(irn); + } } static const be_abi_callbacks_t ia32_abi_callbacks = { @@ -842,7 +907,7 @@ static const arch_irn_ops_if_t ia32_irn_ops_if = { ia32_perform_memory_operand, }; -ia32_irn_ops_t ia32_irn_ops = { +static ia32_irn_ops_t ia32_irn_ops = { &ia32_irn_ops_if, NULL }; @@ -860,6 +925,33 @@ ia32_irn_ops_t ia32_irn_ops = { * |___/ **************************************************/ +static ir_entity *mcount = NULL; + +#define ID(s) new_id_from_chars(s, sizeof(s) - 1) + +static void ia32_before_abi(void *self) { + lower_mode_b_config_t lower_mode_b_config = { + mode_Iu, /* lowered mode */ + mode_Bu, /* prefered mode for set */ + 0, /* don't lower direct compares */ + }; + ia32_code_gen_t *cg = self; + + ir_lower_mode_b(cg->irg, &lower_mode_b_config); + if (cg->dump) + be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched); + if (cg->gprof) { + if (mcount == NULL) { + ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0); + mcount = new_entity(get_glob_type(), ID("mcount"), tp); + /* FIXME: enter the right ld_ident here */ + set_entity_ld_ident(mcount, get_entity_ident(mcount)); + set_entity_visibility(mcount, visibility_external_allocated); + } + instrument_initcall(cg->irg, mcount); + } +} + /** * Transforms the standard firm graph into * an ia32 firm graph @@ -867,18 +959,33 @@ ia32_irn_ops_t ia32_irn_ops = { static void ia32_prepare_graph(void *self) { ia32_code_gen_t *cg = self; - /* transform psi condition trees */ - ia32_pre_transform_phase(cg); + /* do local optimisations */ + optimize_graph_df(cg->irg); + + /* TODO: we often have dead code reachable through out-edges here. So for + * now we rebuild edges (as we need correct user count for code selection) + */ +#if 1 + edges_deactivate(cg->irg); + edges_activate(cg->irg); +#endif + + if (cg->dump) + be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched); + +#ifdef FIRM_GRGEN_BE + /* transform nodes into assembler instructions by PBQP magic */ + ia32_transform_graph_by_pbqp(cg); +#endif - /* transform all remaining nodes */ + if (cg->dump) + be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched); + + /* transform remaining nodes into assembler instructions */ ia32_transform_graph(cg); - //add_fpu_edges(cg->birg); - // Matze: disabled for now. Because after transformation start block has no - // self-loop anymore so it might be merged with its successor block. This - // will bring several nodes to the startblock which sometimes get scheduled - // before the initial IncSP/Barrier - local_optimize_graph(cg->irg); + /* do local optimisations (mainly CSE) */ + optimize_graph_df(cg->irg); if (cg->dump) be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched); @@ -900,77 +1007,108 @@ static void ia32_prepare_graph(void *self) { * Dummy functions for hooks we don't need but which must be filled. */ static void ia32_before_sched(void *self) { + (void) self; } -static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) { - int i, arity; - ir_mode *mode; - ir_node *mem_proj = NULL; +static void turn_back_am(ir_node *node) +{ + ir_graph *irg = current_ir_graph; + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *block = get_nodes_block(node); + ir_node *base = get_irn_n(node, n_ia32_base); + ir_node *index = get_irn_n(node, n_ia32_index); + ir_node *mem = get_irn_n(node, n_ia32_mem); + ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg); + ir_node *load; + ir_node *load_res; + ir_node *mem_proj; + const ir_edge_t *edge; - if (is_Block(irn)) - return; + load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); + load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); - mode = get_irn_mode(irn); + ia32_copy_am_attrs(load, node); + set_irn_n(node, n_ia32_mem, new_NoMem()); - /* check if we already saw this node or the node has more than one user */ - if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) { - return; - }; + switch (get_ia32_am_arity(node)) { + case ia32_am_unary: + set_irn_n(node, n_ia32_unary_op, load_res); + break; - /* mark irn visited */ - bitset_add_irn(already_visited, irn); + case ia32_am_binary: + if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) { + assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) || + is_ia32_Test(node) || is_ia32_Test8Bit(node)); + set_irn_n(node, n_ia32_binary_left, load_res); + } else { + set_irn_n(node, n_ia32_binary_right, load_res); + } + break; - /* non-Tuple nodes with one user: ok, return */ - if (get_irn_n_edges(irn) >= 1 && mode != mode_T) { - return; + case ia32_am_ternary: + set_irn_n(node, n_ia32_binary_right, load_res); + break; + + default: break; } + set_irn_n(node, n_ia32_base, noreg); + set_irn_n(node, n_ia32_index, noreg); + set_ia32_am_offs_int(node, 0); + set_ia32_am_sc(node, NULL); + set_ia32_am_scale(node, 0); + clear_ia32_am_sc_sign(node); + + /* rewire mem-proj */ + if (get_irn_mode(node) == mode_T) { + mem_proj = NULL; + foreach_out_edge(node, edge) { + ir_node *out = get_edge_src_irn(edge); + if(get_Proj_proj(out) == pn_ia32_mem) { + mem_proj = out; + break; + } + } - /* tuple node has one user which is not the mem proj-> ok */ - if (mode == mode_T && get_irn_n_edges(irn) == 1) { - mem_proj = ia32_get_proj_for_mode(irn, mode_M); - if (mem_proj == NULL) { - return; + if(mem_proj != NULL) { + set_Proj_pred(mem_proj, load); + set_Proj_proj(mem_proj, pn_ia32_Load_M); } } - arity = get_irn_arity(irn); - for (i = 0; i < arity; ++i) { - ir_node *pred = get_irn_n(irn, i); - - /* do not follow memory edges or we will accidentally remove stores */ - if (get_irn_mode(pred) == mode_M) { - if(mem_proj != NULL) { - edges_reroute(mem_proj, pred, get_irn_irg(mem_proj)); - mem_proj = NULL; - } - continue; - } + set_ia32_op_type(node, ia32_Normal); + if (sched_is_scheduled(node)) + sched_add_before(node, load); +} - set_irn_n(irn, i, new_Bad()); +static ir_node *flags_remat(ir_node *node, ir_node *after) +{ + /* we should turn back source address mode when rematerializing nodes */ + ia32_op_type_t type = get_ia32_op_type(node); + ir_node *block; + ir_node *copy; - /* - The current node is about to be removed: if the predecessor - has only this node as user, it need to be removed as well. - */ - if (get_irn_n_edges(pred) <= 1) - remove_unused_nodes(pred, already_visited); + if (is_Block(after)) { + block = after; + } else { + block = get_nodes_block(after); } - // we need to set the presd to Bad again to also get the memory edges - arity = get_irn_arity(irn); - for (i = 0; i < arity; ++i) { - set_irn_n(irn, i, new_Bad()); - } + switch (type) { + case ia32_AddrModeS: turn_back_am(node); break; - if (sched_is_scheduled(irn)) { - sched_remove(irn); + case ia32_AddrModeD: + /* TODO implement this later... */ + panic("found DestAM with flag user %+F this should not happen", node); + break; + + default: assert(type == ia32_Normal); break; } -} -static void remove_unused_loads_walker(ir_node *irn, void *env) { - bitset_t *already_visited = env; - if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn)) - remove_unused_nodes(irn, env); + copy = exact_copy(node); + set_nodes_block(copy, block); + sched_add_after(after, copy); + + return copy; } /** @@ -979,19 +1117,16 @@ static void remove_unused_loads_walker(ir_node *irn, void *env) { * simulator and the emitter. */ static void ia32_before_ra(void *self) { - ia32_code_gen_t *cg = self; - bitset_t *already_visited = bitset_irg_alloca(cg->irg); - - /* - Handle special case: - There are sometimes unused loads, only pinned by memory. - We need to remove those Loads and all other nodes which won't be used - after removing the Load from schedule. - */ - irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited); + ia32_code_gen_t *cg = self; /* setup fpu rounding modes */ ia32_setup_fpu_mode(cg); + + /* fixup flags */ + be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags], + &flags_remat); + + ia32_add_missing_keeps(cg); } @@ -1017,10 +1152,10 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { } if (mode_is_float(spillmode)) { - if (USE_SSE2(cg)) - new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem); + if (ia32_cg_config.use_sse2) + new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode); else - new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem); + new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode); } else if (get_mode_size_bits(spillmode) == 128) { // Reload 128 bit sse registers @@ -1029,9 +1164,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { else new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem); - set_ia32_am_support(new_op, ia32_am_Source); set_ia32_op_type(new_op, ia32_AddrModeS); - set_ia32_am_flavour(new_op, ia32_B); set_ia32_ls_mode(new_op, spillmode); set_ia32_frame_ent(new_op, ent); set_ia32_use_frame(new_op); @@ -1042,8 +1175,6 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { if (sched_point) { sched_add_after(sched_point, new_op); - sched_add_after(new_op, proj); - sched_remove(node); } @@ -1090,22 +1221,20 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) { } if (mode_is_float(mode)) { - if (USE_SSE2(cg)) - store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem); + if (ia32_cg_config.use_sse2) + store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val); else - store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem); + store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode); } else if (get_mode_size_bits(mode) == 128) { // Spill 128 bit SSE registers - store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem); + store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val); } else if (get_mode_size_bits(mode) == 8) { - store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem); + store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val); } else { - store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem); + store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val); } - set_ia32_am_support(store, ia32_am_Dest); set_ia32_op_type(store, ia32_AddrModeD); - set_ia32_am_flavour(store, ia32_B); set_ia32_ls_mode(store, mode); set_ia32_frame_ent(store, ent); set_ia32_use_frame(store); @@ -1127,12 +1256,11 @@ static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpo ir_node *noreg = ia32_new_NoReg_gp(cg); ir_node *frame = get_irg_frame(irg); - ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem); + ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg); set_ia32_frame_ent(push, ent); set_ia32_use_frame(push); set_ia32_op_type(push, ia32_AddrModeS); - set_ia32_am_flavour(push, ia32_B); set_ia32_ls_mode(push, mode_Is); sched_add_before(schedpoint, push); @@ -1146,12 +1274,11 @@ static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoi ir_node *noreg = ia32_new_NoReg_gp(cg); ir_node *frame = get_irg_frame(irg); - ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem()); + ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp); set_ia32_frame_ent(pop, ent); set_ia32_use_frame(pop); set_ia32_op_type(pop, ia32_AddrModeD); - set_ia32_am_flavour(pop, ia32_am_OB); set_ia32_ls_mode(pop, mode_Is); sched_add_before(schedpoint, pop); @@ -1159,7 +1286,7 @@ static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoi return pop; } -static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) { +static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) { ir_graph *irg = get_irn_irg(node); dbg_info *dbg = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); @@ -1169,7 +1296,6 @@ static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos); arch_set_irn_register(cg->arch_env, sp, spreg); - sched_add_before(schedpoint, sp); return sp; } @@ -1193,65 +1319,65 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) { arity = be_get_MemPerm_entity_arity(node); pops = alloca(arity * sizeof(pops[0])); - // create pushs + /* create Pushs */ for(i = 0; i < arity; ++i) { ir_entity *inent = be_get_MemPerm_in_entity(node, i); ir_entity *outent = be_get_MemPerm_out_entity(node, i); ir_type *enttype = get_entity_type(inent); - int entbits = get_type_size_bits(enttype); - int entbits2 = get_type_size_bits(get_entity_type(outent)); + unsigned entsize = get_type_size_bytes(enttype); + unsigned entsize2 = get_type_size_bytes(get_entity_type(outent)); ir_node *mem = get_irn_n(node, i + 1); ir_node *push; /* work around cases where entities have different sizes */ - if(entbits2 < entbits) - entbits = entbits2; - assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit"); + if(entsize2 < entsize) + entsize = entsize2; + assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit"); push = create_push(cg, node, node, sp, mem, inent); - sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node); - if(entbits == 64) { - // add another push after the first one + sp = create_spproj(cg, node, push, pn_ia32_Push_stack); + if(entsize == 8) { + /* add another push after the first one */ push = create_push(cg, node, node, sp, mem, inent); add_ia32_am_offs_int(push, 4); - sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node); + sp = create_spproj(cg, node, push, pn_ia32_Push_stack); } set_irn_n(node, i, new_Bad()); } - // create pops + /* create pops */ for(i = arity - 1; i >= 0; --i) { ir_entity *inent = be_get_MemPerm_in_entity(node, i); ir_entity *outent = be_get_MemPerm_out_entity(node, i); ir_type *enttype = get_entity_type(outent); - int entbits = get_type_size_bits(enttype); - int entbits2 = get_type_size_bits(get_entity_type(inent)); + unsigned entsize = get_type_size_bytes(enttype); + unsigned entsize2 = get_type_size_bytes(get_entity_type(inent)); ir_node *pop; /* work around cases where entities have different sizes */ - if(entbits2 < entbits) - entbits = entbits2; - assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit"); + if(entsize2 < entsize) + entsize = entsize2; + assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit"); pop = create_pop(cg, node, node, sp, outent); - sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node); - if(entbits == 64) { + sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack); + if(entsize == 8) { add_ia32_am_offs_int(pop, 4); - // add another pop after the first one + /* add another pop after the first one */ pop = create_pop(cg, node, node, sp, outent); - sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node); + sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack); } pops[i] = pop; } in[0] = sp; - keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); + keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in); sched_add_before(node, keep); - // exchange memprojs + /* exchange memprojs */ foreach_out_edge_safe(node, edge, next) { ir_node *proj = get_edge_src_irn(edge); int p = get_Proj_proj(proj); @@ -1259,10 +1385,10 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) { assert(p < arity); set_Proj_pred(proj, pops[p]); - set_Proj_proj(proj, 3); + set_Proj_proj(proj, pn_ia32_Pop_M); } - // remove memperm + /* remove memperm */ arity = get_irn_arity(node); for(i = 0; i < arity; ++i) { set_irn_n(node, i, new_Bad()); @@ -1305,29 +1431,34 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL && is_ia32_use_frame(node)) { if (is_ia32_need_stackent(node) || is_ia32_Load(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - int align = get_mode_size_bytes(mode); + const ir_mode *mode = get_ia32_ls_mode(node); + const ia32_attr_t *attr = get_ia32_attr_const(node); + int align = get_mode_size_bytes(mode); + + if(attr->data.need_64bit_stackent) { + mode = mode_Ls; + } + if(attr->data.need_32bit_stackent) { + mode = mode_Is; + } be_node_needs_frame_entity(env, node, mode, align); - } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - int align = 4; + } else if (is_ia32_vfild(node) || is_ia32_xLoad(node) + || is_ia32_vfld(node)) { + const ir_mode *mode = get_ia32_ls_mode(node); + int align = 4; be_node_needs_frame_entity(env, node, mode, align); } else if(is_ia32_FldCW(node)) { - const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode; - int align = 4; - be_node_needs_frame_entity(env, node, mode, align); - } else if (is_ia32_SetST0(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - int align = 4; + /* although 2 byte would be enough 4 byte performs best */ + const ir_mode *mode = mode_Iu; + int align = 4; be_node_needs_frame_entity(env, node, mode, align); } else { #ifndef NDEBUG - if(!is_ia32_St(node) && !is_ia32_xStoreSimple(node) - && !is_ia32_vfist(node) - && !is_ia32_GetST0(node) - && !is_ia32_FnstCW(node)) { - assert(0); - } + assert(is_ia32_St(node) || + is_ia32_xStoreSimple(node) || + is_ia32_vfst(node) || + is_ia32_vfist(node) || + is_ia32_FnstCW(node)); #endif } } @@ -1348,8 +1479,6 @@ static void ia32_after_ra(void *self) { be_free_frame_entity_coalescer(fec_env); irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg); - - ia32_finish_irg(irg, cg); } /** @@ -1361,17 +1490,19 @@ static void ia32_finish(void *self) { ia32_code_gen_t *cg = self; ir_graph *irg = cg->irg; - /* if we do x87 code generation, rewrite all the virtual instructions and registers */ - if (cg->used_fp == fp_x87 || cg->force_sim) { + ia32_finish_irg(irg, cg); + + /* we might have to rewrite x87 virtual registers */ + if (cg->do_x87_sim) { x87_simulate_graph(cg->arch_env, cg->birg); } + /* do peephole optimisations */ + ia32_peephole_optimization(cg); + /* create block schedule, this also removes empty blocks which might * produce critical edges */ cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq); - - /* do peephole optimisations */ - ia32_peephole_optimization(irg, cg); } /** @@ -1389,16 +1520,39 @@ static void ia32_codegen(void *self) { /* remove it from the isa */ cg->isa->cg = NULL; + assert(ia32_current_cg == cg); + ia32_current_cg = NULL; + /* de-allocate code generator */ del_set(cg->reg_set); free(cg); } +/** + * Returns the node representing the PIC base. + */ +static ir_node *ia32_get_pic_base(void *self) { + ir_node *block; + ia32_code_gen_t *cg = self; + ir_node *get_eip = cg->get_eip; + if (get_eip != NULL) + return get_eip; + + block = get_irg_start_block(cg->irg); + get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block); + cg->get_eip = get_eip; + + add_irn_dep(get_eip, get_irg_frame(cg->irg)); + + return get_eip; +} + static void *ia32_cg_init(be_irg_t *birg); static const arch_code_generator_if_t ia32_code_gen_if = { ia32_cg_init, - NULL, /* before abi introduce hook */ + ia32_get_pic_base, /* return node used as base in pic code addresses */ + ia32_before_abi, /* before abi introduce hook */ ia32_prepare_graph, NULL, /* spill */ ia32_before_sched, /* before scheduling hook */ @@ -1412,24 +1566,23 @@ static const arch_code_generator_if_t ia32_code_gen_if = { * Initializes a IA32 code generator. */ static void *ia32_cg_init(be_irg_t *birg) { - ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa; + ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env.isa; ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg)); cg->impl = &ia32_code_gen_if; cg->irg = birg->irg; cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024); - cg->arch_env = birg->main_env->arch_env; + cg->arch_env = &birg->main_env->arch_env; cg->isa = isa; cg->birg = birg; cg->blk_sched = NULL; - cg->fp_kind = isa->fp_kind; - cg->used_fp = fp_none; cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; + cg->gprof = (birg->main_env->options->gprof) ? 1 : 0; - /* copy optimizations from isa for easier access */ - cg->opt = isa->opt; - cg->arch = isa->arch; - cg->opt_arch = isa->opt_arch; + if (cg->gprof) { + /* Linux gprof implementation needs base pointer */ + birg->main_env->options->omit_fp = 0; + } /* enter it */ isa->cg = cg; @@ -1445,6 +1598,9 @@ static void *ia32_cg_init(be_irg_t *birg) { ia32_irn_ops.cg = cg; + assert(ia32_current_cg == NULL); + ia32_current_cg = cg; + return (arch_code_generator_t *)cg; } @@ -1464,8 +1620,8 @@ static void *ia32_cg_init(be_irg_t *birg) { * Set output modes for GCC */ static const tarval_mode_info mo_integer = { - TVO_DECIMAL, - NULL, + TVO_HEX, + "0x", NULL, }; @@ -1497,30 +1653,20 @@ static ia32_isa_t ia32_isa_template = { &ia32_gp_regs[REG_ESP], /* stack pointer register */ &ia32_gp_regs[REG_EBP], /* base pointer register */ -1, /* stack direction */ + 16, /* stack alignment */ NULL, /* main environment */ 7, /* costs for a spill instruction */ 5, /* costs for a reload instruction */ }, - { NULL, }, /* emitter environment */ NULL, /* 16bit register names */ NULL, /* 8bit register names */ NULL, /* 8bit register names high */ NULL, /* types */ NULL, /* tv_ents */ - (0 | - IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */ - IA32_OPT_DOAM | /* optimize address mode default: on */ - IA32_OPT_LEA | /* optimize for LEAs default: on */ - IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */ - IA32_OPT_IMMOPS | /* operations can use immediates, default: on */ - IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */ - arch_pentium_4, /* instruction architecture */ - arch_pentium_4, /* optimize for architecture */ - fp_x87, /* floating point mode */ NULL, /* current code generator */ + NULL, /* abstract machine */ #ifndef NDEBUG NULL, /* name obstack */ - 0 /* name obst size */ #endif }; @@ -1544,21 +1690,10 @@ static void *ia32_init(FILE *file_handle) { mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0); } - ia32_register_init(isa); + ia32_register_init(); ia32_create_opcodes(); - ia32_register_copy_attr_func(); - - if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) || - (ARCH_AMD(isa->arch) && isa->arch < arch_athlon)) - /* no SSE2 for these cpu's */ - isa->fp_kind = fp_x87; - - if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) { - /* Pentium 4 don't like inc and dec instructions */ - isa->opt &= ~IA32_OPT_INCDEC; - } - be_emit_init_env(&isa->emit, file_handle); + be_emit_init(file_handle); isa->regs_16bit = pmap_create(); isa->regs_8bit = pmap_create(); isa->regs_8bit_high = pmap_create(); @@ -1575,12 +1710,14 @@ static void *ia32_init(FILE *file_handle) { obstack_init(isa->name_obst); #endif /* NDEBUG */ + /* enter the ISA object into the intrinsic environment */ + intrinsic_env.isa = isa; ia32_handle_intrinsics(); /* needed for the debug support */ - be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT); - be_emit_cstring(&isa->emit, ".Ltext0:\n"); - be_emit_write_line(&isa->emit); + be_gas_emit_switch_section(GAS_SECTION_TEXT); + be_emit_cstring(".Ltext0:\n"); + be_emit_write_line(); /* we mark referenced global entities, so we can only emit those which * are actually referenced. (Note: you mustn't use the type visited flag @@ -1600,7 +1737,7 @@ static void ia32_done(void *self) { ia32_isa_t *isa = self; /* emit now all global declarations */ - be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1); + be_gas_emit_decls(isa->arch_isa.main_env, 1); pmap_destroy(isa->regs_16bit); pmap_destroy(isa->regs_8bit); @@ -1612,7 +1749,7 @@ static void ia32_done(void *self) { obstack_free(isa->name_obst, NULL); #endif /* NDEBUG */ - be_emit_destroy_env(&isa->emit); + be_emit_exit(); free(self); } @@ -1626,16 +1763,19 @@ static void ia32_done(void *self) { * - the virtual floating point registers * - the SSE vector register set */ -static int ia32_get_n_reg_class(const void *self) { +static unsigned ia32_get_n_reg_class(const void *self) { + (void) self; return N_CLASSES; } /** * Return the register class for index i. */ -static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) +static const arch_register_class_t *ia32_get_reg_class(const void *self, + unsigned i) { - assert(i >= 0 && i < N_CLASSES); + (void) self; + assert(i < N_CLASSES); return &ia32_reg_classes[i]; } @@ -1645,10 +1785,13 @@ static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) * @param mode The mode in question. * @return A register class which can hold values of the given mode. */ -const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) { - const ia32_isa_t *isa = self; +const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, + const ir_mode *mode) +{ + (void) self; + if (mode_is_float(mode)) { - return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp]; + return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp]; } else return &ia32_reg_classes[CLASS_ia32_gp]; @@ -1660,62 +1803,66 @@ const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const * @param method_type The type of the method (procedure) in question. * @param abi The abi object to be modified */ -static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) { - const ia32_isa_t *isa = self; +static void ia32_get_call_abi(const void *self, ir_type *method_type, + be_abi_call_t *abi) +{ ir_type *tp; ir_mode *mode; - unsigned cc = get_method_calling_convention(method_type); - int n = get_method_n_params(method_type); - int biggest_n = -1; - int stack_idx = 0; - int i, ignore_1, ignore_2; - ir_mode **modes; - const arch_register_t *reg; + unsigned cc; + int n, i, regnum; be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi); - - unsigned use_push = !IS_P6_ARCH(isa->opt_arch); + (void) self; /* set abi flags for calls */ call_flags.bits.left_to_right = 0; /* always last arg first on stack */ - call_flags.bits.store_args_sequential = use_push; + call_flags.bits.store_args_sequential = 0; /* call_flags.bits.try_omit_fp not changed: can handle both settings */ call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */ call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */ - /* set stack parameter passing style */ + /* set parameter passing style */ be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks); - /* collect the mode for each type */ - modes = alloca(n * sizeof(modes[0])); + if (get_method_variadicity(method_type) == variadicity_variadic) { + /* pass all parameters of a variadic function on the stack */ + cc = cc_cdecl_set; + } else { + cc = get_method_calling_convention(method_type); + if (get_method_additional_properties(method_type) & mtp_property_private + && (ia32_cg_config.optimize_cc)) { + /* set the calling conventions to register parameter */ + cc = (cc & ~cc_bits) | cc_reg_param; + } + } - for (i = 0; i < n; i++) { - tp = get_method_param_type(method_type, i); - modes[i] = get_type_mode(tp); + /* we have to pop the shadow parameter ourself for compound calls */ + if( (get_method_calling_convention(method_type) & cc_compound_ret) + && !(cc & cc_reg_param)) { + be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data)); } - /* set register parameters */ - if (cc & cc_reg_param) { - /* determine the number of parameters passed via registers */ - biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2); + n = get_method_n_params(method_type); + for (i = regnum = 0; i < n; i++) { + ir_mode *mode; + const arch_register_t *reg = NULL; - /* loop over all parameters and set the register requirements */ - for (i = 0; i <= biggest_n; i++) { - reg = ia32_get_RegParam_reg(n, modes, i, cc); - assert(reg && "kaputt"); + tp = get_method_param_type(method_type, i); + mode = get_type_mode(tp); + if (mode != NULL) { + reg = ia32_get_RegParam_reg(cc, regnum, mode); + } + if (reg != NULL) { be_abi_call_param_reg(abi, i, reg); + ++regnum; + } else { + /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes. + * movl has a shorter opcode than mov[sz][bw]l */ + ir_mode *load_mode = mode; + if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu; + be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0); } - - stack_idx = i; - } - - - /* set stack parameters */ - for (i = stack_idx; i < n; i++) { - /* parameters on the stack are 32 bit aligned */ - be_abi_call_param_stack(abi, i, 4, 0, 0); } - /* set return registers */ n = get_method_n_ress(method_type); @@ -1750,7 +1897,11 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_cal } -static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) { +static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, + const ir_node *irn) +{ + (void) self; + (void) irn; return &ia32_irn_ops; } @@ -1758,14 +1909,17 @@ const arch_irn_handler_t ia32_irn_handler = { ia32_get_irn_ops }; -const arch_irn_handler_t *ia32_get_irn_handler(const void *self) { +const arch_irn_handler_t *ia32_get_irn_handler(const void *self) +{ + (void) self; return &ia32_irn_handler; } -int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) { +int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) +{ + (void) block_env; + if(!is_ia32_irn(irn)) { - if (is_ASM(irn)) - return 1; return -1; } @@ -1781,7 +1935,9 @@ int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) { /** * Initializes the code generator interface. */ -static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) { +static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) +{ + (void) self; return &ia32_code_gen_if; } @@ -1798,30 +1954,40 @@ list_sched_selector_t ia32_sched_selector; /** * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded */ -static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) { +static const list_sched_selector_t *ia32_get_list_sched_selector( + const void *self, list_sched_selector_t *selector) +{ + (void) self; memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector)); ia32_sched_selector.exectime = ia32_sched_exectime; ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule; return &ia32_sched_selector; } -static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) { +static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) +{ + (void) self; return NULL; } /** * Returns the necessary byte alignment for storing a register of given class. */ -static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) { +static int ia32_get_reg_class_alignment(const void *self, + const arch_register_class_t *cls) +{ ir_mode *mode = arch_register_class_mode(cls); int bytes = get_mode_size_bytes(mode); + (void) self; if (mode_is_float(mode) && bytes > 8) return 16; return bytes; } -static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) { +static const be_execution_unit_t ***ia32_get_allowed_execution_units( + const void *self, const ir_node *irn) +{ static const be_execution_unit_t *_allowed_units_BRANCH[] = { &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1], &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2], @@ -1854,6 +2020,7 @@ static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void NULL }; const be_execution_unit_t ***ret; + (void) self; if (is_ia32_irn(irn)) { ret = get_ia32_exec_units(irn); @@ -1887,7 +2054,10 @@ static const be_machine_t *ia32_get_machine(const void *self) { /** * Return irp irgs in the desired order. */ -static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) { +static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) +{ + (void) self; + (void) irg_list; return NULL; } @@ -1897,66 +2067,52 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) { */ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) { - ir_node *cmp, *cmp_a, *phi; - ir_mode *mode; + ir_node *phi; -/* we don't want long long an floating point Psi */ -#define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32) + (void)sel; + (void)i; + (void)j; - if (get_irn_mode(sel) != mode_b) + if(!ia32_cg_config.use_cmov) { + /* TODO: we could still handle abs(x)... */ return 0; + } - cmp = get_Proj_pred(sel); - cmp_a = get_Cmp_left(cmp); - mode = get_irn_mode(cmp_a); - - if (IS_BAD_PSI_MODE(mode)) - return 0; + /* we can't handle psis with 64bit compares yet */ + if(is_Proj(sel)) { + ir_node *pred = get_Proj_pred(sel); + if(is_Cmp(pred)) { + ir_node *left = get_Cmp_left(pred); + ir_mode *cmp_mode = get_irn_mode(left); + if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) + return 0; + } + } /* check the Phi nodes */ for (phi = phi_list; phi; phi = get_irn_link(phi)) { - ir_node *pred_i = get_irn_n(phi, i); - ir_node *pred_j = get_irn_n(phi, j); - ir_mode *mode_i = get_irn_mode(pred_i); - ir_mode *mode_j = get_irn_mode(pred_j); + ir_mode *mode = get_irn_mode(phi); - if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j)) + if (mode_is_float(mode) || get_mode_size_bits(mode) > 32) return 0; } -#undef IS_BAD_PSI_MODE - return 1; } -/** - * Called by the frontend to encode a register name into a backend specific way - */ -static unsigned ia32_register_from_name(const char *regname) { - /* NYI */ - return 0; -} - -static ia32_intrinsic_env_t intrinsic_env = { - NULL, /**< the irg, these entities belong to */ - NULL, /**< entity for first div operand (move into FPU) */ - NULL, /**< entity for second div operand (move into FPU) */ - NULL, /**< entity for converts ll -> d */ - NULL, /**< entity for converts d -> ll */ -}; - /** * Returns the libFirm configuration parameter for this backend. */ static const backend_params *ia32_get_libfirm_params(void) { - static const opt_if_conv_info_t ifconv = { + static const ir_settings_if_conv_t ifconv = { 4, /* maxdepth, doesn't matter for Psi-conversion */ ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */ }; - static const arch_dep_params_t ad = { - 1, /* also use subs */ - 4, /* maximum shifts */ - 31, /* maximum shift amount */ + static const ir_settings_arch_dep_t ad = { + 1, /* also use subs */ + 4, /* maximum shifts */ + 31, /* maximum shift amount */ + ia32_evaluate_insn, /* evaluate the instruction sequence */ 1, /* allow Mulhs */ 1, /* allow Mulus */ @@ -1969,61 +2125,21 @@ static const backend_params *ia32_get_libfirm_params(void) { NULL, /* will be set later */ ia32_create_intrinsic_fkt, &intrinsic_env, /* context for ia32_create_intrinsic_fkt */ - NULL, /* will be set later */ - ia32_register_from_name, /* register names */ + NULL, /* will be set below */ }; + ia32_setup_cg_config(); + p.dep_param = &ad; p.if_conv_info = &ifconv; return &p; } -/* instruction set architectures. */ -static const lc_opt_enum_int_items_t arch_items[] = { - { "386", arch_i386, }, - { "486", arch_i486, }, - { "pentium", arch_pentium, }, - { "586", arch_pentium, }, - { "pentiumpro", arch_pentium_pro, }, - { "686", arch_pentium_pro, }, - { "pentiummmx", arch_pentium_mmx, }, - { "pentium2", arch_pentium_2, }, - { "p2", arch_pentium_2, }, - { "pentium3", arch_pentium_3, }, - { "p3", arch_pentium_3, }, - { "pentium4", arch_pentium_4, }, - { "p4", arch_pentium_4, }, - { "pentiumm", arch_pentium_m, }, - { "pm", arch_pentium_m, }, - { "core", arch_core, }, - { "k6", arch_k6, }, - { "athlon", arch_athlon, }, - { "athlon64", arch_athlon_64, }, - { "opteron", arch_opteron, }, - { NULL, 0 } -}; - -static lc_opt_enum_int_var_t arch_var = { - &ia32_isa_template.arch, arch_items -}; - -static lc_opt_enum_int_var_t opt_arch_var = { - &ia32_isa_template.opt_arch, arch_items -}; - -static const lc_opt_enum_int_items_t fp_unit_items[] = { - { "x87" , fp_x87 }, - { "sse2", fp_sse2 }, - { NULL, 0 } -}; - -static lc_opt_enum_int_var_t fp_unit_var = { - &ia32_isa_template.fp_kind, fp_unit_items -}; - static const lc_opt_enum_int_items_t gas_items[] = { - { "normal", GAS_FLAVOUR_NORMAL }, + { "elf", GAS_FLAVOUR_ELF }, { "mingw", GAS_FLAVOUR_MINGW }, + { "yasm", GAS_FLAVOUR_YASM }, + { "macho", GAS_FLAVOUR_MACH_O }, { NULL, 0 } }; @@ -2032,16 +2148,10 @@ static lc_opt_enum_int_var_t gas_var = { }; static const lc_opt_table_entry_t ia32_options[] = { - LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var), - LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var), - LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var), - LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM), - LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA), - LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST), - LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS), - LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS), - LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var), - { NULL } + LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var), + LC_OPT_ENT_INT("stackalign", "set stack alignment for calls", + &ia32_isa_template.arch_isa.stack_alignment), + LC_OPT_LAST }; const arch_isa_if_t ia32_isa_if = { @@ -2070,7 +2180,7 @@ void ia32_init_x87(void); void be_init_arch_ia32(void) { - lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be"); + lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be"); lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32"); lc_opt_add_table(ia32_grp, ia32_options); @@ -2083,6 +2193,7 @@ void be_init_arch_ia32(void) ia32_init_optimize(); ia32_init_transform(); ia32_init_x87(); + ia32_init_architecture(); } BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);