X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=9e65fdb624a286146307602f8c800810da9da26e;hb=11b7b651234355a0298e1075d57703c554e0ef4d;hp=ac2811ccfdaf6a5202398c38945fa7c599b927be;hpb=0fbcef83aa6060534172bb13e71cdadb04428806;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index ac2811ccf..9e65fdb62 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -89,6 +89,8 @@ #ifdef FIRM_GRGEN_BE #include "ia32_pbqp_transform.h" + +transformer_t be_transformer = TRANSFORMER_DEFAULT; #endif DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;) @@ -119,7 +121,7 @@ static ia32_intrinsic_env_t intrinsic_env = { typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block); -static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, +static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, create_const_node_func func, const arch_register_t* reg) { @@ -297,7 +299,7 @@ static const arch_register_t *ia32_get_irn_reg(const ir_node *irn) } static arch_irn_class_t ia32_classify(const ir_node *irn) { - arch_irn_class_t classification = arch_irn_class_normal; + arch_irn_class_t classification = 0; irn = skip_Proj_const(irn); @@ -305,13 +307,7 @@ static arch_irn_class_t ia32_classify(const ir_node *irn) { classification |= arch_irn_class_branch; if (! is_ia32_irn(irn)) - return classification & ~arch_irn_class_normal; - - if (is_ia32_Ld(irn)) - classification |= arch_irn_class_load; - - if (is_ia32_St(irn)) - classification |= arch_irn_class_store; + return classification; if (is_ia32_is_reload(irn)) classification |= arch_irn_class_reload; @@ -397,19 +393,6 @@ static int ia32_get_sp_bias(const ir_node *node) return 0; } -/** - * Put all registers which are saved by the prologue/epilogue in a set. - * - * @param self The callback object. - * @param s The result set. - */ -static void ia32_abi_dont_save_regs(void *self, pset *s) -{ - ia32_abi_env_t *env = self; - if(env->flags.try_omit_fp) - pset_insert_ptr(s, env->aenv->bp); -} - /** * Generate the routine prologue. * @@ -902,7 +885,6 @@ static const be_abi_callbacks_t ia32_abi_callbacks = { ia32_abi_init, ia32_abi_done, ia32_abi_get_between_type, - ia32_abi_dont_save_regs, ia32_abi_prologue, ia32_abi_epilogue }; @@ -963,8 +945,6 @@ static void ia32_before_abi(void *self) { } } -transformer_t be_transformer = TRANSFORMER_DEFAULT; - /** * Transforms the standard firm graph into * an ia32 firm graph @@ -987,20 +967,21 @@ static void ia32_prepare_graph(void *self) { be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched); switch (be_transformer) { - case TRANSFORMER_DEFAULT: - /* transform remaining nodes into assembler instructions */ - ia32_transform_graph(cg); - break; + case TRANSFORMER_DEFAULT: + /* transform remaining nodes into assembler instructions */ + ia32_transform_graph(cg); + break; #ifdef FIRM_GRGEN_BE - case TRANSFORMER_PBQP: - case TRANSFORMER_RAND: - /* transform nodes into assembler instructions by PBQP magic */ - ia32_transform_graph_by_pbqp(cg); - break; + case TRANSFORMER_PBQP: + case TRANSFORMER_RAND: + /* transform nodes into assembler instructions by PBQP magic */ + ia32_transform_graph_by_pbqp(cg); + break; #endif - default: panic("invalid transformer"); + default: + panic("invalid transformer"); } /* do local optimizations (mainly CSE) */ @@ -1012,9 +993,6 @@ static void ia32_prepare_graph(void *self) { /* optimize address mode */ ia32_optimize_graph(cg); - if (cg->dump) - be_dump(cg->irg, "-am", dump_ir_block_graph_sched); - /* do code placement, to optimize the position of constants */ place_code(cg->irg); @@ -1022,13 +1000,6 @@ static void ia32_prepare_graph(void *self) { be_dump(cg->irg, "-place", dump_ir_block_graph_sched); } -/** - * Dummy functions for hooks we don't need but which must be filled. - */ -static void ia32_before_sched(void *self) { - (void) self; -} - ir_node *turn_back_am(ir_node *node) { ir_graph *irg = current_ir_graph; @@ -1322,19 +1293,18 @@ static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos) * push/pop into/from memory cascades. This is possible without using * any registers. */ -static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) { - ir_graph *irg = get_irn_irg(node); - ir_node *block = get_nodes_block(node); - ir_node *in[1]; - ir_node *keep; - int i, arity; - ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]); +static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) +{ + ir_graph *irg = get_irn_irg(node); + ir_node *block = get_nodes_block(node); + ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]); + int arity = be_get_MemPerm_entity_arity(node); + ir_node **pops = ALLOCAN(ir_node*, arity); + ir_node *in[1]; + ir_node *keep; + int i; const ir_edge_t *edge; const ir_edge_t *next; - ir_node **pops; - - arity = be_get_MemPerm_entity_arity(node); - pops = alloca(arity * sizeof(pops[0])); /* create Pushs */ for(i = 0; i < arity; ++i) { @@ -1439,52 +1409,73 @@ static void ia32_after_ra_walker(ir_node *block, void *env) { */ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) { - be_fec_env_t *env = data; + be_fec_env_t *env = data; + const ir_mode *mode; + int align; if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) { - const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node)); - int align = get_mode_size_bytes(mode); - be_node_needs_frame_entity(env, node, mode, align); - } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL - && is_ia32_use_frame(node)) { - if (is_ia32_need_stackent(node) || is_ia32_Load(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - const ia32_attr_t *attr = get_ia32_attr_const(node); - int align; - - if (is_ia32_is_reload(node)) { - mode = get_spill_mode_mode(mode); + mode = get_spill_mode_mode(get_irn_mode(node)); + align = get_mode_size_bytes(mode); + } else if (is_ia32_irn(node) && + get_ia32_frame_ent(node) == NULL && + is_ia32_use_frame(node)) { + if (is_ia32_need_stackent(node)) + goto need_stackent; + + switch (get_ia32_irn_opcode(node)) { +need_stackent: + case iro_ia32_Load: { + const ia32_attr_t *attr = get_ia32_attr_const(node); + + if (attr->data.need_32bit_stackent) { + mode = mode_Is; + } else if (attr->data.need_64bit_stackent) { + mode = mode_Ls; + } else { + mode = get_ia32_ls_mode(node); + if (is_ia32_is_reload(node)) + mode = get_spill_mode_mode(mode); + } + align = get_mode_size_bytes(mode); + break; } - if(attr->data.need_64bit_stackent) { - mode = mode_Ls; + case iro_ia32_vfild: + case iro_ia32_vfld: + case iro_ia32_xLoad: { + mode = get_ia32_ls_mode(node); + align = 4; + break; } - if(attr->data.need_32bit_stackent) { - mode = mode_Is; + + case iro_ia32_FldCW: { + /* although 2 byte would be enough 4 byte performs best */ + mode = mode_Iu; + align = 4; + break; } - align = get_mode_size_bytes(mode); - be_node_needs_frame_entity(env, node, mode, align); - } else if (is_ia32_vfild(node) || is_ia32_xLoad(node) - || is_ia32_vfld(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - int align = 4; - be_node_needs_frame_entity(env, node, mode, align); - } else if(is_ia32_FldCW(node)) { - /* although 2 byte would be enough 4 byte performs best */ - const ir_mode *mode = mode_Iu; - int align = 4; - be_node_needs_frame_entity(env, node, mode, align); - } else { + + default: #ifndef NDEBUG - assert(is_ia32_St(node) || - is_ia32_xStoreSimple(node) || - is_ia32_vfst(node) || - is_ia32_vfist(node) || - is_ia32_vfisttp(node) || - is_ia32_FnstCW(node)); + panic("unexpected frame user while collection frame entity nodes"); + + case iro_ia32_FnstCW: + case iro_ia32_Store8Bit: + case iro_ia32_Store: + case iro_ia32_fst: + case iro_ia32_fstp: + case iro_ia32_vfist: + case iro_ia32_vfisttp: + case iro_ia32_vfst: + case iro_ia32_xStore: + case iro_ia32_xStoreSimple: #endif + return; } + } else { + return; } + be_node_needs_frame_entity(env, node, mode, align); } /** @@ -1577,7 +1568,6 @@ static const arch_code_generator_if_t ia32_code_gen_if = { ia32_before_abi, /* before abi introduce hook */ ia32_prepare_graph, NULL, /* spill */ - ia32_before_sched, /* before scheduling hook */ ia32_before_ra, /* before register allocation hook */ ia32_after_ra, /* after register allocation hook */ ia32_finish, /* called before codegen */ @@ -1595,7 +1585,6 @@ static void *ia32_cg_init(be_irg_t *birg) { cg->irg = birg->irg; cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024); cg->isa = isa; - cg->arch_env = birg->main_env->arch_env; cg->birg = birg; cg->blk_sched = NULL; cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; @@ -2340,22 +2329,24 @@ static lc_opt_enum_int_var_t gas_var = { (int*) &be_gas_flavour, gas_items }; +#ifdef FIRM_GRGEN_BE static const lc_opt_enum_int_items_t transformer_items[] = { { "default", TRANSFORMER_DEFAULT }, -#ifdef FIRM_GRGEN_BE { "pbqp", TRANSFORMER_PBQP }, { "random", TRANSFORMER_RAND }, -#endif { NULL, 0 } }; static lc_opt_enum_int_var_t transformer_var = { (int*)&be_transformer, transformer_items }; +#endif static const lc_opt_table_entry_t ia32_options[] = { LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var), +#ifdef FIRM_GRGEN_BE LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var), +#endif LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls", &ia32_isa_template.arch_env.stack_alignment), LC_OPT_LAST