X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=9dcbae3e8f0386bc6df184e5477744a7d838940a;hb=ca1b1615fbe23a4d5cf72e7be5d2ee831615cbc2;hp=793fadfb3bcd70fedf9328f7eab2bfc9b439edcb;hpb=7378f4a755ffdffdde608a822644869643f2c523;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 793fadfb3..9dcbae3e8 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -40,6 +40,7 @@ #include "ia32_emitter.h" #include "ia32_map_regs.h" #include "ia32_optimize.h" +#include "ia32_x87.h" #define DEBUG_MODULE "firm.be.ia32.isa" @@ -50,11 +51,12 @@ static set *cur_reg_set = NULL; #define is_Start(irn) (get_irn_opcode(irn) == iro_Start) ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) { - return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]); + return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]); } ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) { - return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]); + return be_abi_get_callee_save_irn(cg->birg->abi, + USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]); } /************************************************** @@ -74,24 +76,30 @@ static ir_node *my_skip_proj(const ir_node *n) { return (ir_node *)n; } + /** * Return register requirements for an ia32 node. * If the node returns a tuple (mode_T) then the proj's * will be asked for this information. */ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) { + const ia32_irn_ops_t *ops = self; const ia32_register_req_t *irn_req; long node_pos = pos == -1 ? 0 : pos; - ir_mode *mode = get_irn_mode(irn); - firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE); + ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn); + FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE); - if (mode == mode_T || mode == mode_M) { - DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn)); + if (is_Block(irn) || mode == mode_M || mode == mode_X) { + DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn)); return NULL; } - DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn)); + if (mode == mode_T && pos < 0) { + DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn)); + return NULL; + } + DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn)); if (is_Proj(irn)) { if (pos == -1) { @@ -132,8 +140,12 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_re /* treat Phi like Const with default requirements */ if (is_Phi(irn)) { DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn)); - if (mode_is_float(mode)) - memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req)); + if (mode_is_float(mode)) { + if (USE_SSE2(ops->cg)) + memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req)); + else + memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req)); + } else if (mode_is_int(mode) || mode_is_reference(mode)) memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req)); else if (mode == mode_T || mode == mode_M) { @@ -156,6 +168,10 @@ static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register int pos = 0; const ia32_irn_ops_t *ops = self; + if (get_irn_mode(irn) == mode_X) { + return; + } + DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn)); if (is_Proj(irn)) { @@ -179,6 +195,11 @@ static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node * const arch_register_t *reg = NULL; if (is_Proj(irn)) { + + if (get_irn_mode(irn) == mode_X) { + return NULL; + } + pos = ia32_translate_proj_pos(irn); irn = my_skip_proj(irn); } @@ -222,14 +243,20 @@ static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) { char buf[64]; const ia32_irn_ops_t *ops = self; - if (is_ia32_use_frame(irn) && bias != 0) { + if (get_ia32_frame_ent(irn)) { ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn); DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias)); snprintf(buf, sizeof(buf), "%d", bias); - add_ia32_am_offs(irn, buf); - am_flav |= ia32_O; - set_ia32_am_flavour(irn, am_flav); + + if (get_ia32_op_type(irn) == ia32_Normal) { + set_ia32_cnst(irn, buf); + } + else { + add_ia32_am_offs(irn, buf); + am_flav |= ia32_O; + set_ia32_am_flavour(irn, am_flav); + } } } @@ -239,13 +266,13 @@ typedef struct { ir_graph *irg; } ia32_abi_env_t; -static void *ia32_abi_init(const be_abi_call_t *call, const arch_isa_t *isa, ir_graph *irg) +static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg) { ia32_abi_env_t *env = xmalloc(sizeof(env[0])); be_abi_call_flags_t fl = be_abi_call_get_flags(call); env->flags = fl.bits; env->irg = irg; - env->isa = isa; + env->isa = aenv->isa; return env; } @@ -266,10 +293,10 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap ir_node *bl = get_irg_start_block(env->irg); ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp); ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp); - ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]); + ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]); ir_node *store_bp; - curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_along); + curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand); store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T); set_ia32_am_support(store_bp, ia32_am_Dest); set_ia32_am_flavour(store_bp, ia32_B); @@ -291,10 +318,10 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ ia32_abi_env_t *env = self; ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp); ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp); - ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]); + ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]); if(env->flags.try_omit_fp) { - curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against); + curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink); } else { @@ -398,19 +425,19 @@ ia32_irn_ops_t ia32_irn_ops = { */ static void ia32_prepare_graph(void *self) { ia32_code_gen_t *cg = self; - firm_dbg_module_t *old_mod = cg->mod; + DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;) - cg->mod = firm_dbg_register("firm.be.ia32.transform"); + FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform"); irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg); be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched); - edges_deactivate(cg->irg); - dead_node_elimination(cg->irg); - edges_activate(cg->irg); - - cg->mod = old_mod; + DEBUG_ONLY(cg->mod = old_mod;) if (cg->opt.doam) { + edges_deactivate(cg->irg); + //dead_node_elimination(cg->irg); + edges_activate(cg->irg); + irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg); be_dump(cg->irg, "-am", dump_ir_block_graph_sched); } @@ -425,50 +452,81 @@ static void ia32_prepare_graph(void *self) { static void ia32_finish_irg_walker(ir_node *irn, void *env) { ia32_code_gen_t *cg = env; const ia32_register_req_t **reqs; - const arch_register_t *out_reg, *in_reg; + const arch_register_t *out_reg, *in_reg, *in2_reg; int n_res, i; - ir_node *copy, *in_node, *block; + ir_node *copy, *in_node, *block, *in2_node; + ia32_op_type_t op_tp; - if (! is_ia32_irn(irn)) - return; - - /* nodes with destination address mode don't produce values */ - if (get_ia32_op_type(irn) == ia32_AddrModeD) - return; - - reqs = get_ia32_out_req_all(irn); - n_res = get_ia32_n_res(irn); - block = get_nodes_block(irn); - - /* check all OUT requirements, if there is a should_be_same */ - for (i = 0; i < n_res; i++) { - if (arch_register_req_is(&(reqs[i]->req), should_be_same)) { - /* get in and out register */ - out_reg = get_ia32_out_reg(irn, i); - in_node = get_irn_n(irn, reqs[i]->same_pos); - in_reg = arch_get_irn_register(cg->arch_env, in_node); - - /* check if in and out register are equal */ - if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) { - DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos)); - - /* create copy from in register */ - copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node); + if (is_ia32_irn(irn)) { + /* AM Dest nodes don't produce any values */ + op_tp = get_ia32_op_type(irn); + if (op_tp == ia32_AddrModeD) + return; + + reqs = get_ia32_out_req_all(irn); + n_res = get_ia32_n_res(irn); + block = get_nodes_block(irn); + + /* check all OUT requirements, if there is a should_be_same */ + if (op_tp == ia32_Normal) { + for (i = 0; i < n_res; i++) { + if (arch_register_req_is(&(reqs[i]->req), should_be_same)) { + /* get in and out register */ + out_reg = get_ia32_out_reg(irn, i); + in_node = get_irn_n(irn, reqs[i]->same_pos); + in_reg = arch_get_irn_register(cg->arch_env, in_node); + in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1); + in2_reg = arch_get_irn_register(cg->arch_env, in2_node); + + /* don't copy ignore nodes */ + if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node)) + continue; + + /* check if in and out register are equal */ + if (! REGS_ARE_EQUAL(out_reg, in_reg)) { + /* in case of a commutative op: just exchange the in's */ + if (is_ia32_commutative(irn) && REGS_ARE_EQUAL(out_reg, in2_reg)) { + set_irn_n(irn, reqs[i]->same_pos, in2_node); + set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node); + } + else { + DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos)); + /* create copy from in register */ + copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node); + + /* destination is the out register */ + arch_set_irn_register(cg->arch_env, copy, out_reg); + + /* insert copy before the node into the schedule */ + sched_add_before(irn, copy); + + /* set copy as in */ + set_irn_n(irn, reqs[i]->same_pos, copy); + } + } + } + } + } - /* destination is the out register */ - arch_set_irn_register(cg->arch_env, copy, out_reg); + /* If we have a CondJmp with immediate, we need to */ + /* check if it's the right operand, otherwise we have */ + /* to change it, as CMP doesn't support immediate as */ + /* left operands. */ + if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) { + long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn)); + set_ia32_op_type(irn, ia32_AddrModeD); + set_ia32_pncode(irn, pnc); + } - /* insert copy before the node into the schedule */ - sched_add_before(irn, copy); + /* check if there is a sub which need to be transformed */ + ia32_transform_sub_to_neg_add(irn, cg); - /* set copy as in */ - set_irn_n(irn, reqs[i]->same_pos, copy); - } - } + /* transform a LEA into an Add if possible */ + ia32_transform_lea_to_add(irn, cg); } - /* check if there is a sub which need to be transformed */ - ia32_transform_sub_to_neg_add(irn, cg); + /* check for peephole optimization */ + ia32_peephole_optimization(irn, cg); } /** @@ -486,9 +544,16 @@ static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) { static void ia32_before_sched(void *self) { } +/** + * Called before the register allocator. + * Calculate a block schedule here. We need it for the x87 + * simulator and the emitter. + */ static void ia32_before_ra(void *self) { -} + ia32_code_gen_t *cg = self; + cg->blk_sched = sched_create_block_schedule(cg->irg); +} /** @@ -511,7 +576,10 @@ static void transform_to_Load(ia32_transform_env_t *env) { } if (mode_is_float(mode)) { - new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + if (USE_SSE2(env->cg)) + new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); + else + new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); } else { new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T); @@ -537,8 +605,9 @@ static void transform_to_Load(ia32_transform_env_t *env) { reg = arch_get_irn_register(env->cg->arch_env, irn); arch_set_irn_register(env->cg->arch_env, new_op, reg); - exchange(irn, proj); + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op)); + exchange(irn, proj); } /** @@ -560,7 +629,13 @@ static void transform_to_Store(ia32_transform_env_t *env) { } if (mode_is_float(mode)) { - new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T); + if (USE_SSE2(env->cg)) + new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T); + else + new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T); + } + else if (get_mode_size_bits(mode) == 8) { + new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T); } else { new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T); @@ -569,11 +644,11 @@ static void transform_to_Store(ia32_transform_env_t *env) { set_ia32_am_support(new_op, ia32_am_Dest); set_ia32_op_type(new_op, ia32_AddrModeD); set_ia32_am_flavour(new_op, ia32_B); - set_ia32_ls_mode(new_op, get_irn_mode(val)); + set_ia32_ls_mode(new_op, mode); set_ia32_frame_ent(new_op, ent); set_ia32_use_frame(new_op); - proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0); + proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0); if (sched_point) { sched_add_after(sched_point, new_op); @@ -582,44 +657,75 @@ static void transform_to_Store(ia32_transform_env_t *env) { sched_remove(irn); } + SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op)); + exchange(irn, proj); +} +/** + * Fix the mode of Spill/Reload + */ +static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode) +{ + if (mode_is_float(mode)) { + if (USE_SSE2(cg)) + mode = mode_D; + else + mode = mode_E; + } + else + mode = mode_Is; + return mode; } /** - * Calls the transform functions for StackParam, Spill and Reload. + * Block-Walker: Calls the transform functions Spill and Reload. */ -static void ia32_after_ra_walker(ir_node *node, void *env) { +static void ia32_after_ra_walker(ir_node *block, void *env) { + ir_node *node, *prev; ia32_code_gen_t *cg = env; ia32_transform_env_t tenv; - if (is_Block(node)) - return; - - tenv.block = get_nodes_block(node); - tenv.dbg = get_irn_dbg_info(node); + tenv.block = block; tenv.irg = current_ir_graph; - tenv.irn = node; - tenv.mod = cg->mod; - tenv.mode = get_irn_mode(node); tenv.cg = cg; - - /* be_is_StackParam(node) || */ - if (be_is_Reload(node)) { - transform_to_Load(&tenv); - } - else if (be_is_Spill(node)) { - transform_to_Store(&tenv); + DEBUG_ONLY(tenv.mod = cg->mod;) + + /* beware: the schedule is changed here */ + for (node = sched_last(block); !sched_is_begin(node); node = prev) { + prev = sched_prev(node); + if (be_is_Reload(node)) { + /* we always reload the whole register */ + tenv.dbg = get_irn_dbg_info(node); + tenv.irn = node; + tenv.mode = fix_spill_mode(cg, get_irn_mode(node)); + transform_to_Load(&tenv); + } + else if (be_is_Spill(node)) { + /* we always spill the whole register */ + tenv.dbg = get_irn_dbg_info(node); + tenv.irn = node; + tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node))); + transform_to_Store(&tenv); + } } } /** - * We transform StackParam, Spill and Reload here. This needs to be done before + * We transform Spill and Reload here. This needs to be done before * stack biasing otherwise we would miss the corrected offset for these nodes. + * + * If x87 instruction should be emitted, run the x87 simulator and patch + * the virtual instructions. This must obviously be done after register allocation. */ static void ia32_after_ra(void *self) { ia32_code_gen_t *cg = self; - irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self); + irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self); + + /* if we do x87 code generation, rewrite all the virtual instructions and registers */ + if (cg->used_x87) { + x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched); + } } @@ -670,21 +776,26 @@ static void *ia32_cg_init(FILE *F, const be_irg_t *birg) { ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa; ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg)); - cg->impl = &ia32_code_gen_if; - cg->irg = birg->irg; - cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024); - cg->mod = firm_dbg_register("firm.be.ia32.cg"); - cg->out = F; - cg->arch_env = birg->main_env->arch_env; - cg->types = pmap_create(); - cg->tv_ent = pmap_create(); - cg->birg = birg; + cg->impl = &ia32_code_gen_if; + cg->irg = birg->irg; + cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024); + cg->out = F; + cg->arch_env = birg->main_env->arch_env; + cg->types = pmap_create(); + cg->tv_ent = pmap_create(); + cg->birg = birg; + cg->blk_sched = NULL; + cg->fp_kind = isa->fp_kind; + cg->used_x87 = 0; + + FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg"); /* set optimizations */ cg->opt.incdec = 0; cg->opt.doam = 1; cg->opt.placecnst = 1; cg->opt.immops = 1; + cg->opt.extbb = 1; #ifndef NDEBUG if (isa->name_obst_size) { @@ -729,6 +840,7 @@ static ia32_isa_t ia32_isa_template = { 0, /* number of code generator objects so far */ NULL, /* 16bit register names */ NULL, /* 8bit register names */ + fp_sse2, /* use SSE2 unit for fp operations */ #ifndef NDEBUG NULL, /* name obstack */ 0 /* name obst size */ @@ -750,9 +862,11 @@ static void *ia32_init(void) { ia32_register_init(isa); ia32_create_opcodes(); + ia32_register_copy_attr_func(); isa->regs_16bit = pmap_create(); isa->regs_8bit = pmap_create(); +// isa->fp_kind = fp_x87; ia32_build_16bit_reg_map(isa->regs_16bit); ia32_build_8bit_reg_map(isa->regs_8bit); @@ -788,14 +902,26 @@ static void ia32_done(void *self) { } - +/** + * Return the number of register classes for this architecture. + * We report always these: + * - the general purpose registers + * - the floating point register set (depending on the unit used for FP) + * - MMX/SE registers (currently not supported) + */ static int ia32_get_n_reg_class(const void *self) { - return N_CLASSES; + return 2; } +/** + * Return the register class for index i. + */ static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) { - assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested."); - return &ia32_reg_classes[i]; + const ia32_isa_t *isa = self; + assert(i >= 0 && i < 2 && "Invalid ia32 register class requested."); + if (i == 0) + return &ia32_reg_classes[CLASS_ia32_gp]; + return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp]; } /** @@ -805,8 +931,10 @@ static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) * @return A register class which can hold values of the given mode. */ const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) { - if (mode_is_float(mode)) - return &ia32_reg_classes[CLASS_ia32_fp]; + const ia32_isa_t *isa = self; + if (mode_is_float(mode)) { + return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp]; + } else return &ia32_reg_classes[CLASS_ia32_gp]; } @@ -817,7 +945,8 @@ const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const * @param method_type The type of the method (procedure) in question. * @param abi The abi object to be modified */ -void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) { +static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) { + const ia32_isa_t *isa = self; ir_type *tp; ir_mode *mode; unsigned cc = get_method_calling_convention(method_type); @@ -848,8 +977,7 @@ void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *ab } /* set register parameters */ -// if (cc & cc_reg_param) { - if (1) { + if (cc & cc_reg_param) { /* determine the number of parameters passed via registers */ biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2); @@ -866,7 +994,7 @@ void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *ab /* set stack parameters */ for (i = stack_idx; i < n; i++) { - be_abi_call_param_stack(abi, i); + be_abi_call_param_stack(abi, i, 1, 0, 0); } @@ -891,11 +1019,17 @@ void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *ab be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]); } else if (n == 1) { + const arch_register_t *reg; + tp = get_method_res_type(method_type, 0); assert(is_atomic_type(tp)); mode = get_type_mode(tp); - be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]); + reg = mode_is_float(mode) ? + (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) : + &ia32_gp_regs[REG_EAX]; + + be_abi_call_res_reg(abi, 0, reg); } } @@ -929,11 +1063,24 @@ list_sched_selector_t ia32_sched_selector; * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded */ static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) { +// memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t)); memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t)); ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule; return &ia32_sched_selector; } +/** + * Returns the necessary byte alignment for storing a register of given class. + */ +static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) { + ir_mode *mode = arch_register_class_mode(cls); + int bytes = get_mode_size_bytes(mode); + + if (mode_is_float(mode) && bytes > 8) + return 16; + return bytes; +} + #ifdef WITH_LIBCORE static void ia32_register_options(lc_opt_entry_t *ent) { @@ -952,5 +1099,6 @@ const arch_isa_if_t ia32_isa_if = { ia32_get_call_abi, ia32_get_irn_handler, ia32_get_code_generator_if, - ia32_get_list_sched_selector + ia32_get_list_sched_selector, + ia32_get_reg_class_alignment };