X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=96dce91549dbf827968c7369ebdb92df3ea8417a;hb=435d56a4e04e517c9dfb3e25bcad1ac44f9de2d2;hp=01fa57a49a47714b921fbd9a8e4ee66ac5cb2f43;hpb=4808973ff03cc6c669ee627c9509f2646047d57f;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 01fa57a49..96dce9154 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -101,26 +101,32 @@ static set *cur_reg_set = NULL; ir_mode *mode_fpcw = NULL; ia32_code_gen_t *ia32_current_cg = NULL; +/** The current omit-fp state */ +static unsigned ia32_curr_fp_ommitted = 0; +static ir_type *omit_fp_between_type = NULL; +static ir_type *between_type = NULL; +static ir_entity *old_bp_ent = NULL; +static ir_entity *ret_addr_ent = NULL; +static ir_entity *omit_fp_ret_addr_ent = NULL; + /** * The environment for the intrinsic mapping. */ static ia32_intrinsic_env_t intrinsic_env = { NULL, /* the isa */ NULL, /* the irg, these entities belong to */ - NULL, /* entity for first div operand (move into FPU) */ - NULL, /* entity for second div operand (move into FPU) */ - NULL, /* entity for converts ll -> d */ - NULL, /* entity for converts d -> ll */ NULL, /* entity for __divdi3 library call */ NULL, /* entity for __moddi3 library call */ NULL, /* entity for __udivdi3 library call */ NULL, /* entity for __umoddi3 library call */ - NULL, /* bias value for conversion from float to unsigned 64 */ }; -typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block); +typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block); +/** + * Used to create a Pseudo-Register or Unknown node. + */ static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, create_const_node_func func, const arch_register_t* reg) @@ -131,49 +137,46 @@ static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, return *place; block = get_irg_start_block(cg->irg); - res = func(NULL, cg->irg, block); + res = func(NULL, block); arch_set_irn_register(res, reg); *place = res; - add_irn_dep(get_irg_end(cg->irg), res); - /* add_irn_dep(get_irg_start(cg->irg), res); */ - return res; } /* Creates the unique per irg GP NoReg node. */ ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) { - return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP, + return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP, &ia32_gp_regs[REG_GP_NOREG]); } ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) { - return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP, + return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP, &ia32_vfp_regs[REG_VFP_NOREG]); } ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) { - return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM, + return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM, &ia32_xmm_regs[REG_XMM_NOREG]); } ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) { - return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP, + return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP, &ia32_gp_regs[REG_GP_UKNWN]); } ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) { - return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP, + return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP, &ia32_vfp_regs[REG_VFP_UKNWN]); } ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) { - return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM, + return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM, &ia32_xmm_regs[REG_XMM_UKNWN]); } ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) { - return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW, + return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW, &ia32_fp_cw_regs[REG_FPCW]); } @@ -342,6 +345,7 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap ia32_code_gen_t *cg = ia32_current_cg; const arch_env_t *arch_env = env->aenv; + ia32_curr_fp_ommitted = env->flags.try_omit_fp; if (! env->flags.try_omit_fp) { ir_graph *irg = env->irg; ir_node *bl = get_irg_start_block(irg); @@ -355,7 +359,7 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore); /* push ebp */ - push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp); + push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp); curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack); *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M); @@ -412,7 +416,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ ir_node *leave; /* leave */ - leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp); + leave = new_bd_ia32_Leave(NULL, bl, curr_bp); curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame); curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack); } else { @@ -429,7 +433,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ arch_register_req_type_ignore); /* pop ebp */ - pop = new_rd_ia32_PopEbp(NULL, env->irg, bl, *mem, curr_sp); + pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp); curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res); curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack); @@ -469,23 +473,11 @@ static void ia32_abi_done(void *self) { } /** - * Produces the type which sits between the stack args and the locals on the stack. - * it will contain the return address and space to store the old base pointer. - * @return The Firm type modeling the ABI between type. + * Build the between type and entities if not already build. */ -static ir_type *ia32_abi_get_between_type(void *self) -{ +static void ia32_build_between_type(void) { #define IDENT(s) new_id_from_chars(s, sizeof(s)-1) - static ir_type *omit_fp_between_type = NULL; - static ir_type *between_type = NULL; - - ia32_abi_env_t *env = self; - if (! between_type) { - ir_entity *old_bp_ent; - ir_entity *ret_addr_ent; - ir_entity *omit_fp_ret_addr_ent; - ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu); ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu); @@ -505,9 +497,36 @@ static ir_type *ia32_abi_get_between_type(void *self) set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type)); set_type_state(omit_fp_between_type, layout_fixed); } +#undef IDENT +} +/** + * Produces the type which sits between the stack args and the locals on the stack. + * it will contain the return address and space to store the old base pointer. + * @return The Firm type modeling the ABI between type. + */ +static ir_type *ia32_abi_get_between_type(void *self) +{ + ia32_abi_env_t *env = self; + + ia32_build_between_type(); return env->flags.try_omit_fp ? omit_fp_between_type : between_type; -#undef IDENT +} + +/** + * Return the stack entity that contains the return address. + */ +ir_entity *ia32_get_return_address_entity(void) { + ia32_build_between_type(); + return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent; +} + +/** + * Return the stack entity that contains the frame address. + */ +ir_entity *ia32_get_frame_address_entity(void) { + ia32_build_between_type(); + return ia32_curr_fp_ommitted ? NULL : old_bp_ent; } /** @@ -570,7 +589,6 @@ static int ia32_get_op_estimated_cost(const ir_node *irn) * @return The inverse operation or NULL if operation invertible */ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) { - ir_graph *irg; ir_mode *mode; ir_mode *irn_mode; ir_node *block, *noreg, *nomem; @@ -593,12 +611,11 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_ irn); return NULL; - irg = get_irn_irg(irn); block = get_nodes_block(irn); mode = get_irn_mode(irn); irn_mode = get_irn_mode(irn); noreg = get_irn_n(irn, 0); - nomem = new_r_NoMem(irg); + nomem = new_NoMem(); dbg = get_irn_dbg_info(irn); /* initialize structure */ @@ -612,7 +629,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_ if (get_ia32_immop_type(irn) == ia32_ImmConst) { /* we have an add with a const here */ /* invers == add with negated const */ - inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); + inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); inverse->costs += 1; copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn); set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn))); @@ -621,13 +638,13 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_ else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) { /* we have an add with a symconst here */ /* invers == sub with const */ - inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); + inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); inverse->costs += 2; copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn); } else { /* normal add: inverse == sub */ - inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1)); + inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1)); inverse->costs += 2; } #endif @@ -637,17 +654,17 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_ if (get_ia32_immop_type(irn) != ia32_ImmNone) { /* we have a sub with a const/symconst here */ /* invers == add with this const */ - inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); + inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1; copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn); } else { /* normal sub */ if (i == n_ia32_binary_left) { - inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3)); + inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3)); } else { - inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn); + inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn); } inverse->costs += 1; } @@ -657,24 +674,24 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_ #if 0 if (get_ia32_immop_type(irn) != ia32_ImmNone) { /* xor with const: inverse = xor */ - inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); + inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg); inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1; copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn); } else { /* normal xor */ - inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i)); + inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i)); inverse->costs += 1; } #endif break; case iro_ia32_Not: { - inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn); + inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn); inverse->costs += 1; break; } case iro_ia32_Neg: { - inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn); + inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn); inverse->costs += 1; break; } @@ -874,11 +891,18 @@ static void ia32_before_abi(void *self) { * Transforms the standard firm graph into * an ia32 firm graph */ -static void ia32_prepare_graph(void *self) { - ia32_code_gen_t *cg = self; +static void ia32_prepare_graph(void *self) +{ + ia32_code_gen_t *cg = self; + ir_graph *irg = cg->irg; /* do local optimizations */ - optimize_graph_df(cg->irg); + optimize_graph_df(irg); + + /* we have to do cfopt+remove_critical_edges as we can't have Bad-blocks + * or critical edges in the backend */ + optimize_cf(irg); + remove_critical_cf_edges(irg); /* TODO: we often have dead code reachable through out-edges here. So for * now we rebuild edges (as we need correct user count for code selection) @@ -935,7 +959,7 @@ ir_node *turn_back_am(ir_node *node) ir_node *mem = get_irn_n(node, n_ia32_mem); ir_node *noreg; - ir_node *load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); + ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem); ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); ia32_copy_am_attrs(load, node); @@ -1061,16 +1085,16 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { if (mode_is_float(spillmode)) { if (ia32_cg_config.use_sse2) - new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode); + new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode); else - new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode); + new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode); } else if (get_mode_size_bits(spillmode) == 128) { /* Reload 128 bit SSE registers */ - new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem); + new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem); } else - new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem); + new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem); set_ia32_op_type(new_op, ia32_AddrModeS); set_ia32_ls_mode(new_op, spillmode); @@ -1091,7 +1115,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { reg = arch_get_irn_register(node); arch_set_irn_register(proj, reg); - SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); + SET_IA32_ORIG_NODE(new_op, node); exchange(node, proj); } @@ -1107,7 +1131,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) { const ir_node *spillval = get_irn_n(node, be_pos_Spill_val); ir_mode *mode = get_spill_mode(spillval); ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *nomem = new_rd_NoMem(irg); + ir_node *nomem = new_NoMem(); ir_node *ptr = get_irg_frame(irg); ir_node *val = get_irn_n(node, be_pos_Spill_val); ir_node *store; @@ -1131,16 +1155,16 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) { if (mode_is_float(mode)) { if (ia32_cg_config.use_sse2) - store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val); + store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val); else - store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode); + store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode); } else if (get_mode_size_bits(mode) == 128) { /* Spill 128 bit SSE registers */ - store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val); + store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val); } else if (get_mode_size_bits(mode) == 8) { - store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val); + store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val); } else { - store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val); + store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val); } set_ia32_op_type(store, ia32_AddrModeD); @@ -1148,7 +1172,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) { set_ia32_frame_ent(store, ent); set_ia32_use_frame(store); set_ia32_is_spill(store); - SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node)); + SET_IA32_ORIG_NODE(store, node); DBG_OPT_SPILL2ST(node, store); if (sched_point) { @@ -1160,13 +1184,13 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) { } static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) { - ir_graph *irg = get_irn_irg(node); dbg_info *dbg = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_graph *irg = get_irn_irg(node); ir_node *frame = get_irg_frame(irg); - ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp); + ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp); set_ia32_frame_ent(push, ent); set_ia32_use_frame(push); @@ -1179,13 +1203,13 @@ static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpo } static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) { - ir_graph *irg = get_irn_irg(node); dbg_info *dbg = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_graph *irg = get_irn_irg(node); ir_node *frame = get_irg_frame(irg); - ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp); + ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp); set_ia32_frame_ent(pop, ent); set_ia32_use_frame(pop); @@ -1478,7 +1502,7 @@ static ir_node *ia32_get_pic_base(void *self) { return get_eip; block = get_irg_start_block(cg->irg); - get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block); + get_eip = new_bd_ia32_GetEIP(NULL, block); cg->get_eip = get_eip; be_dep_on_frame(get_eip); @@ -2050,9 +2074,9 @@ static void ia32_mark_remat(const void *self, ir_node *node) { } /** - * Check for Abs or Nabs. + * Check for Abs or -Abs. */ -static int is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) { +static int psi_is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) { ir_node *l, *r; pn_Cmp pnc; @@ -2079,7 +2103,47 @@ static int is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) { } /** - * Allows or disallows the creation of Psi nodes for the given Phi nodes. + * Check for Abs only + */ +static int psi_is_Abs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) { + ir_node *l, *r; + pn_Cmp pnc; + + if (cmp == NULL) + return 0; + + /* must be <, <=, >=, > */ + pnc = get_Proj_proj(sel); + if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt && + pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt) + return 0; + + l = get_Cmp_left(cmp); + r = get_Cmp_right(cmp); + + /* must be x cmp 0 */ + if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r)) + return 0; + + if ((!is_Minus(t) || get_Minus_op(t) != f) && + (!is_Minus(f) || get_Minus_op(f) != t)) + return 0; + + if (pnc & pn_Cmp_Gt) { + /* x >= 0 ? -x : x is NABS */ + if (is_Minus(t)) + return 0; + } else { + /* x < 0 ? x : -x is NABS */ + if (is_Minus(f)) + return 0; + } + return 1; +} + + +/** + * Allows or disallows the creation of Mux nodes for the given Phi nodes. * * @param sel A selector of a Cond. * @param phi_list List of Phi nodes about to be converted (linked via get_Phi_next() field) @@ -2088,30 +2152,45 @@ static int is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) { * * @return 1 if allowed, 0 otherwise */ -static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) +static int ia32_is_mux_allowed(ir_node *sel, ir_node *phi_list, int i, int j) { ir_node *phi; - ir_node *cmp = NULL; + ir_node *cmp; + pn_Cmp pn; + ir_node *cl, *cr; - /* we can't handle Psis with 64bit compares yet */ + /* we can't handle Muxs with 64bit compares yet */ if (is_Proj(sel)) { cmp = get_Proj_pred(sel); if (is_Cmp(cmp)) { ir_node *left = get_Cmp_left(cmp); ir_mode *cmp_mode = get_irn_mode(left); - if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) - return 0; + if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) { + /* 64bit Abs IS supported */ + for (phi = phi_list; phi; phi = get_Phi_next(phi)) { + ir_node *t = get_Phi_pred(phi, i); + ir_node *f = get_Phi_pred(phi, j); + + if (! psi_is_Abs(cmp, sel, t, f)) + return 0; + } + return 1; + } } else { - cmp = NULL; + /* we do not support nodes without Cmp yet */ + return 0; } + } else { + /* we do not support nodes without Cmp yet */ + return 0; } - if (ia32_cg_config.use_cmov) { - if (ia32_cg_config.use_sse2 && cmp != NULL) { - pn_Cmp pn = get_Proj_proj(sel); - ir_node *cl = get_Cmp_left(cmp); - ir_node *cr = get_Cmp_right(cmp); + pn = get_Proj_proj(sel); + cl = get_Cmp_left(cmp); + cr = get_Cmp_right(cmp); + if (ia32_cg_config.use_cmov) { + if (ia32_cg_config.use_sse2) { /* check the Phi nodes: no 64bit and no floating point cmov */ for (phi = phi_list; phi; phi = get_Phi_next(phi)) { ir_mode *mode = get_irn_mode(phi); @@ -2120,23 +2199,22 @@ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) /* check for Min, Max */ ir_node *t = get_Phi_pred(phi, i); ir_node *f = get_Phi_pred(phi, j); - int res = 0; /* SSE2 supports Min & Max */ if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) { if (cl == t && cr == f) { - /* Psi(a <=/>= b, a, b) => MIN, MAX */ - res = 1; + /* Mux(a <=/>= b, a, b) => MIN, MAX */ + continue; } else if (cl == f && cr == t) { - /* Psi(a <=/>= b, b, a) => MAX, MIN */ - res = 1; + /* Mux(a <=/>= b, b, a) => MAX, MIN */ + continue; } } - if (! res) - return 0; - - } else if (get_mode_size_bits(mode) > 32) return 0; + } else if (get_mode_size_bits(mode) > 32) { + /* no 64bit cmov */ + return 0; + } } } else { /* check the Phi nodes: no 64bit and no floating point cmov */ @@ -2147,7 +2225,11 @@ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) ir_node *t = get_Phi_pred(phi, i); ir_node *f = get_Phi_pred(phi, j); - if (! is_Abs_or_Nabs(cmp, sel, t, f)) + /* always support Mux(!float, C1, C2) */ + if (is_Const(t) && is_Const(f) && !mode_is_float(get_irn_mode(cl))) + continue; + /* only abs or nabs supported */ + if (! psi_is_Abs_or_Nabs(cmp, sel, t, f)) return 0; } else if (get_mode_size_bits(mode) > 32) return 0; @@ -2155,30 +2237,22 @@ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) } return 1; - } else { - ir_node *cl, *cr; - pn_Cmp pn; - - /* No Cmov, only some special cases */ - if (cmp == NULL) - return 0; + } else { /* No Cmov, only some special cases */ /* Now some supported cases here */ - pn = get_Proj_proj(sel); - cl = get_Cmp_left(cmp); - cr = get_Cmp_right(cmp); - for (phi = phi_list; phi; phi = get_Phi_next(phi)) { ir_mode *mode = get_irn_mode(phi); - int res = 0; ir_node *t, *f; t = get_Phi_pred(phi, i); f = get_Phi_pred(phi, j); if (mode_is_float(mode)) { + /* always support Mux(!float, C1, C2) */ + if (is_Const(t) && is_Const(f) && !mode_is_float(get_irn_mode(cl))) + continue; /* only abs or nabs supported */ - if (! is_Abs_or_Nabs(cmp, sel, t, f)) + if (! psi_is_Abs_or_Nabs(cmp, sel, t, f)) return 0; } else if (get_mode_size_bits(mode) > 32) { /* no 64bit yet */ @@ -2187,41 +2261,43 @@ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) if (is_Const(t) && is_Const(f)) { if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) { - /* always support Psi(x, C1, C2) */ - res = 1; + /* always support Mux(x, C1, C2) */ + continue; } } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) { - if (0) { #if 0 - } else if (cl == t && cr == f) { - /* Psi(a <=/>= b, a, b) => Min, Max */ - res = 1; - } else if (cl == f && cr == t) { - /* Psi(a <=/>= b, b, a) => Max, Min */ - res = 1; + if (cl == t && cr == f) { + /* Mux(a <=/>= b, a, b) => Min, Max */ + continue; + } + if (cl == f && cr == t) { + /* Mux(a <=/>= b, b, a) => Max, Min */ + continue; + } #endif - } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) && - is_Const(f) && is_Const_null(f) && is_Sub(t) && - get_Sub_left(t) == cl && get_Sub_right(t) == cr) { - /* Psi(a >=u b, a - b, 0) unsigned Doz */ - res = 1; - } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) && - is_Const(t) && is_Const_null(t) && is_Sub(f) && - get_Sub_left(f) == cl && get_Sub_right(f) == cr) { - /* Psi(a <=u b, 0, a - b) unsigned Doz */ - res = 1; - } else if (is_Const(cr) && is_Const_null(cr)) { + if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) && + is_Const(f) && is_Const_null(f) && is_Sub(t) && + get_Sub_left(t) == cl && get_Sub_right(t) == cr) { + /* Mux(a >=u b, a - b, 0) unsigned Doz */ + continue; + } + if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) && + is_Const(t) && is_Const_null(t) && is_Sub(f) && + get_Sub_left(f) == cl && get_Sub_right(f) == cr) { + /* Mux(a <=u b, 0, a - b) unsigned Doz */ + continue; + } + if (is_Const(cr) && is_Const_null(cr)) { if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) { - /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */ - res = 1; + /* Mux(a <=/>= 0 ? a : -a) Nabs/Abs */ + continue; } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) { - /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */ - res = 1; + /* Mux(a <=/>= 0 ? -a : a) Abs/Nabs */ + continue; } } } - if (! res) - return 0; + return 0; } /* all checks passed */ return 1; @@ -2246,13 +2322,40 @@ static int ia32_is_valid_clobber(const void *self, const char *clobber) return ia32_get_clobber_register(clobber) != NULL; } +/** + * Create the trampoline code. + */ +static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee) +{ + ir_graph *irg = get_Block_irg(block); + ir_node *st, *p = trampoline; + ir_mode *mode = get_irn_mode(p); + + /* mov ecx, */ + st = new_r_Store(irg, block, mem, p, new_Const_long(mode_Bu, 0xb9), 0); + mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M); + p = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 1), mode); + st = new_r_Store(irg, block, mem, p, env, 0); + mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M); + p = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 4), mode); + /* jmp */ + st = new_r_Store(irg, block, mem, p, new_Const_long(mode_Bu, 0xe9), 0); + mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M); + p = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 1), mode); + st = new_r_Store(irg, block, mem, p, callee, 0); + mem = new_r_Proj(irg, block, st, mode_M, pn_Store_M); + p = new_r_Add(irg, block, p, new_Const_long(mode_Iu, 4), mode); + + return mem; +} + /** * Returns the libFirm configuration parameter for this backend. */ static const backend_params *ia32_get_libfirm_params(void) { static const ir_settings_if_conv_t ifconv = { - 4, /* maxdepth, doesn't matter for Psi-conversion */ - ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */ + 4, /* maxdepth, doesn't matter for Mux-conversion */ + ia32_is_mux_allowed /* allows or disallows Mux creation for given selector */ }; static const ir_settings_arch_dep_t ad = { 1, /* also use subs */ @@ -2262,18 +2365,20 @@ static const backend_params *ia32_get_libfirm_params(void) { 1, /* allow Mulhs */ 1, /* allow Mulus */ - 32 /* Mulh allowed up to 32 bit */ + 32, /* Mulh allowed up to 32 bit */ }; static backend_params p = { 1, /* need dword lowering */ 1, /* support inline assembly */ - 0, /* no immediate floating point mode. */ - NULL, /* no additional opcodes */ NULL, /* will be set later */ ia32_create_intrinsic_fkt, &intrinsic_env, /* context for ia32_create_intrinsic_fkt */ - NULL, /* will be set below */ - NULL /* will be set below */ + NULL, /* ifconv info will be set below */ + NULL, /* float arithmetic mode, will be set below */ + 12, /* size of trampoline code */ + 4, /* alignment of trampoline code */ + ia32_create_trampoline_fkt, + 4 /* alignment of stack parameter */ }; ia32_setup_cg_config(); @@ -2284,6 +2389,8 @@ static const backend_params *ia32_get_libfirm_params(void) { p.dep_param = &ad; p.if_conv_info = &ifconv; + if (! ia32_cg_config.use_sse2) + p.mode_float_arithmetic = mode_E; return &p; }