X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=7b72b561e73729e550a097097095e6381f8e8e8a;hb=bd734c8925a048face4e8420228eb2deb3fc2154;hp=9e90b505f99821f8501febbf5f7dbcb135051d40;hpb=b46a6da6b265982882b0705ed5104a24d0deb154;p=libfirm

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 9e90b505f..7b72b561e 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -21,7 +21,6 @@
  * @file
  * @brief       This is the main ia32 firm backend driver.
  * @author      Christian Wuerdig
- * @version     $Id$
  */
 #include "config.h"
 
@@ -39,7 +38,6 @@
 #include "irflag.h"
 #include "irgmod.h"
 #include "irgopt.h"
-#include "irbitset.h"
 #include "irgopt.h"
 #include "irdump.h"
 #include "pdeq.h"
@@ -52,32 +50,34 @@
 #include "instrument.h"
 #include "iropt_t.h"
 #include "lower_dw.h"
-
-#include "../beabi.h"
-#include "../beirg.h"
-#include "../benode.h"
-#include "../belower.h"
-#include "../besched.h"
+#include "lower_calls.h"
+#include "lower_mode_b.h"
+#include "lower_softfloat.h"
+
+#include "beabi.h"
+#include "beirg.h"
+#include "benode.h"
+#include "belower.h"
+#include "besched.h"
 #include "be.h"
-#include "../be_t.h"
-#include "../beirgmod.h"
-#include "../be_dbgout.h"
-#include "../beblocksched.h"
-#include "../bemachine.h"
-#include "../bespillslots.h"
-#include "../bemodule.h"
-#include "../begnuas.h"
-#include "../bestate.h"
-#include "../beflags.h"
-#include "../betranshlp.h"
-#include "../belistsched.h"
-#include "../beabihelper.h"
+#include "be_t.h"
+#include "beirgmod.h"
+#include "beblocksched.h"
+#include "bespillutil.h"
+#include "bespillslots.h"
+#include "bemodule.h"
+#include "begnuas.h"
+#include "bestate.h"
+#include "beflags.h"
+#include "betranshlp.h"
+#include "belistsched.h"
+#include "beabihelper.h"
+#include "bestack.h"
 
 #include "bearch_ia32_t.h"
 
 #include "ia32_new_nodes.h"
 #include "gen_ia32_regalloc_if.h"
-#include "gen_ia32_machine.h"
 #include "ia32_common_transform.h"
 #include "ia32_transform.h"
 #include "ia32_emitter.h"
@@ -94,9 +94,9 @@
 transformer_t be_transformer = TRANSFORMER_DEFAULT;
 #endif
 
-DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-
-ir_mode         *ia32_mode_fpcw       = NULL;
+ir_mode *ia32_mode_fpcw;
+ir_mode *ia32_mode_E;
+ir_type *ia32_type_E;
 
 /** The current omit-fp state */
 static ir_type *omit_fp_between_type   = NULL;
@@ -118,7 +118,7 @@ static ia32_intrinsic_env_t intrinsic_env = {
 };
 
 
-typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
+typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
 
 /**
  * Used to create per-graph unique pseudo nodes.
@@ -148,11 +148,11 @@ ir_node *ia32_new_NoReg_gp(ir_graph *irg)
 	                    &ia32_registers[REG_GP_NOREG]);
 }
 
-ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
+ir_node *ia32_new_NoReg_fp(ir_graph *irg)
 {
 	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
-	return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
-	                    &ia32_registers[REG_VFP_NOREG]);
+	return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
+	                    &ia32_registers[REG_FP_NOREG]);
 }
 
 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
@@ -176,7 +176,7 @@ ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
 {
 	ir_graph                  *irg = get_irn_irg(irn);
-	const arch_register_req_t *req = arch_get_register_req(irn, pos);
+	const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
 
 	assert(req != NULL && "Missing register requirements");
 	if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
@@ -185,36 +185,10 @@ static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
 	if (ia32_cg_config.use_sse2) {
 		return ia32_new_NoReg_xmm(irg);
 	} else {
-		return ia32_new_NoReg_vfp(irg);
+		return ia32_new_NoReg_fp(irg);
 	}
 }
 
-static arch_irn_class_t ia32_classify(const ir_node *irn)
-{
-	arch_irn_class_t classification = arch_irn_class_none;
-
-	assert(is_ia32_irn(irn));
-
-	if (is_ia32_is_reload(irn))
-		classification |= arch_irn_class_reload;
-
-	if (is_ia32_is_spill(irn))
-		classification |= arch_irn_class_spill;
-
-	if (is_ia32_is_remat(irn))
-		classification |= arch_irn_class_remat;
-
-	return classification;
-}
-
-/**
- * The IA32 ABI callback object.
- */
-typedef struct {
-	be_abi_call_flags_bits_t flags;  /**< The call flags. */
-	ir_graph *irg;                   /**< The associated graph. */
-} ia32_abi_env_t;
-
 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
 {
 	return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
@@ -270,7 +244,7 @@ static int ia32_get_sp_bias(const ir_node *node)
 static void ia32_build_between_type(void)
 {
 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
-	if (! between_type) {
+	if (between_type == NULL) {
 		ir_type *old_bp_type   = new_type_primitive(mode_Iu);
 		ir_type *ret_addr_type = new_type_primitive(mode_Iu);
 
@@ -396,7 +370,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
 	ir_mode  *mode;
 	ir_mode  *irn_mode;
 	ir_node  *block, *noreg, *nomem;
-	dbg_info *dbg;
+	dbg_info *dbgi;
 
 	/* we cannot invert non-ia32 irns */
 	if (! is_ia32_irn(irn))
@@ -420,7 +394,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
 	irn_mode = get_irn_mode(irn);
 	noreg    = get_irn_n(irn, 0);
 	nomem    = get_irg_no_mem(irg);
-	dbg      = get_irn_dbg_info(irn);
+	dbgi     = get_irn_dbg_info(irn);
 
 	/* initialize structure */
 	inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
@@ -432,7 +406,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
 			if (get_ia32_immop_type(irn) == ia32_ImmConst) {
 				/* we have an add with a const here */
 				/* invers == add with negated const */
-				inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+				inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
 				inverse->costs   += 1;
 				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
 				set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
@@ -441,13 +415,13 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
 			else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
 				/* we have an add with a symconst here */
 				/* invers == sub with const */
-				inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+				inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
 				inverse->costs   += 2;
 				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
 			}
 			else {
 				/* normal add: inverse == sub */
-				inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
+				inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
 				inverse->costs   += 2;
 			}
 			break;
@@ -455,17 +429,17 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
 			if (get_ia32_immop_type(irn) != ia32_ImmNone) {
 				/* we have a sub with a const/symconst here */
 				/* invers == add with this const */
-				inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+				inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
 				inverse->costs   += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
 				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
 			}
 			else {
 				/* normal sub */
 				if (i == n_ia32_binary_left) {
-					inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
+					inverse->nodes[0] = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
 				}
 				else {
-					inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
+					inverse->nodes[0] = new_bd_ia32_Sub(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
 				}
 				inverse->costs += 1;
 			}
@@ -473,23 +447,23 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
 		case iro_ia32_Xor:
 			if (get_ia32_immop_type(irn) != ia32_ImmNone) {
 				/* xor with const: inverse = xor */
-				inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
+				inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
 				inverse->costs   += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
 				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
 			}
 			else {
 				/* normal xor */
-				inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
+				inverse->nodes[0] = new_bd_ia32_Xor(dbgi, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
 				inverse->costs   += 1;
 			}
 			break;
 		case iro_ia32_Not: {
-			inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
+			inverse->nodes[0] = new_bd_ia32_Not(dbgi, block, (ir_node*) irn);
 			inverse->costs   += 1;
 			break;
 		}
 		case iro_ia32_Neg: {
-			inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
+			inverse->nodes[0] = new_bd_ia32_Neg(dbgi, block, (ir_node*) irn);
 			inverse->costs   += 1;
 			break;
 		}
@@ -565,7 +539,7 @@ static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
 					/* we can't swap left/right for limited registers
 					 * (As this (currently) breaks constraint handling copies)
 					 */
-					req = arch_get_in_register_req(irn, n_ia32_binary_left);
+					req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
 					if (req->type & arch_register_req_type_limited)
 						return 0;
 					break;
@@ -631,7 +605,6 @@ static const be_abi_callbacks_t ia32_abi_callbacks = {
 
 /* register allocator interface */
 static const arch_irn_ops_t ia32_irn_ops = {
-	ia32_classify,
 	ia32_get_frame_entity,
 	ia32_set_frame_offset,
 	ia32_get_sp_bias,
@@ -689,6 +662,8 @@ static void ia32_prepare_graph(ir_graph *irg)
 
 	/* do local optimizations (mainly CSE) */
 	optimize_graph_df(irg);
+	/* backend code expects that outedges are always enabled */
+	assure_edges(irg);
 
 	if (irg_data->dump)
 		dump_ir_graph(irg, "transformed");
@@ -698,6 +673,8 @@ static void ia32_prepare_graph(ir_graph *irg)
 
 	/* do code placement, to optimize the position of constants */
 	place_code(irg);
+	/* backend code expects that outedges are always enabled */
+	assure_edges(irg);
 
 	if (irg_data->dump)
 		dump_ir_graph(irg, "place");
@@ -709,11 +686,11 @@ ir_node *ia32_turn_back_am(ir_node *node)
 	ir_graph *irg   = get_irn_irg(node);
 	ir_node  *block = get_nodes_block(node);
 	ir_node  *base  = get_irn_n(node, n_ia32_base);
-	ir_node  *index = get_irn_n(node, n_ia32_index);
+	ir_node  *idx   = get_irn_n(node, n_ia32_index);
 	ir_node  *mem   = get_irn_n(node, n_ia32_mem);
 	ir_node  *noreg;
 
-	ir_node  *load     = new_bd_ia32_Load(dbgi, block, base, index, mem);
+	ir_node  *load     = new_bd_ia32_Load(dbgi, block, base, idx, mem);
 	ir_node  *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
 
 	ia32_copy_am_attrs(load, node);
@@ -747,7 +724,6 @@ ir_node *ia32_turn_back_am(ir_node *node)
 
 	/* rewire mem-proj */
 	if (get_irn_mode(node) == mode_T) {
-		const ir_edge_t *edge;
 		foreach_out_edge(node, edge) {
 			ir_node *out = get_edge_src_irn(edge);
 			if (get_irn_mode(out) == mode_M) {
@@ -787,7 +763,6 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
 		case ia32_AddrModeD:
 			/* TODO implement this later... */
 			panic("found DestAM with flag user %+F this should not happen", node);
-			break;
 
 		default: assert(type == ia32_Normal); break;
 	}
@@ -821,7 +796,7 @@ static void ia32_before_ra(ir_graph *irg)
 static void transform_to_Load(ir_node *node)
 {
 	ir_graph *irg        = get_irn_irg(node);
-	dbg_info *dbg        = get_irn_dbg_info(node);
+	dbg_info *dbgi       = get_irn_dbg_info(node);
 	ir_node *block       = get_nodes_block(node);
 	ir_entity *ent       = be_get_frame_entity(node);
 	ir_mode *mode        = get_irn_mode(node);
@@ -839,16 +814,16 @@ static void transform_to_Load(ir_node *node)
 
 	if (mode_is_float(spillmode)) {
 		if (ia32_cg_config.use_sse2)
-			new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
+			new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
 		else
-			new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
+			new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
 	}
 	else if (get_mode_size_bits(spillmode) == 128) {
 		/* Reload 128 bit SSE registers */
-		new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
+		new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
 	}
 	else
-		new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
+		new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
 
 	set_ia32_op_type(new_op, ia32_AddrModeS);
 	set_ia32_ls_mode(new_op, spillmode);
@@ -858,7 +833,7 @@ static void transform_to_Load(ir_node *node)
 
 	DBG_OPT_RELOAD2LD(node, new_op);
 
-	proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
+	proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
 
 	if (sched_point) {
 		sched_add_after(sched_point, new_op);
@@ -880,7 +855,7 @@ static void transform_to_Load(ir_node *node)
 static void transform_to_Store(ir_node *node)
 {
 	ir_graph *irg  = get_irn_irg(node);
-	dbg_info *dbg  = get_irn_dbg_info(node);
+	dbg_info *dbgi = get_irn_dbg_info(node);
 	ir_node *block = get_nodes_block(node);
 	ir_entity *ent = be_get_frame_entity(node);
 	const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
@@ -899,21 +874,21 @@ static void transform_to_Store(ir_node *node)
 
 	if (mode_is_float(mode)) {
 		if (ia32_cg_config.use_sse2) {
-			store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
+			store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
 			res   = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
 		} else {
-			store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
-			res   = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+			store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
+			res   = new_r_Proj(store, mode_M, pn_ia32_fst_M);
 		}
 	} else if (get_mode_size_bits(mode) == 128) {
 		/* Spill 128 bit SSE registers */
-		store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
+		store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
 		res   = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
 	} else if (get_mode_size_bits(mode) == 8) {
-		store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
+		store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
 		res   = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
 	} else {
-		store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
+		store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
 		res   = new_r_Proj(store, mode_M, pn_ia32_Store_M);
 	}
 
@@ -935,13 +910,13 @@ static void transform_to_Store(ir_node *node)
 
 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
 {
-	dbg_info *dbg = get_irn_dbg_info(node);
-	ir_node *block = get_nodes_block(node);
-	ir_graph *irg = get_irn_irg(node);
-	ir_node *noreg = ia32_new_NoReg_gp(irg);
-	ir_node *frame = get_irg_frame(irg);
+	dbg_info *dbgi  = get_irn_dbg_info(node);
+	ir_node  *block = get_nodes_block(node);
+	ir_graph *irg   = get_irn_irg(node);
+	ir_node  *noreg = ia32_new_NoReg_gp(irg);
+	ir_node  *frame = get_irg_frame(irg);
 
-	ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
+	ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
 
 	set_ia32_frame_ent(push, ent);
 	set_ia32_use_frame(push);
@@ -955,13 +930,13 @@ static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_
 
 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
 {
-	dbg_info *dbg   = get_irn_dbg_info(node);
+	dbg_info *dbgi  = get_irn_dbg_info(node);
 	ir_node  *block = get_nodes_block(node);
 	ir_graph *irg   = get_irn_irg(node);
 	ir_node  *noreg = ia32_new_NoReg_gp(irg);
 	ir_node  *frame = get_irg_frame(irg);
 
-	ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg,
+	ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
 	                                  get_irg_no_mem(irg), sp);
 
 	set_ia32_frame_ent(pop, ent);
@@ -977,12 +952,12 @@ static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_e
 
 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
 {
-	dbg_info *dbg = get_irn_dbg_info(node);
-	ir_mode *spmode = mode_Iu;
+	dbg_info *dbgi   = get_irn_dbg_info(node);
+	ir_mode  *spmode = mode_Iu;
 	const arch_register_t *spreg = &ia32_registers[REG_ESP];
 	ir_node *sp;
 
-	sp = new_rd_Proj(dbg, pred, spmode, pos);
+	sp = new_rd_Proj(dbgi, pred, spmode, pos);
 	arch_set_irn_register(sp, spreg);
 
 	return sp;
@@ -995,16 +970,14 @@ static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
  */
 static void transform_MemPerm(ir_node *node)
 {
-	ir_node         *block = get_nodes_block(node);
-	ir_graph        *irg   = get_irn_irg(node);
-	ir_node         *sp    = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
-	int              arity = be_get_MemPerm_entity_arity(node);
-	ir_node        **pops  = ALLOCAN(ir_node*, arity);
-	ir_node         *in[1];
-	ir_node         *keep;
-	int              i;
-	const ir_edge_t *edge;
-	const ir_edge_t *next;
+	ir_node  *block = get_nodes_block(node);
+	ir_graph *irg   = get_irn_irg(node);
+	ir_node  *sp    = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
+	int       arity = be_get_MemPerm_entity_arity(node);
+	ir_node **pops  = ALLOCAN(ir_node*, arity);
+	ir_node  *in[1];
+	ir_node  *keep;
+	int       i;
 
 	/* create Pushs */
 	for (i = 0; i < arity; ++i) {
@@ -1065,7 +1038,7 @@ static void transform_MemPerm(ir_node *node)
 	sched_add_before(node, keep);
 
 	/* exchange memprojs */
-	foreach_out_edge_safe(node, edge, next) {
+	foreach_out_edge_safe(node, edge) {
 		ir_node *proj = get_edge_src_irn(edge);
 		int p = get_Proj_proj(proj);
 
@@ -1138,8 +1111,8 @@ need_stackent:
 				break;
 			}
 
-			case iro_ia32_vfild:
-			case iro_ia32_vfld:
+			case iro_ia32_fild:
+			case iro_ia32_fld:
 			case iro_ia32_xLoad: {
 				mode  = get_ia32_ls_mode(node);
 				align = 4;
@@ -1161,10 +1134,8 @@ need_stackent:
 			case iro_ia32_Store8Bit:
 			case iro_ia32_Store:
 			case iro_ia32_fst:
-			case iro_ia32_fstp:
-			case iro_ia32_vfist:
-			case iro_ia32_vfisttp:
-			case iro_ia32_vfst:
+			case iro_ia32_fist:
+			case iro_ia32_fisttp:
 			case iro_ia32_xStore:
 			case iro_ia32_xStoreSimple:
 #endif
@@ -1201,7 +1172,7 @@ static void introduce_epilog(ir_node *ret)
 	ir_node               *block      = get_nodes_block(ret);
 	ir_node               *first_sp   = get_irn_n(ret, n_be_Return_sp);
 	ir_node               *curr_sp    = first_sp;
-	ir_mode               *mode_gp    = mode_Iu;
+	ir_mode               *mode_gp    = ia32_reg_classes[CLASS_ia32_gp].mode;
 
 	if (!layout->sp_relative) {
 		int      n_ebp   = determine_ebp_input(ret);
@@ -1267,35 +1238,37 @@ static void introduce_prolog_epilog(ir_graph *irg)
 		ir_node *mem        = get_irg_initial_mem(irg);
 		ir_node *noreg      = ia32_new_NoReg_gp(irg);
 		ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
-		ir_node *curr_bp    = initial_bp;
-		ir_node *push       = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, curr_bp, curr_sp);
+		ir_node *push       = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, initial_bp, initial_sp);
 		ir_node *incsp;
 
 		curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
-		mem     = new_r_Proj(push, mode_M, pn_ia32_Push_M);
 		arch_set_irn_register(curr_sp, sp);
 		sched_add_after(start, push);
 
 		/* move esp to ebp */
-		curr_bp = be_new_Copy(bp->reg_class, block, curr_sp);
+		ir_node *const curr_bp = be_new_Copy(block, curr_sp);
 		sched_add_after(push, curr_bp);
 		be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
-		curr_sp = be_new_CopyKeep_single(sp->reg_class, block, curr_sp, curr_bp, mode_gp);
+		curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
 		sched_add_after(curr_bp, curr_sp);
 		be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
-		edges_reroute(initial_bp, curr_bp);
-		set_irn_n(push, n_ia32_Push_val, initial_bp);
+		edges_reroute_except(initial_bp, curr_bp, push);
 
 		incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
-		edges_reroute(initial_sp, incsp);
-		set_irn_n(push, n_ia32_Push_stack, initial_sp);
+		edges_reroute_except(initial_sp, incsp, push);
 		sched_add_after(curr_sp, incsp);
 
+		/* make sure the initial IncSP is really used by someone */
+		if (get_irn_n_edges(incsp) <= 1) {
+			ir_node *in[] = { incsp };
+			ir_node *keep = be_new_Keep(block, 1, in);
+			sched_add_after(incsp, keep);
+		}
+
 		layout->initial_bias = -4;
 	} else {
-		ir_node *incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
-		edges_reroute(initial_sp, incsp);
-		be_set_IncSP_pred(incsp, curr_sp);
+		ir_node *const incsp = be_new_IncSP(sp, block, initial_sp, frame_size, 0);
+		edges_reroute_except(initial_sp, incsp, incsp);
 		sched_add_after(start, incsp);
 	}
 
@@ -1314,11 +1287,13 @@ static void introduce_prolog_epilog(ir_graph *irg)
 }
 
 /**
- * We transform Spill and Reload here. This needs to be done before
- * stack biasing otherwise we would miss the corrected offset for these nodes.
+ * Last touchups for the graph before emit: x87 simulation to replace the
+ * virtual with real x87 instructions, creating a block schedule and peephole
+ * optimisations.
  */
-static void ia32_after_ra(ir_graph *irg)
+static void ia32_finish_graph(ir_graph *irg)
 {
+	ia32_irg_data_t   *irg_data     = ia32_get_irg_data(irg);
 	be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
 	bool               at_begin     = stack_layout->sp_relative ? true : false;
 	be_fec_env_t      *fec_env      = be_new_frame_entity_coalescer(irg);
@@ -1331,17 +1306,12 @@ static void ia32_after_ra(ir_graph *irg)
 	irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
 
 	introduce_prolog_epilog(irg);
-}
 
-/**
- * Last touchups for the graph before emit: x87 simulation to replace the
- * virtual with real x87 instructions, creating a block schedule and peephole
- * optimisations.
- */
-static void ia32_finish(ir_graph *irg)
-{
-	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+	/* fix stack entity offsets */
+	be_abi_fix_stack_nodes(irg);
+	be_abi_fix_stack_bias(irg);
 
+	/* fix 2-address code constraints */
 	ia32_finish_irg(irg);
 
 	/* we might have to rewrite x87 virtual registers */
@@ -1352,6 +1322,8 @@ static void ia32_finish(ir_graph *irg)
 	/* do peephole optimisations */
 	ia32_peephole_optimization(irg);
 
+	be_remove_dead_nodes_from_schedule(irg);
+
 	/* create block schedule, this also removes empty blocks which might
 	 * produce critical edges */
 	irg_data->blk_sched = be_create_block_schedule(irg);
@@ -1396,20 +1368,16 @@ static void ia32_init_graph(ir_graph *irg)
 	struct obstack  *obst     = be_get_be_obst(irg);
 	ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
 
-	irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
+	irg_data->dump = (be_options.dump_flags & DUMP_BE) ? 1 : 0;
 
 	if (gprof) {
 		/* Linux gprof implementation needs base pointer */
-		be_get_irg_options(irg)->omit_fp = 0;
+		be_options.omit_fp = 0;
 	}
 
 	be_birg_from_irg(irg)->isa_link = irg_data;
 }
 
-
-/**
- * Set output modes for GCC
- */
 static const tarval_mode_info mo_integer = {
 	TVO_HEX,
 	"0x",
@@ -1423,8 +1391,8 @@ static void set_tarval_output_modes(void)
 {
 	size_t i;
 
-	for (i = get_irp_n_modes(); i > 0;) {
-		ir_mode *mode = get_irp_mode(--i);
+	for (i = ir_get_n_modes(); i > 0;) {
+		ir_mode *mode = ir_get_mode(--i);
 
 		if (mode_is_int(mode))
 			set_tarval_mode_output_option(mode, &mo_integer);
@@ -1433,32 +1401,6 @@ static void set_tarval_output_modes(void)
 
 extern const arch_isa_if_t ia32_isa_if;
 
-/**
- * The template that generates a new ISA object.
- * Note that this template can be changed by command line
- * arguments.
- */
-static ia32_isa_t ia32_isa_template = {
-	{
-		&ia32_isa_if,            /* isa interface implementation */
-		N_IA32_REGISTERS,
-		ia32_registers,
-		N_IA32_CLASSES,
-		ia32_reg_classes,
-		&ia32_registers[REG_ESP],  /* stack pointer register */
-		&ia32_registers[REG_EBP],  /* base pointer register */
-		&ia32_reg_classes[CLASS_ia32_gp],  /* static link pointer register class */
-		2,                       /* power of two stack alignment, 2^2 == 4 */
-		NULL,                    /* main environment */
-		7,                       /* costs for a spill instruction */
-		5,                       /* costs for a reload instruction */
-		false,                   /* no custom abi handling */
-	},
-	NULL,                    /* types */
-	NULL,                    /* tv_ents */
-	NULL,                    /* abstract machine */
-};
-
 static void init_asm_constraints(void)
 {
 	be_init_default_asm_constraint_flags();
@@ -1507,128 +1449,431 @@ static void init_asm_constraints(void)
 }
 
 /**
- * Initializes the backend ISA.
+ * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
  */
-static arch_env_t *ia32_init(FILE *file_handle)
+static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
+                                 ir_node *mux_false)
 {
-	ia32_isa_t *isa = XMALLOC(ia32_isa_t);
-
-	set_tarval_output_modes();
-
-	*isa = ia32_isa_template;
+	ir_node    *cmp_l;
+	ir_node    *cmp_r;
+	ir_relation relation;
 
-	if (ia32_mode_fpcw == NULL) {
-		ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
-	}
+	if (!is_Cmp(sel))
+		return false;
 
-	ia32_register_init();
-	ia32_create_opcodes(&ia32_irn_ops);
+	cmp_l = get_Cmp_left(sel);
+	cmp_r = get_Cmp_right(sel);
+	if (!mode_is_float(get_irn_mode(cmp_l)))
+		return false;
 
-	be_emit_init(file_handle);
-	isa->types          = pmap_create();
-	isa->tv_ent         = pmap_create();
-	isa->cpu            = ia32_init_machine_description();
+	/* check for min/max. They're defined as (C-Semantik):
+	 *  min(a, b) = a < b ? a : b
+	 *  or min(a, b) = a <= b ? a : b
+	 *  max(a, b) = a > b ? a : b
+	 *  or max(a, b) = a >= b ? a : b
+	 * (Note we only handle float min/max here)
+	 */
+	relation = get_Cmp_relation(sel);
+	switch (relation) {
+	case ir_relation_greater_equal:
+	case ir_relation_greater:
+		/* this is a max */
+		if (cmp_l == mux_true && cmp_r == mux_false)
+			return true;
+		break;
+	case ir_relation_less_equal:
+	case ir_relation_less:
+		/* this is a min */
+		if (cmp_l == mux_true && cmp_r == mux_false)
+			return true;
+		break;
+	case ir_relation_unordered_greater_equal:
+	case ir_relation_unordered_greater:
+		/* this is a min */
+		if (cmp_l == mux_false && cmp_r == mux_true)
+			return true;
+		break;
+	case ir_relation_unordered_less_equal:
+	case ir_relation_unordered_less:
+		/* this is a max */
+		if (cmp_l == mux_false && cmp_r == mux_true)
+			return true;
+		break;
 
-	/* enter the ISA object into the intrinsic environment */
-	intrinsic_env.isa = isa;
+	default:
+		break;
+	}
 
-	return &isa->base;
+	return false;
 }
 
-
-
-/**
- * Closes the output file and frees the ISA structure.
- */
-static void ia32_done(void *self)
+static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
 {
-	ia32_isa_t *isa = (ia32_isa_t*)self;
-
-	/* emit now all global declarations */
-	be_gas_emit_decls(isa->base.main_env);
+	ir_mode *mode = get_irn_mode(mux_true);
+	(void) sel;
 
-	pmap_destroy(isa->tv_ent);
-	pmap_destroy(isa->types);
+	if (!mode_is_int(mode) && !mode_is_reference(mode)
+			&& mode != mode_b)
+		return false;
 
-	be_emit_exit();
+	if (is_Const(mux_true) && is_Const(mux_false)) {
+		/* we can create a set plus up two 3 instructions for any combination
+		 * of constants */
+		return true;
+	}
 
-	free(self);
+	return false;
 }
 
-
-/**
- * Get the register class which shall be used to store a value of a given mode.
- * @param self The this pointer.
- * @param mode The mode in question.
- * @return A register class which can hold values of the given mode.
- */
-static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
+static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
+                                     ir_node *mux_false)
 {
-	if (mode_is_float(mode)) {
-		return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
-	}
-	else
-		return &ia32_reg_classes[CLASS_ia32_gp];
+	(void) sel;
+
+	if (!mode_is_float(get_irn_mode(mux_true)))
+		return false;
+
+	return is_Const(mux_true) && is_Const(mux_false);
 }
 
-/**
- * Returns the register for parameter nr.
- */
-static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
-                                                    const ir_mode *mode)
+static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
 {
-	static const arch_register_t *gpreg_param_reg_fastcall[] = {
-		&ia32_registers[REG_ECX],
-		&ia32_registers[REG_EDX],
-		NULL
-	};
-	static const unsigned MAXNUM_GPREG_ARGS = 3;
+	ir_node    *cmp_left;
+	ir_node    *cmp_right;
+	ir_node    *sub_left;
+	ir_node    *sub_right;
+	ir_mode    *mode;
+	ir_relation relation;
 
-	static const arch_register_t *gpreg_param_reg_regparam[] = {
-		&ia32_registers[REG_EAX],
-		&ia32_registers[REG_EDX],
-		&ia32_registers[REG_ECX]
-	};
+	if (!is_Cmp(sel))
+		return false;
 
-	static const arch_register_t *gpreg_param_reg_this[] = {
-		&ia32_registers[REG_ECX],
-		NULL,
-		NULL
-	};
+	mode = get_irn_mode(mux_true);
+	if (mode_is_signed(mode) || mode_is_float(mode))
+		return false;
 
-	static const arch_register_t *fpreg_sse_param_reg_std[] = {
-		&ia32_registers[REG_XMM0],
-		&ia32_registers[REG_XMM1],
-		&ia32_registers[REG_XMM2],
-		&ia32_registers[REG_XMM3],
-		&ia32_registers[REG_XMM4],
-		&ia32_registers[REG_XMM5],
-		&ia32_registers[REG_XMM6],
-		&ia32_registers[REG_XMM7]
-	};
+	relation  = get_Cmp_relation(sel);
+	cmp_left  = get_Cmp_left(sel);
+	cmp_right = get_Cmp_right(sel);
 
-	static const arch_register_t *fpreg_sse_param_reg_this[] = {
-		NULL,  /* in case of a "this" pointer, the first parameter must not be a float */
-	};
-	static const unsigned MAXNUM_SSE_ARGS = 8;
+	/* "move" zero constant to false input */
+	if (is_Const(mux_true) && is_Const_null(mux_true)) {
+		ir_node *tmp = mux_false;
+		mux_false = mux_true;
+		mux_true  = tmp;
+		relation = get_negated_relation(relation);
+	}
+	if (!is_Const(mux_false) || !is_Const_null(mux_false))
+		return false;
+	if (!is_Sub(mux_true))
+		return false;
+	sub_left  = get_Sub_left(mux_true);
+	sub_right = get_Sub_right(mux_true);
 
-	if ((cc & cc_this_call) && nr == 0)
-		return gpreg_param_reg_this[0];
+	/* Mux(a >=u b, 0, a-b) */
+	if ((relation & ir_relation_greater)
+			&& sub_left == cmp_left && sub_right == cmp_right)
+		return true;
+	/* Mux(a <=u b, 0, b-a) */
+	if ((relation & ir_relation_less)
+			&& sub_left == cmp_right && sub_right == cmp_left)
+		return true;
 
-	if (! (cc & cc_reg_param))
-		return NULL;
+	return false;
+}
 
-	if (mode_is_float(mode)) {
-		if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
-			return NULL;
-		if (nr >= MAXNUM_SSE_ARGS)
-			return NULL;
+static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
+                               ir_node *mux_true)
+{
+	ir_mode *mode;
 
-		if (cc & cc_this_call) {
-			return fpreg_sse_param_reg_this[nr];
-		}
-		return fpreg_sse_param_reg_std[nr];
-	} else if (mode_is_int(mode) || mode_is_reference(mode)) {
+	/* middleend can handle some things */
+	if (ir_is_optimizable_mux(sel, mux_false, mux_true))
+		return true;
+	/* we can handle Set for all modes and compares */
+	if (mux_is_set(sel, mux_true, mux_false))
+		return true;
+	/* SSE has own min/max operations */
+	if (ia32_cg_config.use_sse2
+			&& mux_is_float_min_max(sel, mux_true, mux_false))
+		return true;
+	/* we can handle Mux(?, Const[f], Const[f]) */
+	if (mux_is_float_const_const(sel, mux_true, mux_false)) {
+#ifdef FIRM_GRGEN_BE
+		/* well, some code selectors can't handle it */
+		if (be_transformer != TRANSFORMER_PBQP
+				|| be_transformer != TRANSFORMER_RAND)
+			return true;
+#else
+		return true;
+#endif
+	}
+
+	/* no support for 64bit inputs to cmov */
+	mode = get_irn_mode(mux_true);
+	if (get_mode_size_bits(mode) > 32)
+		return false;
+	/* we can handle Abs for all modes and compares (except 64bit) */
+	if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
+		return true;
+	/* we can't handle MuxF yet */
+	if (mode_is_float(mode))
+		return false;
+
+	if (mux_is_doz(sel, mux_true, mux_false))
+		return true;
+
+	/* Check Cmp before the node */
+	if (is_Cmp(sel)) {
+		ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
+
+		/* we can't handle 64bit compares */
+		if (get_mode_size_bits(cmp_mode) > 32)
+			return false;
+
+		/* we can't handle float compares */
+		if (mode_is_float(cmp_mode))
+			return false;
+	}
+
+	/* did we disable cmov generation? */
+	if (!ia32_cg_config.use_cmov)
+		return false;
+
+	/* we can use a cmov */
+	return true;
+}
+
+/**
+ * Create the trampoline code.
+ */
+static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
+{
+	ir_graph *const irg  = get_irn_irg(block);
+	ir_node  *      p    = trampoline;
+	ir_mode  *const mode = get_irn_mode(p);
+	ir_node  *const one  = new_r_Const(irg, get_mode_one(mode_Iu));
+	ir_node  *const four = new_r_Const_long(irg, mode_Iu, 4);
+	ir_node  *      st;
+
+	/* mov  ecx,<env> */
+	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
+	mem = new_r_Proj(st, mode_M, pn_Store_M);
+	p   = new_r_Add(block, p, one, mode);
+	st  = new_r_Store(block, mem, p, env, cons_none);
+	mem = new_r_Proj(st, mode_M, pn_Store_M);
+	p   = new_r_Add(block, p, four, mode);
+	/* jmp  <callee> */
+	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
+	mem = new_r_Proj(st, mode_M, pn_Store_M);
+	p   = new_r_Add(block, p, one, mode);
+	st  = new_r_Store(block, mem, p, callee, cons_none);
+	mem = new_r_Proj(st, mode_M, pn_Store_M);
+
+	return mem;
+}
+
+static const ir_settings_arch_dep_t ia32_arch_dep = {
+	1,                   /* also use subs */
+	4,                   /* maximum shifts */
+	63,                  /* maximum shift amount */
+	ia32_evaluate_insn,  /* evaluate the instruction sequence */
+
+	1,  /* allow Mulhs */
+	1,  /* allow Mulus */
+	32, /* Mulh allowed up to 32 bit */
+};
+static backend_params ia32_backend_params = {
+	1,     /* support inline assembly */
+	1,     /* support Rotl nodes */
+	0,     /* little endian */
+	1,     /* modulo shift efficient */
+	0,     /* non-modulo shift not efficient */
+	&ia32_arch_dep, /* will be set later */
+	ia32_is_mux_allowed,
+	32,    /* machine_size */
+	NULL,  /* float arithmetic mode, will be set below */
+	NULL,  /* long long type */
+	NULL,  /* unsigned long long type */
+	NULL,  /* long double type */
+	12,    /* size of trampoline code */
+	4,     /* alignment of trampoline code */
+	ia32_create_trampoline_fkt,
+	4      /* alignment of stack parameter */
+};
+
+/**
+ * Initializes the backend ISA.
+ */
+static void ia32_init(void)
+{
+	ir_mode *mode_long_long;
+	ir_mode *mode_unsigned_long_long;
+	ir_type *type_long_long;
+	ir_type *type_unsigned_long_long;
+
+	ia32_setup_cg_config();
+
+	init_asm_constraints();
+
+	ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
+
+	/* note mantissa is 64bit but with explicitely encoded 1 so the really
+	 * usable part as counted by firm is only 63 bits */
+	ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
+	ia32_type_E = new_type_primitive(ia32_mode_E);
+	set_type_size_bytes(ia32_type_E, 12);
+	set_type_alignment_bytes(ia32_type_E, 4);
+
+	mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
+	type_long_long = new_type_primitive(mode_long_long);
+	mode_unsigned_long_long
+		= new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
+	type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
+
+	ia32_backend_params.type_long_long          = type_long_long;
+	ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
+
+	if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
+		ia32_backend_params.mode_float_arithmetic = NULL;
+		ia32_backend_params.type_long_double = NULL;
+	} else {
+		ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
+		ia32_backend_params.type_long_double      = ia32_type_E;
+	}
+
+	ia32_register_init();
+	obstack_init(&opcodes_obst);
+	ia32_create_opcodes(&ia32_irn_ops);
+}
+
+static void ia32_finish(void)
+{
+	if (between_type != NULL) {
+		free_type(between_type);
+		between_type = NULL;
+	}
+	ia32_free_opcodes();
+	obstack_free(&opcodes_obst, NULL);
+}
+
+/**
+ * The template that generates a new ISA object.
+ * Note that this template can be changed by command line
+ * arguments.
+ */
+static ia32_isa_t ia32_isa_template = {
+	{
+		&ia32_isa_if,            /* isa interface implementation */
+		N_IA32_REGISTERS,
+		ia32_registers,
+		N_IA32_CLASSES,
+		ia32_reg_classes,
+		&ia32_registers[REG_ESP],  /* stack pointer register */
+		&ia32_registers[REG_EBP],  /* base pointer register */
+		&ia32_reg_classes[CLASS_ia32_gp],  /* static link pointer register class */
+		2,                       /* power of two stack alignment, 2^2 == 4 */
+		NULL,                    /* main environment */
+		7,                       /* costs for a spill instruction */
+		5,                       /* costs for a reload instruction */
+		false,                   /* no custom abi handling */
+	},
+	NULL,                    /* tv_ents */
+	IA32_FPU_ARCH_X87,       /* FPU architecture */
+};
+
+static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
+{
+	ia32_isa_t *isa = XMALLOC(ia32_isa_t);
+
+	set_tarval_output_modes();
+
+	*isa        = ia32_isa_template;
+	isa->tv_ent = pmap_create();
+
+	/* enter the ISA object into the intrinsic environment */
+	intrinsic_env.isa = isa;
+
+	be_emit_init(env->file_handle);
+	be_gas_begin_compilation_unit(env);
+
+	return &isa->base;
+}
+
+/**
+ * Closes the output file and frees the ISA structure.
+ */
+static void ia32_end_codegeneration(void *self)
+{
+	ia32_isa_t *isa = (ia32_isa_t*)self;
+
+	/* emit now all global declarations */
+	be_gas_end_compilation_unit(isa->base.main_env);
+
+	be_emit_exit();
+
+	pmap_destroy(isa->tv_ent);
+	free(self);
+}
+
+/**
+ * Returns the register for parameter nr.
+ */
+static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
+                                                    const ir_mode *mode)
+{
+	static const arch_register_t *gpreg_param_reg_fastcall[] = {
+		&ia32_registers[REG_ECX],
+		&ia32_registers[REG_EDX],
+		NULL
+	};
+	static const unsigned MAXNUM_GPREG_ARGS = 3;
+
+	static const arch_register_t *gpreg_param_reg_regparam[] = {
+		&ia32_registers[REG_EAX],
+		&ia32_registers[REG_EDX],
+		&ia32_registers[REG_ECX]
+	};
+
+	static const arch_register_t *gpreg_param_reg_this[] = {
+		&ia32_registers[REG_ECX],
+		NULL,
+		NULL
+	};
+
+	static const arch_register_t *fpreg_sse_param_reg_std[] = {
+		&ia32_registers[REG_XMM0],
+		&ia32_registers[REG_XMM1],
+		&ia32_registers[REG_XMM2],
+		&ia32_registers[REG_XMM3],
+		&ia32_registers[REG_XMM4],
+		&ia32_registers[REG_XMM5],
+		&ia32_registers[REG_XMM6],
+		&ia32_registers[REG_XMM7]
+	};
+
+	static const arch_register_t *fpreg_sse_param_reg_this[] = {
+		NULL,  /* in case of a "this" pointer, the first parameter must not be a float */
+	};
+	static const unsigned MAXNUM_SSE_ARGS = 8;
+
+	if ((cc & cc_this_call) && nr == 0)
+		return gpreg_param_reg_this[0];
+
+	if (! (cc & cc_reg_param))
+		return NULL;
+
+	if (mode_is_float(mode)) {
+		if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
+			return NULL;
+		if (nr >= MAXNUM_SSE_ARGS)
+			return NULL;
+
+		if (cc & cc_this_call) {
+			return fpreg_sse_param_reg_this[nr];
+		}
+		return fpreg_sse_param_reg_std[nr];
+	} else if (mode_is_int(mode) || mode_is_reference(mode)) {
 		unsigned num_regparam;
 
 		if (get_mode_size_bits(mode) > 32)
@@ -1655,28 +1900,17 @@ static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
 
 /**
  * Get the ABI restrictions for procedure calls.
- * @param self        The this pointer.
- * @param method_type The type of the method (procedure) in question.
- * @param abi         The abi object to be modified
  */
-static void ia32_get_call_abi(const void *self, ir_type *method_type,
-                              be_abi_call_t *abi)
+static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
 {
-	ir_type  *tp;
-	ir_mode  *mode;
 	unsigned  cc;
 	int       n, i, regnum;
 	int                 pop_amount = 0;
 	be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
 
-	(void) self;
-
 	/* set abi flags for calls */
-	call_flags.bits.left_to_right         = 0;  /* always last arg first on stack */
-	call_flags.bits.store_args_sequential = 0;
 	/* call_flags.bits.try_omit_fp                 not changed: can handle both settings */
-	call_flags.bits.fp_free               = 0;  /* the frame pointer is fixed in IA32 */
-	call_flags.bits.call_has_imm          = 0;  /* No call immediate, we handle this by ourselves */
+	call_flags.bits.call_has_imm = false;  /* No call immediate, we handle this by ourselves */
 
 	/* set parameter passing style */
 	be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
@@ -1701,11 +1935,10 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 
 	n = get_method_n_params(method_type);
 	for (i = regnum = 0; i < n; i++) {
-		ir_mode               *mode;
-		const arch_register_t *reg = NULL;
+		const arch_register_t *reg  = NULL;
+		ir_type               *tp   = get_method_param_type(method_type, i);
+		ir_mode               *mode = get_type_mode(tp);
 
-		tp   = get_method_param_type(method_type, i);
-		mode = get_type_mode(tp);
 		if (mode != NULL) {
 			reg  = ia32_get_RegParam_reg(cc, regnum, mode);
 		}
@@ -1740,8 +1973,8 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 
 	/* In case of 64bit returns, we will have two 32bit values */
 	if (n == 2) {
-		tp   = get_method_res_type(method_type, 0);
-		mode = get_type_mode(tp);
+		ir_type *tp   = get_method_res_type(method_type, 0);
+		ir_mode *mode = get_type_mode(tp);
 
 		assert(!mode_is_float(mode) && "two FP results not supported");
 
@@ -1754,41 +1987,17 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 		be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
 	}
 	else if (n == 1) {
+		ir_type *tp   = get_method_res_type(method_type, 0);
+		ir_mode *mode = get_type_mode(tp);
 		const arch_register_t *reg;
-
-		tp   = get_method_res_type(method_type, 0);
 		assert(is_atomic_type(tp));
-		mode = get_type_mode(tp);
 
-		reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
+		reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
 
 		be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
 	}
 }
 
-/**
- * Returns the necessary byte alignment for storing a register of given class.
- */
-static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
-{
-	ir_mode *mode = arch_register_class_mode(cls);
-	int bytes     = get_mode_size_bytes(mode);
-
-	if (mode_is_float(mode) && bytes > 8)
-		return 16;
-	return bytes;
-}
-
-/**
- * Return irp irgs in the desired order.
- */
-static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
-{
-	(void) self;
-	(void) irg_list;
-	return NULL;
-}
-
 static void ia32_mark_remat(ir_node *node)
 {
 	if (is_ia32_irn(node)) {
@@ -1796,199 +2005,6 @@ static void ia32_mark_remat(ir_node *node)
 	}
 }
 
-/**
- * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
- */
-static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
-                                 ir_node *mux_false)
-{
-	ir_node    *cmp_l;
-	ir_node    *cmp_r;
-	ir_relation relation;
-
-	if (!is_Cmp(sel))
-		return false;
-
-	cmp_l = get_Cmp_left(sel);
-	cmp_r = get_Cmp_right(sel);
-	if (!mode_is_float(get_irn_mode(cmp_l)))
-		return false;
-
-	/* check for min/max. They're defined as (C-Semantik):
-	 *  min(a, b) = a < b ? a : b
-	 *  or min(a, b) = a <= b ? a : b
-	 *  max(a, b) = a > b ? a : b
-	 *  or max(a, b) = a >= b ? a : b
-	 * (Note we only handle float min/max here)
-	 */
-	relation = get_Cmp_relation(sel);
-	switch (relation) {
-	case ir_relation_greater_equal:
-	case ir_relation_greater:
-		/* this is a max */
-		if (cmp_l == mux_true && cmp_r == mux_false)
-			return true;
-		break;
-	case ir_relation_less_equal:
-	case ir_relation_less:
-		/* this is a min */
-		if (cmp_l == mux_true && cmp_r == mux_false)
-			return true;
-		break;
-	case ir_relation_unordered_greater_equal:
-	case ir_relation_unordered_greater:
-		/* this is a min */
-		if (cmp_l == mux_false && cmp_r == mux_true)
-			return true;
-		break;
-	case ir_relation_unordered_less_equal:
-	case ir_relation_unordered_less:
-		/* this is a max */
-		if (cmp_l == mux_false && cmp_r == mux_true)
-			return true;
-		break;
-
-	default:
-		break;
-	}
-
-	return false;
-}
-
-static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
-{
-	ir_mode *mode = get_irn_mode(mux_true);
-	(void) sel;
-
-	if (!mode_is_int(mode) && !mode_is_reference(mode)
-			&& mode != mode_b)
-		return false;
-
-	if (is_Const(mux_true) && is_Const(mux_false)) {
-		/* we can create a set plus up two 3 instructions for any combination
-		 * of constants */
-		return true;
-	}
-
-	return false;
-}
-
-static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
-                                     ir_node *mux_false)
-{
-	(void) sel;
-
-	if (!mode_is_float(get_irn_mode(mux_true)))
-		return false;
-
-	return is_Const(mux_true) && is_Const(mux_false);
-}
-
-static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
-{
-	ir_node    *cmp_left;
-	ir_node    *cmp_right;
-	ir_node    *sub_left;
-	ir_node    *sub_right;
-	ir_mode    *mode;
-	ir_relation relation;
-
-	if (!is_Cmp(sel))
-		return false;
-
-	mode = get_irn_mode(mux_true);
-	if (mode_is_signed(mode) || mode_is_float(mode))
-		return false;
-
-	relation  = get_Cmp_relation(sel);
-	cmp_left  = get_Cmp_left(sel);
-	cmp_right = get_Cmp_right(sel);
-
-	/* "move" zero constant to false input */
-	if (is_Const(mux_true) && is_Const_null(mux_true)) {
-		ir_node *tmp = mux_false;
-		mux_false = mux_true;
-		mux_true  = tmp;
-		relation = get_negated_relation(relation);
-	}
-	if (!is_Const(mux_false) || !is_Const_null(mux_false))
-		return false;
-	if (!is_Sub(mux_true))
-		return false;
-	sub_left  = get_Sub_left(mux_true);
-	sub_right = get_Sub_right(mux_true);
-
-	/* Mux(a >=u b, 0, a-b) */
-	if ((relation & ir_relation_greater)
-			&& sub_left == cmp_left && sub_right == cmp_right)
-		return true;
-	/* Mux(a <=u b, 0, b-a) */
-	if ((relation & ir_relation_less)
-			&& sub_left == cmp_right && sub_right == cmp_left)
-		return true;
-
-	return false;
-}
-
-static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
-                               ir_node *mux_true)
-{
-	ir_mode *mode;
-
-	/* we can handle Set for all modes and compares */
-	if (mux_is_set(sel, mux_true, mux_false))
-		return true;
-	/* SSE has own min/max operations */
-	if (ia32_cg_config.use_sse2
-			&& mux_is_float_min_max(sel, mux_true, mux_false))
-		return true;
-	/* we can handle Mux(?, Const[f], Const[f]) */
-	if (mux_is_float_const_const(sel, mux_true, mux_false)) {
-#ifdef FIRM_GRGEN_BE
-		/* well, some code selectors can't handle it */
-		if (be_transformer != TRANSFORMER_PBQP
-				|| be_transformer != TRANSFORMER_RAND)
-			return true;
-#else
-		return true;
-#endif
-	}
-
-	/* no support for 64bit inputs to cmov */
-	mode = get_irn_mode(mux_true);
-	if (get_mode_size_bits(mode) > 32)
-		return false;
-	/* we can handle Abs for all modes and compares (except 64bit) */
-	if (ir_mux_is_abs(sel, mux_true, mux_false) != 0)
-		return true;
-	/* we can't handle MuxF yet */
-	if (mode_is_float(mode))
-		return false;
-
-	if (mux_is_doz(sel, mux_true, mux_false))
-		return true;
-
-	/* Check Cmp before the node */
-	if (is_Cmp(sel)) {
-		ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
-
-		/* we can't handle 64bit compares */
-		if (get_mode_size_bits(cmp_mode) > 32)
-			return false;
-
-		/* we can't handle float compares */
-		if (mode_is_float(cmp_mode))
-			return false;
-	}
-
-	/* did we disable cmov generation? */
-	if (!ia32_cg_config.use_cmov)
-		return false;
-
-	/* we can use a cmov */
-	return true;
-}
-
 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
 {
 	(void) c;
@@ -2003,29 +2019,10 @@ static int ia32_is_valid_clobber(const char *clobber)
 	return ia32_get_clobber_register(clobber) != NULL;
 }
 
-static ir_node *ia32_create_set(ir_node *cond)
-{
-	/* ia32-set function produces 8-bit results which have to be converted */
-	ir_node *set   = ir_create_mux_set(cond, mode_Bu);
-	ir_node *block = get_nodes_block(set);
-	return new_r_Conv(block, set, mode_Iu);
-}
-
 static void ia32_lower_for_target(void)
 {
+	ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
 	size_t i, n_irgs = get_irp_n_irgs();
-	lower_mode_b_config_t lower_mode_b_config = {
-		mode_Iu,  /* lowered mode */
-		ia32_create_set,
-		0,        /* don't lower direct compares */
-	};
-	lower_params_t params = {
-		4,                                     /* def_ptr_alignment */
-		LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
-		ADD_HIDDEN_ALWAYS_IN_FRONT,            /* hidden_params */
-		NULL,                                  /* find pointer type */
-		NULL,                                  /* ret_compound_in_regs */
-	};
 
 	/* perform doubleword lowering */
 	lwrdw_param_t lower_dw_params = {
@@ -2035,47 +2032,42 @@ static void ia32_lower_for_target(void)
 		&intrinsic_env,
 	};
 
-	/* lower compound param handling */
-	lower_calls_with_compounds(&params);
+	/* lower compound param handling
+	 * Note: we lower compound arguments ourself, since on ia32 we don't
+	 * have hidden parameters but know where to find the structs on the stack.
+	 * (This also forces us to always allocate space for the compound arguments
+	 *  on the callframe and we can't just use an arbitrary position on the
+	 *  stackframe)
+	 */
+	lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
 
-	ir_prepare_dw_lowering(&lower_dw_params);
-	ir_lower_dw_ops();
+	/* replace floating point operations by function calls */
+	if (ia32_cg_config.use_softfloat) {
+		lower_floating_point();
+	}
 
 	for (i = 0; i < n_irgs; ++i) {
 		ir_graph *irg = get_irp_irg(i);
-		/* lower for mode_b stuff */
-		ir_lower_mode_b(irg, &lower_mode_b_config);
 		/* break up switches with wide ranges */
-		lower_switch(irg, 4, 256, false);
+		lower_switch(irg, 4, 256, mode_gp);
 	}
-}
 
-/**
- * Create the trampoline code.
- */
-static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
-{
-	ir_graph *irg  = get_irn_irg(block);
-	ir_node  *p    = trampoline;
-	ir_mode  *mode = get_irn_mode(p);
-	ir_node  *st;
+	ir_prepare_dw_lowering(&lower_dw_params);
+	ir_lower_dw_ops();
 
-	/* mov  ecx,<env> */
-	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
-	mem = new_r_Proj(st, mode_M, pn_Store_M);
-	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
-	st  = new_r_Store(block, mem, p, env, cons_none);
-	mem = new_r_Proj(st, mode_M, pn_Store_M);
-	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
-	/* jmp  <callee> */
-	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
-	mem = new_r_Proj(st, mode_M, pn_Store_M);
-	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
-	st  = new_r_Store(block, mem, p, callee, cons_none);
-	mem = new_r_Proj(st, mode_M, pn_Store_M);
-	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
+	for (i = 0; i < n_irgs; ++i) {
+		ir_graph *irg = get_irp_irg(i);
+		/* lower for mode_b stuff */
+		ir_lower_mode_b(irg, mode_Iu);
+	}
 
-	return mem;
+	for (i = 0; i < n_irgs; ++i) {
+		ir_graph *irg = get_irp_irg(i);
+		/* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
+		 * so we can generate rep movs later, and turn all big CopyBs into
+		 * memcpy calls. */
+		lower_CopyB(irg, 64, 8193, true);
+	}
 }
 
 /**
@@ -2083,39 +2075,7 @@ static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node
  */
 static const backend_params *ia32_get_libfirm_params(void)
 {
-	static const ir_settings_arch_dep_t ad = {
-		1,                   /* also use subs */
-		4,                   /* maximum shifts */
-		63,                  /* maximum shift amount */
-		ia32_evaluate_insn,  /* evaluate the instruction sequence */
-
-		1,  /* allow Mulhs */
-		1,  /* allow Mulus */
-		32, /* Mulh allowed up to 32 bit */
-	};
-	static backend_params p = {
-		1,     /* support inline assembly */
-		1,     /* support Rotl nodes */
-		0,     /* little endian */
-		NULL,  /* will be set later */
-		ia32_is_mux_allowed,
-		NULL,  /* float arithmetic mode, will be set below */
-		12,    /* size of trampoline code */
-		4,     /* alignment of trampoline code */
-		ia32_create_trampoline_fkt,
-		4      /* alignment of stack parameter */
-	};
-
-	ia32_setup_cg_config();
-
-	/* doesn't really belong here, but this is the earliest place the backend
-	 * is called... */
-	init_asm_constraints();
-
-	p.dep_param    = &ad;
-	if (! ia32_cg_config.use_sse2)
-		p.mode_float_arithmetic = mode_E;
-	return &p;
+	return &ia32_backend_params;
 }
 
 /**
@@ -2150,9 +2110,9 @@ static int ia32_register_saved_by(const arch_register_t *reg, int callee)
 		} else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
 			/* all XMM registers are caller save */
 			return reg->index != REG_XMM_NOREG;
-		} else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
-			/* all VFP registers are caller save */
-			return reg->index != REG_VFP_NOREG;
+		} else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
+			/* all FP registers are caller save */
+			return reg->index != REG_FP_NOREG;
 		}
 	}
 	return 0;
@@ -2195,27 +2155,28 @@ static const lc_opt_table_entry_t ia32_options[] = {
 
 const arch_isa_if_t ia32_isa_if = {
 	ia32_init,
-	ia32_lower_for_target,
-	ia32_done,
-	ia32_handle_intrinsics,
-	ia32_get_reg_class_for_mode,
-	ia32_get_call_abi,
-	ia32_get_reg_class_alignment,
+	ia32_finish,
 	ia32_get_libfirm_params,
-	ia32_get_irg_list,
-	ia32_mark_remat,
+	ia32_lower_for_target,
 	ia32_parse_asm_constraint,
 	ia32_is_valid_clobber,
 
+	ia32_begin_codegeneration,
+	ia32_end_codegeneration,
 	ia32_init_graph,
+	ia32_get_call_abi,
+	ia32_mark_remat,
 	ia32_get_pic_base,   /* return node used as base in pic code addresses */
+	be_new_spill,
+	be_new_reload,
+	ia32_register_saved_by,
+
+	ia32_handle_intrinsics,
 	ia32_before_abi,     /* before abi introduce hook */
 	ia32_prepare_graph,
 	ia32_before_ra,      /* before register allocation hook */
-	ia32_after_ra,       /* after register allocation hook */
-	ia32_finish,         /* called before codegen */
+	ia32_finish_graph,   /* called before codegen */
 	ia32_emit,           /* emit && done */
-	ia32_register_saved_by,
 };
 
 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
@@ -2227,8 +2188,6 @@ void be_init_arch_ia32(void)
 	lc_opt_add_table(ia32_grp, ia32_options);
 	be_register_isa_if("ia32", &ia32_isa_if);
 
-	FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
-
 	ia32_init_emitter();
 	ia32_init_finish();
 	ia32_init_optimize();