X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=6b25e8595e18df328c1e6028c2a0b73201627a5f;hb=a676ad455598022522c985e77173d169c68168f3;hp=9d0ccda1dde38c42b49afeb35e87a0a4f1312d30;hpb=998c6fe45b321549321e8bda048dc2d4ed6a33b2;p=libfirm

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 9d0ccda1d..6b25e8595 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
  *
  * This file is part of libFirm.
  *
@@ -27,8 +27,8 @@
 #include "config.h"
 #endif
 
-#include <libcore/lc_opts.h>
-#include <libcore/lc_opts_enum.h>
+#include "lc_opts.h"
+#include "lc_opts_enum.h"
 
 #include <math.h>
 
@@ -39,6 +39,7 @@
 #include "irprintf.h"
 #include "iredges_t.h"
 #include "ircons.h"
+#include "irflag.h"
 #include "irgmod.h"
 #include "irgopt.h"
 #include "irbitset.h"
@@ -49,6 +50,8 @@
 #include "error.h"
 #include "xmalloc.h"
 #include "irtools.h"
+#include "iroptimize.h"
+#include "instrument.h"
 
 #include "../beabi.h"
 #include "../beirg_t.h"
@@ -67,12 +70,14 @@
 #include "../begnuas.h"
 #include "../bestate.h"
 #include "../beflags.h"
+#include "../betranshlp.h"
 
 #include "bearch_ia32_t.h"
 
 #include "ia32_new_nodes.h"
 #include "gen_ia32_regalloc_if.h"
 #include "gen_ia32_machine.h"
+#include "ia32_common_transform.h"
 #include "ia32_transform.h"
 #include "ia32_emitter.h"
 #include "ia32_map_regs.h"
@@ -82,6 +87,11 @@
 #include "ia32_finish.h"
 #include "ia32_util.h"
 #include "ia32_fpu.h"
+#include "ia32_architecture.h"
+
+#ifdef FIRM_GRGEN_BE
+#include "ia32_pbqp_transform.h"
+#endif
 
 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
 
@@ -147,11 +157,6 @@ ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
 	                    &ia32_xmm_regs[REG_XMM_NOREG]);
 }
 
-/* Creates the unique per irg FP NoReg node. */
-ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
-	return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
-}
-
 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
 	return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
 	                    &ia32_gp_regs[REG_GP_UKNWN]);
@@ -174,9 +179,10 @@ ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
 
 
 /**
- * Returns gp_noreg or fp_noreg, depending in input requirements.
+ * Returns the admissible noreg register node for input register pos of node irn.
  */
-ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
+static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
+{
 	const arch_register_req_t *req;
 
 	req = arch_get_register_req(cg->arch_env, irn, pos);
@@ -184,7 +190,11 @@ ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
 	if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
 		return ia32_new_NoReg_gp(cg);
 
-	return ia32_new_NoReg_fp(cg);
+	if (ia32_cg_config.use_sse2) {
+		return ia32_new_NoReg_xmm(cg);
+	} else {
+		return ia32_new_NoReg_vfp(cg);
+	}
 }
 
 /**************************************************
@@ -203,15 +213,13 @@ ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
  * If the node returns a tuple (mode_T) then the proj's
  * will be asked for this information.
  */
-static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
-                                                       const ir_node *node,
+static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
 													   int pos)
 {
-	long node_pos = pos == -1 ? 0 : pos;
-	ir_mode *mode     = is_Block(node) ? NULL : get_irn_mode(node);
-	(void) self;
+	ir_mode *mode = get_irn_mode(node);
+	long    node_pos;
 
-	if (is_Block(node) || mode == mode_X) {
+	if (mode == mode_X || is_Block(node)) {
 		return arch_no_register_req;
 	}
 
@@ -219,11 +227,9 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
 		return arch_no_register_req;
 	}
 
+	node_pos = pos == -1 ? 0 : pos;
 	if (is_Proj(node)) {
-		if(mode == mode_M)
-			return arch_no_register_req;
-
-		if(pos >= 0) {
+		if (mode == mode_M || pos >= 0) {
 			return arch_no_register_req;
 		}
 
@@ -233,7 +239,7 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
 
 	if (is_ia32_irn(node)) {
 		const arch_register_req_t *req;
-		if(pos >= 0)
+		if (pos >= 0)
 			req = get_ia32_in_req(node, pos);
 		else
 			req = get_ia32_out_req(node, node_pos);
@@ -245,15 +251,12 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
 
 	/* unknowns should be transformed already */
 	assert(!is_Unknown(node));
-
 	return arch_no_register_req;
 }
 
-static void ia32_set_irn_reg(const void *self, ir_node *irn,
-                             const arch_register_t *reg)
+static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
 {
-	int                   pos = 0;
-	(void) self;
+	int    pos = 0;
 
 	if (get_irn_mode(irn) == mode_X) {
 		return;
@@ -274,12 +277,10 @@ static void ia32_set_irn_reg(const void *self, ir_node *irn,
 	}
 }
 
-static const arch_register_t *ia32_get_irn_reg(const void *self,
-                                               const ir_node *irn)
+static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
 {
 	int pos = 0;
 	const arch_register_t *reg = NULL;
-	(void) self;
 
 	if (is_Proj(irn)) {
 
@@ -303,9 +304,8 @@ static const arch_register_t *ia32_get_irn_reg(const void *self,
 	return reg;
 }
 
-static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
+static arch_irn_class_t ia32_classify(const ir_node *irn) {
 	arch_irn_class_t classification = arch_irn_class_normal;
-	(void) self;
 
 	irn = skip_Proj_const(irn);
 
@@ -321,15 +321,20 @@ static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
 	if (is_ia32_St(irn))
 		classification |= arch_irn_class_store;
 
-	if (is_ia32_need_stackent(irn))
+	if (is_ia32_is_reload(irn))
 		classification |= arch_irn_class_reload;
 
+	if (is_ia32_is_spill(irn))
+		classification |= arch_irn_class_spill;
+
+	if (is_ia32_is_remat(irn))
+		classification |= arch_irn_class_remat;
+
 	return classification;
 }
 
-static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
+static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
 	arch_irn_flags_t flags = arch_irn_flags_none;
-	(void) self;
 
 	if (is_Unknown(irn))
 		return arch_irn_flags_ignore;
@@ -356,47 +361,45 @@ static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
  */
 typedef struct {
 	be_abi_call_flags_bits_t flags;  /**< The call flags. */
-	const arch_isa_t *isa;           /**< The ISA handle. */
 	const arch_env_t *aenv;          /**< The architecture environment. */
 	ir_graph *irg;                   /**< The associated graph. */
 } ia32_abi_env_t;
 
-static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
-	(void) self;
+static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
 	return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
 }
 
-static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
-	(void) self;
+static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
 	set_ia32_frame_ent(irn, ent);
 }
 
-static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
-	const ia32_irn_ops_t *ops = self;
+static void ia32_set_frame_offset(ir_node *irn, int bias)
+{
+	if (get_ia32_frame_ent(irn) == NULL)
+		return;
 
-	if (get_ia32_frame_ent(irn)) {
-		if (is_ia32_Pop(irn)) {
-			int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
-			if (omit_fp) {
-				/* Pop nodes modify the stack pointer before calculating the destination
-				 * address, so fix this here
-				 */
-				bias -= 4;
-			}
+	if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
+		ia32_code_gen_t *cg = ia32_current_cg;
+		int omit_fp = be_abi_omit_fp(cg->birg->abi);
+		if (omit_fp) {
+			/* Pop nodes modify the stack pointer before calculating the
+			 * destination address, so fix this here
+			 */
+			bias -= 4;
 		}
-
-		add_ia32_am_offs_int(irn, bias);
 	}
+	add_ia32_am_offs_int(irn, bias);
 }
 
-static int ia32_get_sp_bias(const void *self, const ir_node *node)
+static int ia32_get_sp_bias(const ir_node *node)
 {
-	(void) self;
+	if (is_ia32_Call(node))
+		return -(int)get_ia32_call_attr_const(node)->pop;
 
 	if (is_ia32_Push(node))
 		return 4;
 
-	if (is_ia32_Pop(node))
+	if (is_ia32_Pop(node) || is_ia32_PopMem(node))
 		return -4;
 
 	return 0;
@@ -412,64 +415,69 @@ static void ia32_abi_dont_save_regs(void *self, pset *s)
 {
 	ia32_abi_env_t *env = self;
 	if(env->flags.try_omit_fp)
-		pset_insert_ptr(s, env->isa->bp);
+		pset_insert_ptr(s, env->aenv->bp);
 }
 
 /**
  * Generate the routine prologue.
  *
- * @param self    The callback object.
- * @param mem     A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param self       The callback object.
+ * @param mem        A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map    A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param stack_bias Points to the current stack bias, can be modified if needed.
  *
- * @return        The register which shall be used as a stack frame base.
+ * @return           The register which shall be used as a stack frame base.
  *
  * All nodes which define registers in @p reg_map must keep @p reg_map current.
  */
-static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
+static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
 {
-	ia32_abi_env_t *env = self;
-	const ia32_isa_t *isa     = (ia32_isa_t *)env->isa;
-	ia32_code_gen_t *cg = isa->cg;
+	ia32_abi_env_t   *env      = self;
+	ia32_code_gen_t  *cg       = ia32_current_cg;
+	const arch_env_t *arch_env = env->aenv;
 
 	if (! env->flags.try_omit_fp) {
-		ir_node *bl      = get_irg_start_block(env->irg);
-		ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
-		ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
-		ir_node *noreg = ia32_new_NoReg_gp(cg);
-		ir_node *push;
+		ir_graph *irg     =env->irg;
+		ir_node  *bl      = get_irg_start_block(irg);
+		ir_node  *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
+		ir_node  *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
+		ir_node  *noreg = ia32_new_NoReg_gp(cg);
+		ir_node  *push;
 
 		/* ALL nodes representing bp must be set to ignore. */
 		be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
 
 		/* push ebp */
-		push    = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp);
-		curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
-		*mem    = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
+		push    = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
+		curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
+		*mem    = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
 
 		/* the push must have SP out register */
-		arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+		arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
 		set_ia32_flags(push, arch_irn_flags_ignore);
 
+		/* this modifies the stack bias, because we pushed 32bit */
+		*stack_bias -= 4;
+
 		/* move esp to ebp */
-		curr_bp  = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
-		be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
-		arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
+		curr_bp  = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
+		be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
+		arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
 		be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
 
 		/* beware: the copy must be done before any other sp use */
-		curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
-		be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
-		arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+		curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
+		be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
+		arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
 		be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
 
-		be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
-		be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
+		be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
+		be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
 
-		return env->isa->bp;
+		return arch_env->bp;
 	}
 
-	return env->isa->sp;
+	return arch_env->sp;
 }
 
 /**
@@ -484,55 +492,52 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
  */
 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
 {
-	ia32_abi_env_t *env     = self;
-	ir_node        *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
-	ir_node        *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
+	ia32_abi_env_t   *env      = self;
+	const arch_env_t *arch_env = env->aenv;
+	ir_node          *curr_sp  = be_abi_reg_map_get(reg_map, arch_env->sp);
+	ir_node          *curr_bp  = be_abi_reg_map_get(reg_map, arch_env->bp);
+	ir_graph         *irg      = env->irg;
 
 	if (env->flags.try_omit_fp) {
 		/* simply remove the stack frame here */
-		curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
-		add_irn_dep(curr_sp, *mem);
+		curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
 	} else {
-		const ia32_isa_t *isa     = (ia32_isa_t *)env->isa;
-		ia32_code_gen_t *cg = isa->cg;
-		ir_mode         *mode_bp = env->isa->bp->reg_class->mode;
-		ir_graph        *irg     = current_ir_graph;
+		ir_mode *mode_bp = arch_env->bp->reg_class->mode;
 
-		if (ARCH_AMD(isa->opt_arch)) {
+		if (ia32_cg_config.use_leave) {
 			ir_node *leave;
 
 			/* leave */
-			leave   = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
+			leave   = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
 			set_ia32_flags(leave, arch_irn_flags_ignore);
 			curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
 			curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
 		} else {
-			ir_node *noreg = ia32_new_NoReg_gp(cg);
 			ir_node *pop;
 
 			/* the old SP is not needed anymore (kill the proj) */
 			assert(is_Proj(curr_sp));
-			be_kill_node(curr_sp);
+			kill_node(curr_sp);
 
 			/* copy ebp to esp */
 			curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
-			arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+			arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
 			be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
 
 			/* pop ebp */
-			pop     = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
+			pop     = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
 			set_ia32_flags(pop, arch_irn_flags_ignore);
 			curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
 			curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
 
 			*mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
 		}
-		arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
-		arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
+		arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
+		arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
 	}
 
-	be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
-	be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
+	be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
+	be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
 }
 
 /**
@@ -544,12 +549,11 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
  */
 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
 {
-	ia32_abi_env_t *env    = xmalloc(sizeof(env[0]));
-	be_abi_call_flags_t fl = be_abi_call_get_flags(call);
+	ia32_abi_env_t      *env = XMALLOC(ia32_abi_env_t);
+	be_abi_call_flags_t  fl  = be_abi_call_get_flags(call);
 	env->flags = fl.bits;
 	env->irg   = irg;
 	env->aenv  = aenv;
-	env->isa   = aenv->isa;
 	return env;
 }
 
@@ -611,11 +615,10 @@ static ir_type *ia32_abi_get_between_type(void *self)
  *
  * @return     The estimated cycle count for this operation
  */
-static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
+static int ia32_get_op_estimated_cost(const ir_node *irn)
 {
-	int cost;
+	int            cost;
 	ia32_op_type_t op_tp;
-	const ia32_irn_ops_t *ops = self;
 
 	if (is_Proj(irn))
 		return 0;
@@ -629,14 +632,10 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
 
 	if (is_ia32_CopyB(irn)) {
 		cost = 250;
-		if (ARCH_INTEL(ops->cg->arch))
-			cost += 150;
 	}
 	else if (is_ia32_CopyB_i(irn)) {
-		int size = get_ia32_pncode(irn);
+		int size = get_ia32_copyb_size(irn);
 		cost     = 20 + (int)ceil((4/3) * size);
-		if (ARCH_INTEL(ops->cg->arch))
-			cost += 150;
 	}
 	/* in case of address mode operations add additional cycles */
 	else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
@@ -645,9 +644,10 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
 			(we assume they are in cache), other memory operations cost 20
 			cycles.
 		*/
-		if(is_ia32_use_frame(irn) ||
-				(is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
-		         is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
+		if (is_ia32_use_frame(irn) || (
+		    	is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
+		    	is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
+		    )) {
 			cost += 5;
 		} else {
 			cost += 20;
@@ -666,13 +666,12 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
  * @param obstack   The obstack to use for allocation of the returned nodes array
  * @return          The inverse operation or NULL if operation invertible
  */
-static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
+static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
 	ir_graph *irg;
 	ir_mode  *mode;
 	ir_mode  *irn_mode;
 	ir_node  *block, *noreg, *nomem;
 	dbg_info *dbg;
-	(void) self;
 
 	/* we cannot invert non-ia32 irns */
 	if (! is_ia32_irn(irn))
@@ -807,76 +806,95 @@ static ir_mode *get_spill_mode(const ir_node *node)
  */
 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
 {
-	if(mode_is_float(mode)) {
-		return mode == spillmode;
-	} else {
-		return 1;
-	}
+	return !mode_is_float(mode) || mode == spillmode;
 }
 
 /**
- * Check if irn can load it's operand at position i from memory (source addressmode).
- * @param self   Pointer to irn ops itself
+ * Check if irn can load its operand at position i from memory (source addressmode).
  * @param irn    The irn to be checked
  * @param i      The operands position
  * @return Non-Zero if operand can be loaded
  */
-static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
-	ir_node *op = get_irn_n(irn, i);
-	const ir_mode *mode = get_irn_mode(op);
+static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
+{
+	ir_node       *op        = get_irn_n(irn, i);
+	const ir_mode *mode      = get_irn_mode(op);
 	const ir_mode *spillmode = get_spill_mode(op);
-	(void) self;
 
-	if (! is_ia32_irn(irn)                                  ||  /* must be an ia32 irn */
-		get_ia32_am_arity(irn) != ia32_am_binary              ||  /* must be a binary operation TODO is this necessary? */
-		get_ia32_op_type(irn) != ia32_Normal                  ||  /* must not already be a addressmode irn */
-		! (get_ia32_am_support(irn) & ia32_am_Source)         ||  /* must be capable of source addressmode */
-		! ia32_is_spillmode_compatible(mode, spillmode)       ||
-		(i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
-		is_ia32_use_frame(irn))                                  /* must not already use frame */
+	if (!is_ia32_irn(irn)                              ||  /* must be an ia32 irn */
+	    get_ia32_op_type(irn) != ia32_Normal           ||  /* must not already be a addressmode irn */
+	    !ia32_is_spillmode_compatible(mode, spillmode) ||
+	    is_ia32_use_frame(irn))                            /* must not already use frame */
 		return 0;
 
-	if (i == n_ia32_binary_left) {
-		const arch_register_req_t *req;
-		if(!is_ia32_commutative(irn))
-			return 0;
-		/* we can't swap left/right for limited registers
-		 * (As this (currently) breaks constraint handling copies)
-		 */
-		req = get_ia32_in_req(irn, n_ia32_binary_left);
-		if(req->type & arch_register_req_type_limited) {
+	switch (get_ia32_am_support(irn)) {
+		case ia32_am_none:
 			return 0;
-		}
-	}
 
-	return 1;
-}
+		case ia32_am_unary:
+			return i == n_ia32_unary_op;
 
-static void ia32_perform_memory_operand(const void *self, ir_node *irn,
-                                        ir_node *spill, unsigned int i)
-{
-	const ia32_irn_ops_t *ops = self;
-	ia32_code_gen_t      *cg  = ops->cg;
+		case ia32_am_binary:
+			switch (i) {
+				case n_ia32_binary_left: {
+					const arch_register_req_t *req;
+					if (!is_ia32_commutative(irn))
+						return 0;
+
+					/* we can't swap left/right for limited registers
+					 * (As this (currently) breaks constraint handling copies)
+					 */
+					req = get_ia32_in_req(irn, n_ia32_binary_left);
+					if (req->type & arch_register_req_type_limited)
+						return 0;
+
+					return 1;
+				}
 
-	assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
+				case n_ia32_binary_right:
+					return 1;
 
-	if (i == n_ia32_binary_left) {
-		ia32_swap_left_right(irn);
+				default:
+					return 0;
+			}
+
+		default:
+			panic("Unknown AM type");
 	}
+}
+
+static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
+                                        unsigned int i)
+{
+	ir_mode *load_mode;
+	ir_mode *dest_op_mode;
+
+	assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
 
 	set_ia32_op_type(irn, ia32_AddrModeS);
-	set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
+
+	load_mode    = get_irn_mode(get_irn_n(irn, i));
+	dest_op_mode = get_ia32_ls_mode(irn);
+	if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
+		set_ia32_ls_mode(irn, load_mode);
+	}
 	set_ia32_use_frame(irn);
 	set_ia32_need_stackent(irn);
 
-	set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
-	set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
-	set_irn_n(irn, n_ia32_mem, spill);
-
-	/* immediates are only allowed on the right side */
-	if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
+	if (i == n_ia32_binary_left                    &&
+	    get_ia32_am_support(irn) == ia32_am_binary &&
+	    /* immediates are only allowed on the right side */
+	    !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
 		ia32_swap_left_right(irn);
+		i = n_ia32_binary_right;
 	}
+
+	assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
+
+	set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
+	set_irn_n(irn, n_ia32_mem,  spill);
+	set_irn_n(irn, i,           ia32_get_admissible_noreg(ia32_current_cg, irn, i));
+	set_ia32_is_reload(irn);
 }
 
 static const be_abi_callbacks_t ia32_abi_callbacks = {
@@ -890,7 +908,7 @@ static const be_abi_callbacks_t ia32_abi_callbacks = {
 
 /* fill register allocator interface */
 
-static const arch_irn_ops_if_t ia32_irn_ops_if = {
+static const arch_irn_ops_t ia32_irn_ops = {
 	ia32_get_irn_reg_req,
 	ia32_set_irn_reg,
 	ia32_get_irn_reg,
@@ -906,13 +924,6 @@ static const arch_irn_ops_if_t ia32_irn_ops_if = {
 	ia32_perform_memory_operand,
 };
 
-ia32_irn_ops_t ia32_irn_ops = {
-	&ia32_irn_ops_if,
-	NULL
-};
-
-
-
 /**************************************************
  *                _                         _  __
  *               | |                       (_)/ _|
@@ -924,14 +935,35 @@ ia32_irn_ops_t ia32_irn_ops = {
  *                       |___/
  **************************************************/
 
+static ir_entity *mcount = NULL;
+
+#define ID(s) new_id_from_chars(s, sizeof(s) - 1)
+
 static void ia32_before_abi(void *self) {
+	lower_mode_b_config_t lower_mode_b_config = {
+		mode_Iu,  /* lowered mode */
+		mode_Bu,  /* preferred mode for set */
+		0,        /* don't lower direct compares */
+	};
 	ia32_code_gen_t *cg = self;
 
-	ir_lower_mode_b(cg->irg, mode_Iu, 0);
-	if(cg->dump)
+	ir_lower_mode_b(cg->irg, &lower_mode_b_config);
+	if (cg->dump)
 		be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
+	if (cg->gprof) {
+		if (mcount == NULL) {
+			ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
+			mcount = new_entity(get_glob_type(), ID("mcount"), tp);
+			/* FIXME: enter the right ld_ident here */
+			set_entity_ld_ident(mcount, get_entity_ident(mcount));
+			set_entity_visibility(mcount, visibility_external_allocated);
+		}
+		instrument_initcall(cg->irg, mcount);
+	}
 }
 
+transformer_t be_transformer = TRANSFORMER_DEFAULT;
+
 /**
  * Transforms the standard firm graph into
  * an ia32 firm graph
@@ -939,7 +971,7 @@ static void ia32_before_abi(void *self) {
 static void ia32_prepare_graph(void *self) {
 	ia32_code_gen_t *cg = self;
 
-	/* do local optimisations */
+	/* do local optimizations */
 	optimize_graph_df(cg->irg);
 
 	/* TODO: we often have dead code reachable through out-edges here. So for
@@ -950,13 +982,27 @@ static void ia32_prepare_graph(void *self) {
 	edges_activate(cg->irg);
 #endif
 
-	if(cg->dump)
+	if (cg->dump)
 		be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
 
-	/* transform nodes into assembler instructions */
-	ia32_transform_graph(cg);
+	switch (be_transformer) {
+		case TRANSFORMER_DEFAULT:
+			/* transform remaining nodes into assembler instructions */
+			ia32_transform_graph(cg);
+			break;
+
+#ifdef FIRM_GRGEN_BE
+		case TRANSFORMER_PBQP:
+		case TRANSFORMER_RAND:
+			/* transform nodes into assembler instructions by PBQP magic */
+			ia32_transform_graph_by_pbqp(cg);
+			break;
+#endif
+
+		default: panic("invalid transformer");
+	}
 
-	/* do local optimisations (mainly CSE) */
+	/* do local optimizations (mainly CSE) */
 	optimize_graph_df(cg->irg);
 
 	if (cg->dump)
@@ -982,7 +1028,7 @@ static void ia32_before_sched(void *self) {
 	(void) self;
 }
 
-static void turn_back_am(ir_node *node)
+ir_node *turn_back_am(ir_node *node)
 {
 	ir_graph *irg   = current_ir_graph;
 	dbg_info *dbgi  = get_irn_dbg_info(node);
@@ -990,40 +1036,34 @@ static void turn_back_am(ir_node *node)
 	ir_node  *base  = get_irn_n(node, n_ia32_base);
 	ir_node  *index = get_irn_n(node, n_ia32_index);
 	ir_node  *mem   = get_irn_n(node, n_ia32_mem);
-	ir_node  *noreg = ia32_new_NoReg_gp(ia32_current_cg);
-	ir_node  *load;
-	ir_node  *load_res;
-	ir_node  *mem_proj;
-	const ir_edge_t *edge;
+	ir_node  *noreg;
 
-	load     = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
-	load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
+	ir_node  *load     = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
+	ir_node  *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
 
 	ia32_copy_am_attrs(load, node);
+	if (is_ia32_is_reload(node))
+		set_ia32_is_reload(load);
 	set_irn_n(node, n_ia32_mem, new_NoMem());
 
-	switch (get_ia32_am_arity(node)) {
+	switch (get_ia32_am_support(node)) {
 		case ia32_am_unary:
 			set_irn_n(node, n_ia32_unary_op, load_res);
 			break;
 
 		case ia32_am_binary:
-			if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
-				assert(is_ia32_Cmp(node)  || is_ia32_Cmp8Bit(node) ||
-				       is_ia32_Test(node) || is_ia32_Test8Bit(node));
+			if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
 				set_irn_n(node, n_ia32_binary_left, load_res);
 			} else {
 				set_irn_n(node, n_ia32_binary_right, load_res);
 			}
 			break;
 
-		case ia32_am_ternary:
-			set_irn_n(node, n_ia32_binary_right, load_res);
-			break;
-
-		default: break;
+		default:
+			panic("Unknown AM type");
 	}
-	set_irn_n(node, n_ia32_base, noreg);
+	noreg = ia32_new_NoReg_gp(ia32_current_cg);
+	set_irn_n(node, n_ia32_base,  noreg);
 	set_irn_n(node, n_ia32_index, noreg);
 	set_ia32_am_offs_int(node, 0);
 	set_ia32_am_sc(node, NULL);
@@ -1031,42 +1071,43 @@ static void turn_back_am(ir_node *node)
 	clear_ia32_am_sc_sign(node);
 
 	/* rewire mem-proj */
-	if(get_irn_mode(node) == mode_T) {
-		mem_proj = NULL;
+	if (get_irn_mode(node) == mode_T) {
+		const ir_edge_t *edge;
 		foreach_out_edge(node, edge) {
 			ir_node *out = get_edge_src_irn(edge);
-			if(get_Proj_proj(out) == pn_ia32_mem) {
-				mem_proj = out;
+			if (get_irn_mode(out) == mode_M) {
+				set_Proj_pred(out, load);
+				set_Proj_proj(out, pn_ia32_Load_M);
 				break;
 			}
 		}
-
-		if(mem_proj != NULL) {
-			set_Proj_pred(mem_proj, load);
-			set_Proj_proj(mem_proj, pn_ia32_Load_M);
-		}
 	}
 
 	set_ia32_op_type(node, ia32_Normal);
-	if(sched_is_scheduled(node))
+	if (sched_is_scheduled(node))
 		sched_add_before(node, load);
+
+	return load_res;
 }
 
 static ir_node *flags_remat(ir_node *node, ir_node *after)
 {
 	/* we should turn back source address mode when rematerializing nodes */
-	ia32_op_type_t  type = get_ia32_op_type(node);
+	ia32_op_type_t type;
 	ir_node        *block;
 	ir_node        *copy;
 
-	if(is_Block(after)) {
+	if (is_Block(after)) {
 		block = after;
 	} else {
 		block = get_nodes_block(after);
 	}
 
+	type = get_ia32_op_type(node);
 	switch (type) {
-		case ia32_AddrModeS: turn_back_am(node); break;
+		case ia32_AddrModeS:
+			turn_back_am(node);
+			break;
 
 		case ia32_AddrModeD:
 			/* TODO implement this later... */
@@ -1085,8 +1126,6 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
 
 /**
  * Called before the register allocator.
- * Calculate a block schedule here. We need it for the x87
- * simulator and the emitter.
  */
 static void ia32_before_ra(void *self) {
 	ia32_code_gen_t *cg = self;
@@ -1124,13 +1163,13 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
 	}
 
 	if (mode_is_float(spillmode)) {
-		if (USE_SSE2(cg))
+		if (ia32_cg_config.use_sse2)
 			new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
 		else
 			new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
 	}
 	else if (get_mode_size_bits(spillmode) == 128) {
-		// Reload 128 bit sse registers
+		/* Reload 128 bit SSE registers */
 		new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
 	}
 	else
@@ -1140,6 +1179,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
 	set_ia32_ls_mode(new_op, spillmode);
 	set_ia32_frame_ent(new_op, ent);
 	set_ia32_use_frame(new_op);
+	set_ia32_is_reload(new_op);
 
 	DBG_OPT_RELOAD2LD(node, new_op);
 
@@ -1193,12 +1233,12 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
 	}
 
 	if (mode_is_float(mode)) {
-		if (USE_SSE2(cg))
+		if (ia32_cg_config.use_sse2)
 			store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
 		else
 			store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
 	} else if (get_mode_size_bits(mode) == 128) {
-		// Spill 128 bit SSE registers
+		/* Spill 128 bit SSE registers */
 		store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
 	} else if (get_mode_size_bits(mode) == 8) {
 		store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
@@ -1210,6 +1250,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
 	set_ia32_ls_mode(store, mode);
 	set_ia32_frame_ent(store, ent);
 	set_ia32_use_frame(store);
+	set_ia32_is_spill(store);
 	SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
 	DBG_OPT_SPILL2ST(node, store);
 
@@ -1228,12 +1269,13 @@ static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpo
 	ir_node *noreg = ia32_new_NoReg_gp(cg);
 	ir_node *frame = get_irg_frame(irg);
 
-	ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg);
+	ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
 
 	set_ia32_frame_ent(push, ent);
 	set_ia32_use_frame(push);
 	set_ia32_op_type(push, ia32_AddrModeS);
 	set_ia32_ls_mode(push, mode_Is);
+	set_ia32_is_spill(push);
 
 	sched_add_before(schedpoint, push);
 	return push;
@@ -1246,12 +1288,13 @@ static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoi
 	ir_node *noreg = ia32_new_NoReg_gp(cg);
 	ir_node *frame = get_irg_frame(irg);
 
-	ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
+	ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
 
 	set_ia32_frame_ent(pop, ent);
 	set_ia32_use_frame(pop);
 	set_ia32_op_type(pop, ia32_AddrModeD);
 	set_ia32_ls_mode(pop, mode_Is);
+	set_ia32_is_reload(pop);
 
 	sched_add_before(schedpoint, pop);
 
@@ -1273,7 +1316,7 @@ static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred,
 }
 
 /**
- * Transform memperm, currently we do this the ugly way and produce
+ * Transform MemPerm, currently we do this the ugly way and produce
  * push/pop into/from memory cascades. This is possible without using
  * any registers.
  */
@@ -1291,25 +1334,25 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
 	arity = be_get_MemPerm_entity_arity(node);
 	pops = alloca(arity * sizeof(pops[0]));
 
-	// create pushs
+	/* create Pushs */
 	for(i = 0; i < arity; ++i) {
 		ir_entity *inent = be_get_MemPerm_in_entity(node, i);
 		ir_entity *outent = be_get_MemPerm_out_entity(node, i);
 		ir_type *enttype = get_entity_type(inent);
-		int entbits = get_type_size_bits(enttype);
-		int entbits2 = get_type_size_bits(get_entity_type(outent));
+		unsigned entsize = get_type_size_bytes(enttype);
+		unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
 		ir_node *mem = get_irn_n(node, i + 1);
 		ir_node *push;
 
 		/* work around cases where entities have different sizes */
-		if(entbits2 < entbits)
-			entbits = entbits2;
-		assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
+		if(entsize2 < entsize)
+			entsize = entsize2;
+		assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
 
 		push = create_push(cg, node, node, sp, mem, inent);
 		sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
-		if(entbits == 64) {
-			// add another push after the first one
+		if(entsize == 8) {
+			/* add another push after the first one */
 			push = create_push(cg, node, node, sp, mem, inent);
 			add_ia32_am_offs_int(push, 4);
 			sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
@@ -1318,26 +1361,26 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
 		set_irn_n(node, i, new_Bad());
 	}
 
-	// create pops
+	/* create pops */
 	for(i = arity - 1; i >= 0; --i) {
 		ir_entity *inent = be_get_MemPerm_in_entity(node, i);
 		ir_entity *outent = be_get_MemPerm_out_entity(node, i);
 		ir_type *enttype = get_entity_type(outent);
-		int entbits = get_type_size_bits(enttype);
-		int entbits2 = get_type_size_bits(get_entity_type(inent));
+		unsigned entsize = get_type_size_bytes(enttype);
+		unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
 		ir_node *pop;
 
 		/* work around cases where entities have different sizes */
-		if(entbits2 < entbits)
-			entbits = entbits2;
-		assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
+		if(entsize2 < entsize)
+			entsize = entsize2;
+		assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
 
 		pop = create_pop(cg, node, node, sp, outent);
 		sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
-		if(entbits == 64) {
+		if(entsize == 8) {
 			add_ia32_am_offs_int(pop, 4);
 
-			// add another pop after the first one
+			/* add another pop after the first one */
 			pop = create_pop(cg, node, node, sp, outent);
 			sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
 		}
@@ -1346,10 +1389,10 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
 	}
 
 	in[0] = sp;
-	keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+	keep  = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
 	sched_add_before(node, keep);
 
-	// exchange memprojs
+	/* exchange memprojs */
 	foreach_out_edge_safe(node, edge, next) {
 		ir_node *proj = get_edge_src_irn(edge);
 		int p = get_Proj_proj(proj);
@@ -1360,7 +1403,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
 		set_Proj_proj(proj, pn_ia32_Pop_M);
 	}
 
-	// remove memperm
+	/* remove memperm */
 	arity = get_irn_arity(node);
 	for(i = 0; i < arity; ++i) {
 		set_irn_n(node, i, new_Bad());
@@ -1383,7 +1426,7 @@ static void ia32_after_ra_walker(ir_node *block, void *env) {
 			transform_to_Load(cg, node);
 		} else if (be_is_Spill(node)) {
 			transform_to_Store(cg, node);
-		} else if(be_is_MemPerm(node)) {
+		} else if (be_is_MemPerm(node)) {
 			transform_MemPerm(cg, node);
 		}
 	}
@@ -1405,7 +1448,11 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
 		if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
 			const ir_mode     *mode  = get_ia32_ls_mode(node);
 			const ia32_attr_t *attr  = get_ia32_attr_const(node);
-			int                align = get_mode_size_bytes(mode);
+			int                align;
+
+			if (is_ia32_is_reload(node)) {
+				mode = get_spill_mode_mode(mode);
+			}
 
 			if(attr->data.need_64bit_stackent) {
 				mode = mode_Ls;
@@ -1413,15 +1460,17 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
 			if(attr->data.need_32bit_stackent) {
 				mode = mode_Is;
 			}
+			align = get_mode_size_bytes(mode);
 			be_node_needs_frame_entity(env, node, mode, align);
 		} else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
 		           || is_ia32_vfld(node)) {
-			const ir_mode *mode = get_ia32_ls_mode(node);
-			int align = 4;
+			const ir_mode *mode  = get_ia32_ls_mode(node);
+			int            align = 4;
 			be_node_needs_frame_entity(env, node, mode, align);
 		} else if(is_ia32_FldCW(node)) {
-			const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
-			int align = 4;
+			/* although 2 byte would be enough 4 byte performs best */
+			const ir_mode *mode  = mode_Iu;
+			int            align = 4;
 			be_node_needs_frame_entity(env, node, mode, align);
 		} else {
 #ifndef NDEBUG
@@ -1429,6 +1478,7 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
  				   is_ia32_xStoreSimple(node) ||
 				   is_ia32_vfst(node) ||
 				   is_ia32_vfist(node) ||
+				   is_ia32_vfisttp(node) ||
 			       is_ia32_FnstCW(node));
 #endif
 		}
@@ -1469,7 +1519,7 @@ static void ia32_finish(void *self) {
 	}
 
 	/* do peephole optimisations */
-	ia32_peephole_optimization(irg, cg);
+	ia32_peephole_optimization(cg);
 
 	/* create block schedule, this also removes empty blocks which might
 	 * produce critical edges */
@@ -1499,10 +1549,29 @@ static void ia32_codegen(void *self) {
 	free(cg);
 }
 
+/**
+ * Returns the node representing the PIC base.
+ */
+static ir_node *ia32_get_pic_base(void *self) {
+	ir_node         *block;
+	ia32_code_gen_t *cg      = self;
+	ir_node         *get_eip = cg->get_eip;
+	if (get_eip != NULL)
+		return get_eip;
+
+	block       = get_irg_start_block(cg->irg);
+	get_eip     = new_rd_ia32_GetEIP(NULL, cg->irg, block);
+	cg->get_eip = get_eip;
+
+	be_dep_on_frame(get_eip);
+	return get_eip;
+}
+
 static void *ia32_cg_init(be_irg_t *birg);
 
 static const arch_code_generator_if_t ia32_code_gen_if = {
 	ia32_cg_init,
+	ia32_get_pic_base,   /* return node used as base in pic code addresses */
 	ia32_before_abi,     /* before abi introduce hook */
 	ia32_prepare_graph,
 	NULL,                /* spill */
@@ -1517,23 +1586,23 @@ static const arch_code_generator_if_t ia32_code_gen_if = {
  * Initializes a IA32 code generator.
  */
 static void *ia32_cg_init(be_irg_t *birg) {
-	ia32_isa_t      *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
-	ia32_code_gen_t *cg  = xcalloc(1, sizeof(*cg));
+	ia32_isa_t      *isa = (ia32_isa_t *)birg->main_env->arch_env;
+	ia32_code_gen_t *cg  = XMALLOCZ(ia32_code_gen_t);
 
 	cg->impl      = &ia32_code_gen_if;
 	cg->irg       = birg->irg;
 	cg->reg_set   = new_set(ia32_cmp_irn_reg_assoc, 1024);
-	cg->arch_env  = birg->main_env->arch_env;
 	cg->isa       = isa;
+	cg->arch_env  = birg->main_env->arch_env;
 	cg->birg      = birg;
 	cg->blk_sched = NULL;
-	cg->fp_kind   = isa->fp_kind;
 	cg->dump      = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
+	cg->gprof     = (birg->main_env->options->gprof) ? 1 : 0;
 
-	/* copy optimizations from isa for easier access */
-	cg->opt      = isa->opt;
-	cg->arch     = isa->arch;
-	cg->opt_arch = isa->opt_arch;
+	if (cg->gprof) {
+		/* Linux gprof implementation needs base pointer */
+		birg->main_env->options->omit_fp = 0;
+	}
 
 	/* enter it */
 	isa->cg = cg;
@@ -1547,8 +1616,6 @@ static void *ia32_cg_init(be_irg_t *birg) {
 
 	cur_reg_set = cg->reg_set;
 
-	ia32_irn_ops.cg = cg;
-
 	assert(ia32_current_cg == NULL);
 	ia32_current_cg = cg;
 
@@ -1604,6 +1671,7 @@ static ia32_isa_t ia32_isa_template = {
 		&ia32_gp_regs[REG_ESP],  /* stack pointer register */
 		&ia32_gp_regs[REG_EBP],  /* base pointer register */
 		-1,                      /* stack direction */
+		2,                       /* power of two stack alignment, 2^2 == 4 */
 		NULL,                    /* main environment */
 		7,                       /* costs for a spill instruction */
 		5,                       /* costs for a reload instruction */
@@ -1613,27 +1681,67 @@ static ia32_isa_t ia32_isa_template = {
 	NULL,                    /* 8bit register names high */
 	NULL,                    /* types */
 	NULL,                    /* tv_ents */
-	(0                 |
-	IA32_OPT_INCDEC    |     /* optimize add 1, sub 1 into inc/dec               default: on */
-	IA32_OPT_CC),
-	arch_pentium_4,          /* instruction architecture */
-	arch_pentium_4,          /* optimize for architecture */
-	fp_x87,                  /* floating point mode */
 	NULL,                    /* current code generator */
+	NULL,                    /* abstract machine */
 #ifndef NDEBUG
 	NULL,                    /* name obstack */
-	0                        /* name obst size */
 #endif
 };
 
-static void set_arch_costs(enum cpu_support arch);
+static void init_asm_constraints(void)
+{
+	be_init_default_asm_constraint_flags();
+
+	asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
+	asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
+	asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
+
+	/* no support for autodecrement/autoincrement */
+	asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	/* no float consts */
+	asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	/* makes no sense on x86 */
+	asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	/* no support for sse consts yet */
+	asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	/* no support for x87 consts yet */
+	asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	/* no support for mmx registers yet */
+	asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	/* not available in 32bit mode */
+	asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+	asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+
+	/* no code yet to determine register class needed... */
+	asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
+}
 
 /**
  * Initializes the backend ISA.
  */
-static void *ia32_init(FILE *file_handle) {
+static arch_env_t *ia32_init(FILE *file_handle) {
 	static int inited = 0;
 	ia32_isa_t *isa;
+	int        i, n;
 
 	if (inited)
 		return NULL;
@@ -1641,7 +1749,7 @@ static void *ia32_init(FILE *file_handle) {
 
 	set_tarval_output_modes();
 
-	isa = xmalloc(sizeof(*isa));
+	isa = XMALLOC(ia32_isa_t);
 	memcpy(isa, &ia32_isa_template, sizeof(*isa));
 
 	if(mode_fpcw == NULL) {
@@ -1649,19 +1757,7 @@ static void *ia32_init(FILE *file_handle) {
 	}
 
 	ia32_register_init();
-	ia32_create_opcodes();
-
-	set_arch_costs(isa->opt_arch);
-
-	if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
-	    (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
-		/* no SSE2 for these cpu's */
-		isa->fp_kind = fp_x87;
-
-	if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
-		/* Pentium 4 don't like inc and dec instructions */
-		isa->opt &= ~IA32_OPT_INCDEC;
-	}
+	ia32_create_opcodes(&ia32_irn_ops);
 
 	be_emit_init(file_handle);
 	isa->regs_16bit     = pmap_create();
@@ -1676,7 +1772,7 @@ static void *ia32_init(FILE *file_handle) {
 	ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
 
 #ifndef NDEBUG
-	isa->name_obst = xmalloc(sizeof(*isa->name_obst));
+	isa->name_obst = XMALLOC(struct obstack);
 	obstack_init(isa->name_obst);
 #endif /* NDEBUG */
 
@@ -1684,6 +1780,14 @@ static void *ia32_init(FILE *file_handle) {
 	intrinsic_env.isa = isa;
 	ia32_handle_intrinsics();
 
+	/* emit asm includes */
+	n = get_irp_n_asms();
+	for (i = 0; i < n; ++i) {
+		be_emit_cstring("#APP\n");
+		be_emit_ident(get_irp_asm(i));
+		be_emit_cstring("\n#NO_APP\n");
+	}
+
 	/* needed for the debug support */
 	be_gas_emit_switch_section(GAS_SECTION_TEXT);
 	be_emit_cstring(".Ltext0:\n");
@@ -1695,7 +1799,7 @@ static void *ia32_init(FILE *file_handle) {
 	 */
 	inc_master_type_visited();
 
-	return isa;
+	return &isa->arch_env;
 }
 
 
@@ -1707,7 +1811,7 @@ static void ia32_done(void *self) {
 	ia32_isa_t *isa = self;
 
 	/* emit now all global declarations */
-	be_gas_emit_decls(isa->arch_isa.main_env, 1);
+	be_gas_emit_decls(isa->arch_env.main_env, 1);
 
 	pmap_destroy(isa->regs_16bit);
 	pmap_destroy(isa->regs_8bit);
@@ -1755,10 +1859,13 @@ static const arch_register_class_t *ia32_get_reg_class(const void *self,
  * @param mode The mode in question.
  * @return A register class which can hold values of the given mode.
  */
-const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
-	const ia32_isa_t *isa = self;
+const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
+		const ir_mode *mode)
+{
+	(void) self;
+
 	if (mode_is_float(mode)) {
-		return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
+		return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
 	}
 	else
 		return &ia32_reg_classes[CLASS_ia32_gp];
@@ -1770,20 +1877,24 @@ const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const
  * @param method_type The type of the method (procedure) in question.
  * @param abi         The abi object to be modified
  */
-static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
-	const ia32_isa_t *isa = self;
+static void ia32_get_call_abi(const void *self, ir_type *method_type,
+                              be_abi_call_t *abi)
+{
 	ir_type  *tp;
 	ir_mode  *mode;
 	unsigned  cc;
 	int       n, i, regnum;
+	int                 pop_amount = 0;
 	be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
 
+	(void) self;
+
 	/* set abi flags for calls */
 	call_flags.bits.left_to_right         = 0;  /* always last arg first on stack */
 	call_flags.bits.store_args_sequential = 0;
 	/* call_flags.bits.try_omit_fp                 not changed: can handle both settings */
 	call_flags.bits.fp_free               = 0;  /* the frame pointer is fixed in IA32 */
-	call_flags.bits.call_has_imm          = 1;  /* IA32 calls can have immediate address */
+	call_flags.bits.call_has_imm          = 0;  /* No call immediates, we handle this by ourselves */
 
 	/* set parameter passing style */
 	be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
@@ -1793,8 +1904,8 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_cal
 		cc = cc_cdecl_set;
 	} else {
 		cc = get_method_calling_convention(method_type);
-		if (get_method_additional_properties(method_type) & mtp_property_private
-				&& (ia32_isa_template.opt & IA32_OPT_CC)) {
+		if (get_method_additional_properties(method_type) & mtp_property_private &&
+		    ia32_cg_config.optimize_cc) {
 			/* set the calling conventions to register parameter */
 			cc = (cc & ~cc_bits) | cc_reg_param;
 		}
@@ -1803,27 +1914,43 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_cal
 	/* we have to pop the shadow parameter ourself for compound calls */
 	if( (get_method_calling_convention(method_type) & cc_compound_ret)
 			&& !(cc & cc_reg_param)) {
-		be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
+		pop_amount += get_mode_size_bytes(mode_P_data);
 	}
 
 	n = get_method_n_params(method_type);
 	for (i = regnum = 0; i < n; i++) {
-		const ir_mode         *mode;
+		ir_mode               *mode;
 		const arch_register_t *reg = NULL;
 
 		tp   = get_method_param_type(method_type, i);
 		mode = get_type_mode(tp);
 		if (mode != NULL) {
-			reg  = ia32_get_RegParam_reg(isa->cg, cc, regnum, mode);
+			reg  = ia32_get_RegParam_reg(cc, regnum, mode);
 		}
 		if (reg != NULL) {
 			be_abi_call_param_reg(abi, i, reg);
 			++regnum;
 		} else {
-			be_abi_call_param_stack(abi, i, 4, 0, 0);
+			/* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
+			 * movl has a shorter opcode than mov[sz][bw]l */
+			ir_mode *load_mode = mode;
+
+			if (mode != NULL) {
+				unsigned size = get_mode_size_bytes(mode);
+
+				if (cc & cc_callee_clear_stk) {
+					pop_amount += (size + 3U) & ~3U;
+				}
+
+				if (size < 4) load_mode = mode_Iu;
+			}
+
+			be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
 		}
 	}
 
+	be_abi_call_set_pop(abi, pop_amount);
+
 	/* set return registers */
 	n = get_method_n_ress(method_type);
 
@@ -1857,25 +1984,6 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_cal
 	}
 }
 
-
-static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
-                                    const ir_node *irn)
-{
-	(void) self;
-	(void) irn;
-	return &ia32_irn_ops;
-}
-
-const arch_irn_handler_t ia32_irn_handler = {
-	ia32_get_irn_ops
-};
-
-const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
-{
-	(void) self;
-	return &ia32_irn_handler;
-}
-
 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
 {
 	(void) block_env;
@@ -1906,8 +2014,8 @@ static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
  * Returns the estimated execution time of an ia32 irn.
  */
 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
-	const arch_env_t *arch_env = env;
-	return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
+	(void) env;
+	return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
 }
 
 list_sched_selector_t ia32_sched_selector;
@@ -1985,16 +2093,13 @@ static const be_execution_unit_t ***ia32_get_allowed_execution_units(
 
 	if (is_ia32_irn(irn)) {
 		ret = get_ia32_exec_units(irn);
-	}
-	else if (is_be_node(irn)) {
-		if (be_is_Call(irn) || be_is_Return(irn)) {
+	} else if (is_be_node(irn)) {
+		if (be_is_Return(irn)) {
 			ret = _units_callret;
-		}
-		else if (be_is_Barrier(irn)) {
+		} else if (be_is_Barrier(irn)) {
 			ret = _units_dummy;
-		}
-		else {
-			 ret = _units_other;
+		} else {
+			ret = _units_other;
 		}
 	}
 	else {
@@ -2022,6 +2127,13 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
 	return NULL;
 }
 
+static void ia32_mark_remat(const void *self, ir_node *node) {
+	(void) self;
+	if (is_ia32_irn(node)) {
+		set_ia32_is_remat(node);
+	}
+}
+
 /**
  * Allows or disallows the creation of Psi nodes for the given Phi nodes.
  * @return 1 if allowed, 0 otherwise
@@ -2029,198 +2141,148 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
 {
 	ir_node *phi;
-
-	(void)sel;
-	(void)i;
-	(void)j;
+	ir_node *cmp = NULL;
 
 	/* we can't handle psis with 64bit compares yet */
-	if(is_Proj(sel)) {
-		ir_node *pred = get_Proj_pred(sel);
-		if(is_Cmp(pred)) {
-			ir_node *left     = get_Cmp_left(pred);
+	if (is_Proj(sel)) {
+		cmp = get_Proj_pred(sel);
+		if (is_Cmp(cmp)) {
+			ir_node *left     = get_Cmp_left(cmp);
 			ir_mode *cmp_mode = get_irn_mode(left);
-			if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
+			if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
 				return 0;
+		} else {
+			cmp = NULL;
 		}
 	}
 
-	/* check the Phi nodes */
-	for (phi = phi_list; phi; phi = get_irn_link(phi)) {
-		ir_mode *mode = get_irn_mode(phi);
-
-		if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
-			return 0;
-	}
-
-	return 1;
-}
-
-typedef struct insn_const {
-	int add_cost;       /**< cost of an add instruction */
-	int lea_cost;       /**< cost of a lea instruction */
-	int const_shf_cost; /**< cost of a constant shift instruction */
-	int cost_mul_start; /**< starting cost of a multiply instruction */
-	int cost_mul_bit;   /**< cost of multiply for every set bit */
-} insn_const;
-
-/* costs for the i386 */
-static const insn_const i386_cost = {
-	1,   /* cost of an add instruction */
-	1,   /* cost of a lea instruction */
-	2,   /* cost of a constant shift instruction */
-	6,   /* starting cost of a multiply instruction */
-	1    /* cost of multiply for every set bit */
-};
-
-/* costs for the i486 */
-static const insn_const i486_cost = {
-	1,   /* cost of an add instruction */
-	1,   /* cost of a lea instruction */
-	2,   /* cost of a constant shift instruction */
-	12,  /* starting cost of a multiply instruction */
-	1    /* cost of multiply for every set bit */
-};
-
-/* costs for the Pentium */
-static const insn_const pentium_cost = {
-	1,   /* cost of an add instruction */
-	1,   /* cost of a lea instruction */
-	1,   /* cost of a constant shift instruction */
-	11,  /* starting cost of a multiply instruction */
-	0    /* cost of multiply for every set bit */
-};
+	if (ia32_cg_config.use_cmov) {
+		if (ia32_cg_config.use_sse2 && cmp != NULL) {
+			pn_Cmp pn   = get_Proj_proj(sel);
+			ir_node *cl = get_Cmp_left(cmp);
+			ir_node *cr = get_Cmp_right(cmp);
+
+			/* check the Phi nodes: no 64bit and no floating point cmov */
+			for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
+				ir_mode *mode = get_irn_mode(phi);
+
+				if (mode_is_float(mode)) {
+					/* check for Min, Max */
+					ir_node *t = get_Phi_pred(phi, i);
+					ir_node *f = get_Phi_pred(phi, j);
+					int res    = 0;
+
+					/* SSE2 supports Min & Max */
+					if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
+						if (cl == t && cr == f) {
+							/* Psi(a <=/>= b, a, b) => MIN, MAX */
+							res = 1;
+						} else if (cl == f && cr == t) {
+							/* Psi(a <=/>= b, b, a) => MAX, MIN */
+							res = 1;
+						}
+					}
+					if (! res)
+						return 0;
+
+				} else if (get_mode_size_bits(mode) > 32)
+					return 0;
+			}
+		} else {
+			/* check the Phi nodes: no 64bit and no floating point cmov */
+			for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
+				ir_mode *mode = get_irn_mode(phi);
 
-/* costs for the Pentium Pro */
-static const insn_const pentiumpro_cost = {
-	1,   /* cost of an add instruction */
-	1,   /* cost of a lea instruction */
-	1,   /* cost of a constant shift instruction */
-	4,   /* starting cost of a multiply instruction */
-	0    /* cost of multiply for every set bit */
-};
+				if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
+					return 0;
+			}
+		}
 
-/* costs for the K6 */
-static const insn_const k6_cost = {
-	1,   /* cost of an add instruction */
-	2,   /* cost of a lea instruction */
-	1,   /* cost of a constant shift instruction */
-	3,   /* starting cost of a multiply instruction */
-	0    /* cost of multiply for every set bit */
-};
+		return 1;
+	} else {
+		ir_node *cl, *cr;
+		pn_Cmp  pn;
 
-/* costs for the Athlon */
-static const insn_const athlon_cost = {
-	1,   /* cost of an add instruction */
-	2,   /* cost of a lea instruction */
-	1,   /* cost of a constant shift instruction */
-	5,   /* starting cost of a multiply instruction */
-	0    /* cost of multiply for every set bit */
-};
+		/* No cmov, only some special cases */
+		if (cmp == NULL)
+			return 0;
 
-/* costs for the Pentium 4 */
-static const insn_const pentium4_cost = {
-	1,   /* cost of an add instruction */
-	3,   /* cost of a lea instruction */
-	4,   /* cost of a constant shift instruction */
-	15,  /* starting cost of a multiply instruction */
-	0    /* cost of multiply for every set bit */
-};
+		/* Now some supported cases here */
+		pn = get_Proj_proj(sel);
+		cl = get_Cmp_left(cmp);
+		cr = get_Cmp_right(cmp);
 
-/* costs for the Core */
-static const insn_const core_cost = {
-	1,   /* cost of an add instruction */
-	1,   /* cost of a lea instruction */
-	1,   /* cost of a constant shift instruction */
-	10,  /* starting cost of a multiply instruction */
-	0    /* cost of multiply for every set bit */
-};
+		for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
+			ir_mode *mode = get_irn_mode(phi);
+			int res = 0;
+			ir_node *t, *f;
 
-/* costs for the generic */
-static const insn_const generic_cost = {
-	1,   /* cost of an add instruction */
-	2,   /* cost of a lea instruction */
-	1,   /* cost of a constant shift instruction */
-	4,   /* starting cost of a multiply instruction */
-	0    /* cost of multiply for every set bit */
-};
+			t = get_Phi_pred(phi, i);
+			f = get_Phi_pred(phi, j);
 
-static const insn_const *arch_costs = &generic_cost;
-
-static void set_arch_costs(enum cpu_support arch) {
-	switch (arch) {
-	case arch_i386:
-		arch_costs = &i386_cost;
-		break;
-	case arch_i486:
-		arch_costs = &i486_cost;
-		break;
-	case arch_pentium:
-	case arch_pentium_mmx:
-		arch_costs = &pentium_cost;
-		break;
-	case arch_pentium_pro:
-	case arch_pentium_2:
-	case arch_pentium_3:
-		arch_costs = &pentiumpro_cost;
-		break;
-	case arch_pentium_4:
-		arch_costs = &pentium4_cost;
-		break;
-	case arch_pentium_m:
-		arch_costs = &pentiumpro_cost;
-		break;
-	case arch_core:
-		arch_costs = &core_cost;
-		break;
-	case arch_k6:
-		arch_costs = &k6_cost;
-		break;
-	case arch_athlon:
-	case arch_athlon_xp:
-	case arch_athlon_64:
-	case arch_opteron:
-		arch_costs = &athlon_cost;
-		break;
-	case arch_generic:
-	default:
-		arch_costs = &generic_cost;
-	}
-}
+			/* no floating point and no 64bit yet */
+			if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
+				return 0;
 
-/**
- * Evaluate a given simple instruction.
- */
-static int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
-	int cost;
-
-	switch (kind) {
-	case MUL:
-		cost =  arch_costs->cost_mul_start;
-		if (arch_costs->cost_mul_bit > 0) {
-			char *bitstr = get_tarval_bitpattern(tv);
-			int i;
-
-			for (i = 0; bitstr[i] != '\0'; ++i) {
-				if (bitstr[i] == '1') {
-					cost += arch_costs->cost_mul_bit;
+			if (is_Const(t) && is_Const(f)) {
+				if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
+					/* always support Psi(x, C1, C2) */
+					res = 1;
+				}
+			} else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
+				if (0) {
+#if 0
+				} else if (cl == t && cr == f) {
+					/* Psi(a <=/>= b, a, b) => Min, Max */
+					res = 1;
+				} else if (cl == f && cr == t) {
+					/* Psi(a <=/>= b, b, a) => Max, Min */
+					res = 1;
+#endif
+				} else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
+				           is_Const(f) && is_Const_null(f) && is_Sub(t) &&
+				           get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
+					/* Psi(a >=u b, a - b, 0) unsigned Doz */
+					res = 1;
+				} else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
+				           is_Const(t) && is_Const_null(t) && is_Sub(f) &&
+				           get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
+					/* Psi(a <=u b, 0, a - b) unsigned Doz */
+					res = 1;
+				} else if (is_Const(cr) && is_Const_null(cr)) {
+					if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
+						/* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
+						res = 1;
+					} else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
+						/* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
+						res = 1;
+					}
 				}
 			}
-			free(bitstr);
+			if (! res)
+				return 0;
 		}
-		return cost;
-	case LEA:
-		return arch_costs->lea_cost;
-	case ADD:
-	case SUB:
-		return arch_costs->add_cost;
-	case SHIFT:
-		return arch_costs->const_shf_cost;
-	case ZERO:
-		return arch_costs->add_cost;
-	default:
+		/* all checks passed */
 		return 1;
 	}
+	return 0;
+}
+
+static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
+{
+	(void) self;
+	(void) c;
+
+	/* we already added all our simple flags to the flags modifier list in
+	 * init, so this flag we don't know. */
+	return ASM_CONSTRAINT_FLAG_INVALID;
+}
+
+static int ia32_is_valid_clobber(const void *self, const char *clobber)
+{
+	(void) self;
+
+	return ia32_get_clobber_register(clobber) != NULL;
 }
 
 /**
@@ -2244,66 +2306,31 @@ static const backend_params *ia32_get_libfirm_params(void) {
 	static backend_params p = {
 		1,     /* need dword lowering */
 		1,     /* support inline assembly */
+		0,     /* no immediate floating point mode. */
 		NULL,  /* no additional opcodes */
 		NULL,  /* will be set later */
 		ia32_create_intrinsic_fkt,
 		&intrinsic_env,  /* context for ia32_create_intrinsic_fkt */
 		NULL,  /* will be set below */
+		NULL   /* will be set below */
 	};
 
+	ia32_setup_cg_config();
+
+	/* doesn't really belong here, but this is the earliest place the backend
+	 * is called... */
+	init_asm_constraints();
+
 	p.dep_param    = &ad;
 	p.if_conv_info = &ifconv;
 	return &p;
 }
 
-/* instruction set architectures. */
-static const lc_opt_enum_int_items_t arch_items[] = {
-	{ "386",        arch_i386, },
-	{ "486",        arch_i486, },
-	{ "pentium",    arch_pentium, },
-	{ "586",        arch_pentium, },
-	{ "pentiumpro", arch_pentium_pro, },
-	{ "686",        arch_pentium_pro, },
-	{ "pentiummmx", arch_pentium_mmx, },
-	{ "pentium2",   arch_pentium_2, },
-	{ "p2",         arch_pentium_2, },
-	{ "pentium3",   arch_pentium_3, },
-	{ "p3",         arch_pentium_3, },
-	{ "pentium4",   arch_pentium_4, },
-	{ "p4",         arch_pentium_4, },
-	{ "pentiumm",   arch_pentium_m, },
-	{ "pm",         arch_pentium_m, },
-	{ "core",       arch_core, },
-	{ "k6",         arch_k6, },
-	{ "athlon",     arch_athlon, },
-	{ "athlon-xp",  arch_athlon_xp, },
-	{ "athlon64",   arch_athlon_64, },
-	{ "opteron",    arch_opteron, },
-	{ "generic",    arch_generic, },
-	{ NULL,         0 }
-};
-
-static lc_opt_enum_int_var_t arch_var = {
-	&ia32_isa_template.arch, arch_items
-};
-
-static lc_opt_enum_int_var_t opt_arch_var = {
-	&ia32_isa_template.opt_arch, arch_items
-};
-
-static const lc_opt_enum_int_items_t fp_unit_items[] = {
-	{ "x87" ,    fp_x87 },
-	{ "sse2",    fp_sse2 },
-	{ NULL,      0 }
-};
-
-static lc_opt_enum_int_var_t fp_unit_var = {
-	&ia32_isa_template.fp_kind, fp_unit_items
-};
-
 static const lc_opt_enum_int_items_t gas_items[] = {
-	{ "normal",  GAS_FLAVOUR_NORMAL },
+	{ "elf",     GAS_FLAVOUR_ELF },
 	{ "mingw",   GAS_FLAVOUR_MINGW  },
+	{ "yasm",    GAS_FLAVOUR_YASM   },
+	{ "macho",   GAS_FLAVOUR_MACH_O },
 	{ NULL,      0 }
 };
 
@@ -2311,12 +2338,24 @@ static lc_opt_enum_int_var_t gas_var = {
 	(int*) &be_gas_flavour, gas_items
 };
 
+static const lc_opt_enum_int_items_t transformer_items[] = {
+	{ "default", TRANSFORMER_DEFAULT },
+#ifdef FIRM_GRGEN_BE
+	{ "pbqp",    TRANSFORMER_PBQP    },
+	{ "random",  TRANSFORMER_RAND    },
+#endif
+	{ NULL,      0                   }
+};
+
+static lc_opt_enum_int_var_t transformer_var = {
+	(int*)&be_transformer, transformer_items
+};
+
 static const lc_opt_table_entry_t ia32_options[] = {
-	LC_OPT_ENT_ENUM_INT("arch",      "select the instruction architecture", &arch_var),
-	LC_OPT_ENT_ENUM_INT("opt",       "optimize for instruction architecture", &opt_arch_var),
-	LC_OPT_ENT_ENUM_INT("fpunit",    "select the floating point unit", &fp_unit_var),
-	LC_OPT_ENT_NEGBIT("nooptcc",  "do not optimize calling convention", &ia32_isa_template.opt, IA32_OPT_CC),
-	LC_OPT_ENT_ENUM_INT("gasmode",   "set the GAS compatibility mode", &gas_var),
+	LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
+	LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
+	LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
+	               &ia32_isa_template.arch_env.stack_alignment),
 	LC_OPT_LAST
 };
 
@@ -2327,7 +2366,6 @@ const arch_isa_if_t ia32_isa_if = {
 	ia32_get_reg_class,
 	ia32_get_reg_class_for_mode,
 	ia32_get_call_abi,
-	ia32_get_irn_handler,
 	ia32_get_code_generator_if,
 	ia32_get_list_sched_selector,
 	ia32_get_ilp_sched_selector,
@@ -2336,6 +2374,9 @@ const arch_isa_if_t ia32_isa_if = {
 	ia32_get_allowed_execution_units,
 	ia32_get_machine,
 	ia32_get_irg_list,
+	ia32_mark_remat,
+	ia32_parse_asm_constraint,
+	ia32_is_valid_clobber
 };
 
 void ia32_init_emitter(void);
@@ -2346,7 +2387,7 @@ void ia32_init_x87(void);
 
 void be_init_arch_ia32(void)
 {
-	lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
+	lc_opt_entry_t *be_grp   = lc_opt_get_grp(firm_opt_get_root(), "be");
 	lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
 
 	lc_opt_add_table(ia32_grp, ia32_options);
@@ -2359,6 +2400,7 @@ void be_init_arch_ia32(void)
 	ia32_init_optimize();
 	ia32_init_transform();
 	ia32_init_x87();
+	ia32_init_architecture();
 }
 
 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);