X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=6b25e8595e18df328c1e6028c2a0b73201627a5f;hb=a676ad455598022522c985e77173d169c68168f3;hp=5923ae9a95449319cd01d57bd568340a17f9348c;hpb=a7d7eff700f5602dacd03a3e555cbce09b3ca360;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 5923ae9a9..6b25e8595 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -70,6 +70,7 @@ #include "../begnuas.h" #include "../bestate.h" #include "../beflags.h" +#include "../betranshlp.h" #include "bearch_ia32_t.h" @@ -180,7 +181,8 @@ ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) { /** * Returns the admissible noreg register node for input register pos of node irn. */ -ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) { +static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) +{ const arch_register_req_t *req; req = arch_get_register_req(cg->arch_env, irn, pos); @@ -319,9 +321,15 @@ static arch_irn_class_t ia32_classify(const ir_node *irn) { if (is_ia32_St(irn)) classification |= arch_irn_class_store; - if (is_ia32_need_stackent(irn)) + if (is_ia32_is_reload(irn)) classification |= arch_irn_class_reload; + if (is_ia32_is_spill(irn)) + classification |= arch_irn_class_spill; + + if (is_ia32_is_remat(irn)) + classification |= arch_irn_class_remat; + return classification; } @@ -385,6 +393,9 @@ static void ia32_set_frame_offset(ir_node *irn, int bias) static int ia32_get_sp_bias(const ir_node *node) { + if (is_ia32_Call(node)) + return -(int)get_ia32_call_attr_const(node)->pop; + if (is_ia32_Push(node)) return 4; @@ -410,15 +421,16 @@ static void ia32_abi_dont_save_regs(void *self, pset *s) /** * Generate the routine prologue. * - * @param self The callback object. - * @param mem A pointer to the mem node. Update this if you define new memory. - * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes. + * @param self The callback object. + * @param mem A pointer to the mem node. Update this if you define new memory. + * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes. + * @param stack_bias Points to the current stack bias, can be modified if needed. * - * @return The register which shall be used as a stack frame base. + * @return The register which shall be used as a stack frame base. * * All nodes which define registers in @p reg_map must keep @p reg_map current. */ -static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map) +static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) { ia32_abi_env_t *env = self; ia32_code_gen_t *cg = ia32_current_cg; @@ -444,6 +456,9 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap arch_set_irn_register(arch_env, curr_sp, arch_env->sp); set_ia32_flags(push, arch_irn_flags_ignore); + /* this modifies the stack bias, because we pushed 32bit */ + *stack_bias -= 4; + /* move esp to ebp */ curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp); be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp); @@ -493,7 +508,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ ir_node *leave; /* leave */ - leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp); + leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp); set_ia32_flags(leave, arch_irn_flags_ignore); curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame); curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack); @@ -534,8 +549,8 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ */ static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg) { - ia32_abi_env_t *env = xmalloc(sizeof(env[0])); - be_abi_call_flags_t fl = be_abi_call_get_flags(call); + ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t); + be_abi_call_flags_t fl = be_abi_call_get_flags(call); env->flags = fl.bits; env->irg = irg; env->aenv = aenv; @@ -791,75 +806,95 @@ static ir_mode *get_spill_mode(const ir_node *node) */ static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode) { - if(mode_is_float(mode)) { - return mode == spillmode; - } else { - return 1; - } + return !mode_is_float(mode) || mode == spillmode; } /** * Check if irn can load its operand at position i from memory (source addressmode). - * @param self Pointer to irn ops itself * @param irn The irn to be checked * @param i The operands position * @return Non-Zero if operand can be loaded */ -static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) { - ir_node *op = get_irn_n(irn, i); - const ir_mode *mode = get_irn_mode(op); +static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) +{ + ir_node *op = get_irn_n(irn, i); + const ir_mode *mode = get_irn_mode(op); const ir_mode *spillmode = get_spill_mode(op); - if ( - (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */ - ! is_ia32_irn(irn) || /* must be an ia32 irn */ - get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */ - get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */ - ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */ - ! ia32_is_spillmode_compatible(mode, spillmode) || - is_ia32_use_frame(irn)) /* must not already use frame */ + if (!is_ia32_irn(irn) || /* must be an ia32 irn */ + get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */ + !ia32_is_spillmode_compatible(mode, spillmode) || + is_ia32_use_frame(irn)) /* must not already use frame */ return 0; - if (i == n_ia32_binary_left) { - const arch_register_req_t *req; - if(!is_ia32_commutative(irn)) + switch (get_ia32_am_support(irn)) { + case ia32_am_none: return 0; - /* we can't swap left/right for limited registers - * (As this (currently) breaks constraint handling copies) - */ - req = get_ia32_in_req(irn, n_ia32_binary_left); - if (req->type & arch_register_req_type_limited) { - return 0; - } - } - return 1; + case ia32_am_unary: + return i == n_ia32_unary_op; + + case ia32_am_binary: + switch (i) { + case n_ia32_binary_left: { + const arch_register_req_t *req; + if (!is_ia32_commutative(irn)) + return 0; + + /* we can't swap left/right for limited registers + * (As this (currently) breaks constraint handling copies) + */ + req = get_ia32_in_req(irn, n_ia32_binary_left); + if (req->type & arch_register_req_type_limited) + return 0; + + return 1; + } + + case n_ia32_binary_right: + return 1; + + default: + return 0; + } + + default: + panic("Unknown AM type"); + } } static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill, unsigned int i) { - ia32_code_gen_t *cg = ia32_current_cg; + ir_mode *load_mode; + ir_mode *dest_op_mode; assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change"); - if (i == n_ia32_binary_left) { - ia32_swap_left_right(irn); - } - set_ia32_op_type(irn, ia32_AddrModeS); - set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i))); + + load_mode = get_irn_mode(get_irn_n(irn, i)); + dest_op_mode = get_ia32_ls_mode(irn); + if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) { + set_ia32_ls_mode(irn, load_mode); + } set_ia32_use_frame(irn); set_ia32_need_stackent(irn); - set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn))); - set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right)); - set_irn_n(irn, n_ia32_mem, spill); - - /* immediates are only allowed on the right side */ - if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) { + if (i == n_ia32_binary_left && + get_ia32_am_support(irn) == ia32_am_binary && + /* immediates are only allowed on the right side */ + !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) { ia32_swap_left_right(irn); + i = n_ia32_binary_right; } + + assert(is_NoMem(get_irn_n(irn, n_ia32_mem))); + + set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn))); + set_irn_n(irn, n_ia32_mem, spill); + set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i)); + set_ia32_is_reload(irn); } static const be_abi_callbacks_t ia32_abi_callbacks = { @@ -907,7 +942,7 @@ static ir_entity *mcount = NULL; static void ia32_before_abi(void *self) { lower_mode_b_config_t lower_mode_b_config = { mode_Iu, /* lowered mode */ - mode_Bu, /* prefered mode for set */ + mode_Bu, /* preferred mode for set */ 0, /* don't lower direct compares */ }; ia32_code_gen_t *cg = self; @@ -958,15 +993,9 @@ static void ia32_prepare_graph(void *self) { #ifdef FIRM_GRGEN_BE case TRANSFORMER_PBQP: - // disable CSE, because of two-step node-construction - set_opt_cse(0); - + case TRANSFORMER_RAND: /* transform nodes into assembler instructions by PBQP magic */ ia32_transform_graph_by_pbqp(cg); - - if (cg->dump) - be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched); - set_opt_cse(1); break; #endif @@ -999,7 +1028,7 @@ static void ia32_before_sched(void *self) { (void) self; } -static void turn_back_am(ir_node *node) +ir_node *turn_back_am(ir_node *node) { ir_graph *irg = current_ir_graph; dbg_info *dbgi = get_irn_dbg_info(node); @@ -1007,40 +1036,34 @@ static void turn_back_am(ir_node *node) ir_node *base = get_irn_n(node, n_ia32_base); ir_node *index = get_irn_n(node, n_ia32_index); ir_node *mem = get_irn_n(node, n_ia32_mem); - ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg); - ir_node *load; - ir_node *load_res; - ir_node *mem_proj; - const ir_edge_t *edge; + ir_node *noreg; - load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); - load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); + ir_node *load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem); + ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res); ia32_copy_am_attrs(load, node); + if (is_ia32_is_reload(node)) + set_ia32_is_reload(load); set_irn_n(node, n_ia32_mem, new_NoMem()); - switch (get_ia32_am_arity(node)) { + switch (get_ia32_am_support(node)) { case ia32_am_unary: set_irn_n(node, n_ia32_unary_op, load_res); break; case ia32_am_binary: - if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) { - assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) || - is_ia32_Test(node) || is_ia32_Test8Bit(node)); + if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) { set_irn_n(node, n_ia32_binary_left, load_res); } else { set_irn_n(node, n_ia32_binary_right, load_res); } break; - case ia32_am_ternary: - set_irn_n(node, n_ia32_binary_right, load_res); - break; - - default: break; + default: + panic("Unknown AM type"); } - set_irn_n(node, n_ia32_base, noreg); + noreg = ia32_new_NoReg_gp(ia32_current_cg); + set_irn_n(node, n_ia32_base, noreg); set_irn_n(node, n_ia32_index, noreg); set_ia32_am_offs_int(node, 0); set_ia32_am_sc(node, NULL); @@ -1049,24 +1072,22 @@ static void turn_back_am(ir_node *node) /* rewire mem-proj */ if (get_irn_mode(node) == mode_T) { - mem_proj = NULL; + const ir_edge_t *edge; foreach_out_edge(node, edge) { ir_node *out = get_edge_src_irn(edge); - if(get_irn_mode(out) == mode_M) { - assert(mem_proj == NULL); - mem_proj = out; + if (get_irn_mode(out) == mode_M) { + set_Proj_pred(out, load); + set_Proj_proj(out, pn_ia32_Load_M); + break; } } - - if(mem_proj != NULL) { - set_Proj_pred(mem_proj, load); - set_Proj_proj(mem_proj, pn_ia32_Load_M); - } } set_ia32_op_type(node, ia32_Normal); if (sched_is_scheduled(node)) sched_add_before(node, load); + + return load_res; } static ir_node *flags_remat(ir_node *node, ir_node *after) @@ -1105,8 +1126,6 @@ static ir_node *flags_remat(ir_node *node, ir_node *after) /** * Called before the register allocator. - * Calculate a block schedule here. We need it for the x87 - * simulator and the emitter. */ static void ia32_before_ra(void *self) { ia32_code_gen_t *cg = self; @@ -1160,6 +1179,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { set_ia32_ls_mode(new_op, spillmode); set_ia32_frame_ent(new_op, ent); set_ia32_use_frame(new_op); + set_ia32_is_reload(new_op); DBG_OPT_RELOAD2LD(node, new_op); @@ -1230,6 +1250,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) { set_ia32_ls_mode(store, mode); set_ia32_frame_ent(store, ent); set_ia32_use_frame(store); + set_ia32_is_spill(store); SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node)); DBG_OPT_SPILL2ST(node, store); @@ -1254,6 +1275,7 @@ static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpo set_ia32_use_frame(push); set_ia32_op_type(push, ia32_AddrModeS); set_ia32_ls_mode(push, mode_Is); + set_ia32_is_spill(push); sched_add_before(schedpoint, push); return push; @@ -1272,6 +1294,7 @@ static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoi set_ia32_use_frame(pop); set_ia32_op_type(pop, ia32_AddrModeD); set_ia32_ls_mode(pop, mode_Is); + set_ia32_is_reload(pop); sched_add_before(schedpoint, pop); @@ -1425,7 +1448,11 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) if (is_ia32_need_stackent(node) || is_ia32_Load(node)) { const ir_mode *mode = get_ia32_ls_mode(node); const ia32_attr_t *attr = get_ia32_attr_const(node); - int align = get_mode_size_bytes(mode); + int align; + + if (is_ia32_is_reload(node)) { + mode = get_spill_mode_mode(mode); + } if(attr->data.need_64bit_stackent) { mode = mode_Ls; @@ -1433,6 +1460,7 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) if(attr->data.need_32bit_stackent) { mode = mode_Is; } + align = get_mode_size_bytes(mode); be_node_needs_frame_entity(env, node, mode, align); } else if (is_ia32_vfild(node) || is_ia32_xLoad(node) || is_ia32_vfld(node)) { @@ -1535,8 +1563,7 @@ static ir_node *ia32_get_pic_base(void *self) { get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block); cg->get_eip = get_eip; - add_irn_dep(get_eip, get_irg_frame(cg->irg)); - + be_dep_on_frame(get_eip); return get_eip; } @@ -1560,7 +1587,7 @@ static const arch_code_generator_if_t ia32_code_gen_if = { */ static void *ia32_cg_init(be_irg_t *birg) { ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env; - ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg)); + ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t); cg->impl = &ia32_code_gen_if; cg->irg = birg->irg; @@ -1644,7 +1671,7 @@ static ia32_isa_t ia32_isa_template = { &ia32_gp_regs[REG_ESP], /* stack pointer register */ &ia32_gp_regs[REG_EBP], /* base pointer register */ -1, /* stack direction */ - 4, /* power of two stack alignment, 2^4 == 16 */ + 2, /* power of two stack alignment, 2^2 == 4 */ NULL, /* main environment */ 7, /* costs for a spill instruction */ 5, /* costs for a reload instruction */ @@ -1722,7 +1749,7 @@ static arch_env_t *ia32_init(FILE *file_handle) { set_tarval_output_modes(); - isa = xmalloc(sizeof(*isa)); + isa = XMALLOC(ia32_isa_t); memcpy(isa, &ia32_isa_template, sizeof(*isa)); if(mode_fpcw == NULL) { @@ -1745,7 +1772,7 @@ static arch_env_t *ia32_init(FILE *file_handle) { ia32_build_8bit_reg_map_high(isa->regs_8bit_high); #ifndef NDEBUG - isa->name_obst = xmalloc(sizeof(*isa->name_obst)); + isa->name_obst = XMALLOC(struct obstack); obstack_init(isa->name_obst); #endif /* NDEBUG */ @@ -1867,7 +1894,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, call_flags.bits.store_args_sequential = 0; /* call_flags.bits.try_omit_fp not changed: can handle both settings */ call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */ - call_flags.bits.call_has_imm = 1; /* No call immediates, we handle this by ourselves */ + call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */ /* set parameter passing style */ be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks); @@ -2066,16 +2093,13 @@ static const be_execution_unit_t ***ia32_get_allowed_execution_units( if (is_ia32_irn(irn)) { ret = get_ia32_exec_units(irn); - } - else if (is_be_node(irn)) { - if (be_is_Call(irn) || be_is_Return(irn)) { + } else if (is_be_node(irn)) { + if (be_is_Return(irn)) { ret = _units_callret; - } - else if (be_is_Barrier(irn)) { + } else if (be_is_Barrier(irn)) { ret = _units_dummy; - } - else { - ret = _units_other; + } else { + ret = _units_other; } } else { @@ -2103,6 +2127,13 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) return NULL; } +static void ia32_mark_remat(const void *self, ir_node *node) { + (void) self; + if (is_ia32_irn(node)) { + set_ia32_is_remat(node); + } +} + /** * Allows or disallows the creation of Psi nodes for the given Phi nodes. * @return 1 if allowed, 0 otherwise @@ -2311,6 +2342,7 @@ static const lc_opt_enum_int_items_t transformer_items[] = { { "default", TRANSFORMER_DEFAULT }, #ifdef FIRM_GRGEN_BE { "pbqp", TRANSFORMER_PBQP }, + { "random", TRANSFORMER_RAND }, #endif { NULL, 0 } }; @@ -2342,6 +2374,7 @@ const arch_isa_if_t ia32_isa_if = { ia32_get_allowed_execution_units, ia32_get_machine, ia32_get_irg_list, + ia32_mark_remat, ia32_parse_asm_constraint, ia32_is_valid_clobber };