X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=5e5eb721fff75a3b26f425f3267802403c3a64db;hb=c1fdf770d4d000dd5cf22daead32369342c5f5d1;hp=7fc5d809f9531b8f7aeb7943d538f64eba43da38;hpb=2cc8c3b3bb545e020df93fa6bbc880974d66c20b;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 7fc5d809f..5e5eb721f 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -23,9 +23,7 @@ * @author Christian Wuerdig * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include "lc_opts.h" #include "lc_opts_enum.h" @@ -70,6 +68,7 @@ #include "../begnuas.h" #include "../bestate.h" #include "../beflags.h" +#include "../betranshlp.h" #include "bearch_ia32_t.h" @@ -131,7 +130,7 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, block = get_irg_start_block(cg->irg); res = func(NULL, cg->irg, block); - arch_set_irn_register(cg->arch_env, res, reg); + arch_set_irn_register(res, reg); *place = res; add_irn_dep(get_irg_end(cg->irg), res); @@ -182,9 +181,8 @@ ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) { */ static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) { - const arch_register_req_t *req; + const arch_register_req_t *req = arch_get_register_req(irn, pos); - req = arch_get_register_req(cg->arch_env, irn, pos); assert(req != NULL && "Missing register requirements"); if (req->cls == &ia32_reg_classes[CLASS_ia32_gp]) return ia32_new_NoReg_gp(cg); @@ -279,10 +277,8 @@ static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg) static const arch_register_t *ia32_get_irn_reg(const ir_node *irn) { int pos = 0; - const arch_register_t *reg = NULL; if (is_Proj(irn)) { - if (get_irn_mode(irn) == mode_X) { return NULL; } @@ -292,19 +288,16 @@ static const arch_register_t *ia32_get_irn_reg(const ir_node *irn) } if (is_ia32_irn(irn)) { - const arch_register_t **slots; - slots = get_ia32_slots(irn); + const arch_register_t **slots = get_ia32_slots(irn); assert(pos < get_ia32_n_res(irn)); - reg = slots[pos]; + return slots[pos]; } else { - reg = ia32_get_firm_reg(irn, cur_reg_set); + return ia32_get_firm_reg(irn, cur_reg_set); } - - return reg; } static arch_irn_class_t ia32_classify(const ir_node *irn) { - arch_irn_class_t classification = arch_irn_class_normal; + arch_irn_class_t classification = 0; irn = skip_Proj_const(irn); @@ -312,13 +305,7 @@ static arch_irn_class_t ia32_classify(const ir_node *irn) { classification |= arch_irn_class_branch; if (! is_ia32_irn(irn)) - return classification & ~arch_irn_class_normal; - - if (is_ia32_Ld(irn)) - classification |= arch_irn_class_load; - - if (is_ia32_St(irn)) - classification |= arch_irn_class_store; + return classification; if (is_ia32_is_reload(irn)) classification |= arch_irn_class_reload; @@ -392,6 +379,9 @@ static void ia32_set_frame_offset(ir_node *irn, int bias) static int ia32_get_sp_bias(const ir_node *node) { + if (is_ia32_Call(node)) + return -(int)get_ia32_call_attr_const(node)->pop; + if (is_ia32_Push(node)) return 4; @@ -449,7 +439,7 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M); /* the push must have SP out register */ - arch_set_irn_register(arch_env, curr_sp, arch_env->sp); + arch_set_irn_register(curr_sp, arch_env->sp); set_ia32_flags(push, arch_irn_flags_ignore); /* this modifies the stack bias, because we pushed 32bit */ @@ -458,13 +448,13 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap /* move esp to ebp */ curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp); be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp); - arch_set_irn_register(arch_env, curr_bp, arch_env->bp); + arch_set_irn_register(curr_bp, arch_env->bp); be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore); /* beware: the copy must be done before any other sp use */ curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp)); be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp); - arch_set_irn_register(arch_env, curr_sp, arch_env->sp); + arch_set_irn_register(curr_sp, arch_env->sp); be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore); be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp); @@ -517,7 +507,7 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ /* copy ebp to esp */ curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp); - arch_set_irn_register(arch_env, curr_sp, arch_env->sp); + arch_set_irn_register(curr_sp, arch_env->sp); be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore); /* pop ebp */ @@ -528,8 +518,8 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M); } - arch_set_irn_register(arch_env, curr_sp, arch_env->sp); - arch_set_irn_register(arch_env, curr_bp, arch_env->bp); + arch_set_irn_register(curr_sp, arch_env->sp); + arch_set_irn_register(curr_bp, arch_env->bp); } be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp); @@ -828,7 +818,9 @@ static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) return 0; case ia32_am_unary: - return i == n_ia32_unary_op; + if (i != n_ia32_unary_op) + return 0; + break; case ia32_am_binary: switch (i) { @@ -843,20 +835,27 @@ static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) req = get_ia32_in_req(irn, n_ia32_binary_left); if (req->type & arch_register_req_type_limited) return 0; - - return 1; + break; } case n_ia32_binary_right: - return 1; + break; default: return 0; } + break; default: panic("Unknown AM type"); } + + /* HACK: must not already use "real" memory. + * This can happen for Call and Div */ + if (!is_NoMem(get_irn_n(irn, n_ia32_mem))) + return 0; + + return 1; } static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill, @@ -885,6 +884,8 @@ static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill, i = n_ia32_binary_right; } + assert(is_NoMem(get_irn_n(irn, n_ia32_mem))); + set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn))); set_irn_n(irn, n_ia32_mem, spill); set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i)); @@ -1185,8 +1186,8 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { } /* copy the register from the old node to the new Load */ - reg = arch_get_irn_register(cg->arch_env, node); - arch_set_irn_register(cg->arch_env, new_op, reg); + reg = arch_get_irn_register(node); + arch_set_irn_register(new_op, reg); SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node)); @@ -1295,7 +1296,8 @@ static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoi return pop; } -static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) { +static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos) +{ ir_graph *irg = get_irn_irg(node); dbg_info *dbg = get_irn_dbg_info(node); ir_node *block = get_nodes_block(node); @@ -1304,7 +1306,7 @@ static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, ir_node *sp; sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos); - arch_set_irn_register(cg->arch_env, sp, spreg); + arch_set_irn_register(sp, spreg); return sp; } @@ -1344,12 +1346,12 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) { assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit"); push = create_push(cg, node, node, sp, mem, inent); - sp = create_spproj(cg, node, push, pn_ia32_Push_stack); + sp = create_spproj(node, push, pn_ia32_Push_stack); if(entsize == 8) { /* add another push after the first one */ push = create_push(cg, node, node, sp, mem, inent); add_ia32_am_offs_int(push, 4); - sp = create_spproj(cg, node, push, pn_ia32_Push_stack); + sp = create_spproj(node, push, pn_ia32_Push_stack); } set_irn_n(node, i, new_Bad()); @@ -1370,13 +1372,13 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) { assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit"); pop = create_pop(cg, node, node, sp, outent); - sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack); + sp = create_spproj(node, pop, pn_ia32_Pop_stack); if(entsize == 8) { add_ia32_am_offs_int(pop, 4); /* add another pop after the first one */ pop = create_pop(cg, node, node, sp, outent); - sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack); + sp = create_spproj(node, pop, pn_ia32_Pop_stack); } pops[i] = pop; @@ -1431,52 +1433,73 @@ static void ia32_after_ra_walker(ir_node *block, void *env) { */ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) { - be_fec_env_t *env = data; + be_fec_env_t *env = data; + const ir_mode *mode; + int align; if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) { - const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node)); - int align = get_mode_size_bytes(mode); - be_node_needs_frame_entity(env, node, mode, align); - } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL - && is_ia32_use_frame(node)) { - if (is_ia32_need_stackent(node) || is_ia32_Load(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - const ia32_attr_t *attr = get_ia32_attr_const(node); - int align; - - if (is_ia32_is_reload(node)) { - mode = get_spill_mode_mode(mode); + mode = get_spill_mode_mode(get_irn_mode(node)); + align = get_mode_size_bytes(mode); + } else if (is_ia32_irn(node) && + get_ia32_frame_ent(node) == NULL && + is_ia32_use_frame(node)) { + if (is_ia32_need_stackent(node)) + goto need_stackent; + + switch (get_ia32_irn_opcode(node)) { +need_stackent: + case iro_ia32_Load: { + const ia32_attr_t *attr = get_ia32_attr_const(node); + + if (attr->data.need_32bit_stackent) { + mode = mode_Is; + } else if (attr->data.need_64bit_stackent) { + mode = mode_Ls; + } else { + mode = get_ia32_ls_mode(node); + if (is_ia32_is_reload(node)) + mode = get_spill_mode_mode(mode); + } + align = get_mode_size_bytes(mode); + break; } - if(attr->data.need_64bit_stackent) { - mode = mode_Ls; + case iro_ia32_vfild: + case iro_ia32_vfld: + case iro_ia32_xLoad: { + mode = get_ia32_ls_mode(node); + align = 4; + break; } - if(attr->data.need_32bit_stackent) { - mode = mode_Is; + + case iro_ia32_FldCW: { + /* although 2 byte would be enough 4 byte performs best */ + mode = mode_Iu; + align = 4; + break; } - align = get_mode_size_bytes(mode); - be_node_needs_frame_entity(env, node, mode, align); - } else if (is_ia32_vfild(node) || is_ia32_xLoad(node) - || is_ia32_vfld(node)) { - const ir_mode *mode = get_ia32_ls_mode(node); - int align = 4; - be_node_needs_frame_entity(env, node, mode, align); - } else if(is_ia32_FldCW(node)) { - /* although 2 byte would be enough 4 byte performs best */ - const ir_mode *mode = mode_Iu; - int align = 4; - be_node_needs_frame_entity(env, node, mode, align); - } else { + + default: #ifndef NDEBUG - assert(is_ia32_St(node) || - is_ia32_xStoreSimple(node) || - is_ia32_vfst(node) || - is_ia32_vfist(node) || - is_ia32_vfisttp(node) || - is_ia32_FnstCW(node)); + panic("unexpected frame user while collection frame entity nodes"); + + case iro_ia32_FnstCW: + case iro_ia32_Store8Bit: + case iro_ia32_Store: + case iro_ia32_fst: + case iro_ia32_fstp: + case iro_ia32_vfist: + case iro_ia32_vfisttp: + case iro_ia32_vfst: + case iro_ia32_xStore: + case iro_ia32_xStoreSimple: #endif + return; } + } else { + return; } + be_node_needs_frame_entity(env, node, mode, align); } /** @@ -1509,7 +1532,7 @@ static void ia32_finish(void *self) { /* we might have to rewrite x87 virtual registers */ if (cg->do_x87_sim) { - x87_simulate_graph(cg->arch_env, cg->birg); + x87_simulate_graph(cg->birg); } /* do peephole optimisations */ @@ -1557,8 +1580,7 @@ static ir_node *ia32_get_pic_base(void *self) { get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block); cg->get_eip = get_eip; - add_irn_dep(get_eip, get_irg_frame(cg->irg)); - + be_dep_on_frame(get_eip); return get_eip; } @@ -1588,7 +1610,6 @@ static void *ia32_cg_init(be_irg_t *birg) { cg->irg = birg->irg; cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024); cg->isa = isa; - cg->arch_env = birg->main_env->arch_env; cg->birg = birg; cg->blk_sched = NULL; cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; @@ -1889,7 +1910,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, call_flags.bits.store_args_sequential = 0; /* call_flags.bits.try_omit_fp not changed: can handle both settings */ call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */ - call_flags.bits.call_has_imm = 1; /* No call immediates, we handle this by ourselves */ + call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */ /* set parameter passing style */ be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks); @@ -2088,16 +2109,13 @@ static const be_execution_unit_t ***ia32_get_allowed_execution_units( if (is_ia32_irn(irn)) { ret = get_ia32_exec_units(irn); - } - else if (is_be_node(irn)) { - if (be_is_Call(irn) || be_is_Return(irn)) { + } else if (is_be_node(irn)) { + if (be_is_Return(irn)) { ret = _units_callret; - } - else if (be_is_Barrier(irn)) { + } else if (be_is_Barrier(irn)) { ret = _units_dummy; - } - else { - ret = _units_other; + } else { + ret = _units_other; } } else {