X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=3d6973a2e0ede7d726d0008af84061459cd2a90e;hb=ab2e5fb8cd8e614caf0788d776250a3776b4e662;hp=f1e77aea31168f6f1e3684059cd79e5e444870e1;hpb=4fa8da0e905f6bace754423d74462232bb338765;p=libfirm

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index f1e77aea3..3d6973a2e 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -63,7 +63,6 @@
 #include "../be_dbgout.h"
 #include "../beblocksched.h"
 #include "../bemachine.h"
-#include "../beilpsched.h"
 #include "../bespillslots.h"
 #include "../bemodule.h"
 #include "../begnuas.h"
@@ -81,7 +80,6 @@
 #include "ia32_common_transform.h"
 #include "ia32_transform.h"
 #include "ia32_emitter.h"
-#include "ia32_map_regs.h"
 #include "ia32_optimize.h"
 #include "ia32_x87.h"
 #include "ia32_dbg_stat.h"
@@ -98,8 +96,7 @@ transformer_t be_transformer = TRANSFORMER_DEFAULT;
 
 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
 
-ir_mode         *mode_fpcw       = NULL;
-ia32_code_gen_t *ia32_current_cg = NULL;
+ir_mode         *ia32_mode_fpcw       = NULL;
 
 /** The current omit-fp state */
 static unsigned ia32_curr_fp_ommitted  = 0;
@@ -127,7 +124,7 @@ typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
 /**
  * Used to create per-graph unique pseudo nodes.
  */
-static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
+static inline ir_node *create_const(ir_graph *irg, ir_node **place,
                                     create_const_node_func func,
                                     const arch_register_t* reg)
 {
@@ -136,7 +133,7 @@ static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
 	if (*place != NULL)
 		return *place;
 
-	block = get_irg_start_block(cg->irg);
+	block = get_irg_start_block(irg);
 	res = func(NULL, block);
 	arch_set_irn_register(res, reg);
 	*place = res;
@@ -145,61 +142,57 @@ static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
 }
 
 /* Creates the unique per irg GP NoReg node. */
-ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
+ir_node *ia32_new_NoReg_gp(ir_graph *irg)
 {
-	return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
-	                    &ia32_gp_regs[REG_GP_NOREG]);
+	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+	return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
+	                    &ia32_registers[REG_GP_NOREG]);
 }
 
-ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
+ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
 {
-	return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
-	                    &ia32_vfp_regs[REG_VFP_NOREG]);
+	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+	return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
+	                    &ia32_registers[REG_VFP_NOREG]);
 }
 
-ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
+ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
 {
-	return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
-	                    &ia32_xmm_regs[REG_XMM_NOREG]);
+	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+	return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
+	                    &ia32_registers[REG_XMM_NOREG]);
 }
 
-ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
+ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
 {
-	return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
-                        &ia32_fp_cw_regs[REG_FPCW]);
+	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+	return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
+                        &ia32_registers[REG_FPCW]);
 }
 
 
 /**
  * Returns the admissible noreg register node for input register pos of node irn.
  */
-static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
+static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
 {
+	ir_graph                  *irg = get_irn_irg(irn);
 	const arch_register_req_t *req = arch_get_register_req(irn, pos);
 
 	assert(req != NULL && "Missing register requirements");
 	if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
-		return ia32_new_NoReg_gp(cg);
+		return ia32_new_NoReg_gp(irg);
 
 	if (ia32_cg_config.use_sse2) {
-		return ia32_new_NoReg_xmm(cg);
+		return ia32_new_NoReg_xmm(irg);
 	} else {
-		return ia32_new_NoReg_vfp(cg);
+		return ia32_new_NoReg_vfp(irg);
 	}
 }
 
-
-static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
-		const ir_node *node, int pos)
-{
-	(void) node;
-	(void) pos;
-	return arch_no_register_req;
-}
-
 static arch_irn_class_t ia32_classify(const ir_node *irn)
 {
-	arch_irn_class_t classification = 0;
+	arch_irn_class_t classification = arch_irn_class_none;
 
 	assert(is_ia32_irn(irn));
 
@@ -265,6 +258,11 @@ static int ia32_get_sp_bias(const ir_node *node)
 	if (is_ia32_Pop(node) || is_ia32_PopMem(node))
 		return -4;
 
+	if (is_ia32_Leave(node) || (be_is_Copy(node)
+	    && arch_get_irn_register(node) == &ia32_registers[REG_ESP])) {
+		return SP_BIAS_RESET;
+	}
+
 	return 0;
 }
 
@@ -282,16 +280,16 @@ static int ia32_get_sp_bias(const ir_node *node)
  */
 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
 {
-	ia32_abi_env_t   *env      = self;
-	ia32_code_gen_t  *cg       = ia32_current_cg;
-	const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
+	ia32_abi_env_t   *env      = (ia32_abi_env_t*)self;
+	ir_graph         *irg      = env->irg;
+	const arch_env_t *arch_env = be_get_irg_arch_env(irg);
 
 	ia32_curr_fp_ommitted = env->flags.try_omit_fp;
 	if (! env->flags.try_omit_fp) {
 		ir_node  *bl      = get_irg_start_block(env->irg);
 		ir_node  *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
 		ir_node  *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
-		ir_node  *noreg   = ia32_new_NoReg_gp(cg);
+		ir_node  *noreg   = ia32_new_NoReg_gp(irg);
 		ir_node  *push;
 
 		/* mark bp register as ignore */
@@ -300,8 +298,10 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
 
 		/* push ebp */
 		push    = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
+		arch_irn_add_flags(push, arch_irn_flags_prolog);
 		curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
 		*mem    = new_r_Proj(push, mode_M, pn_ia32_Push_M);
+		set_irn_pinned(push, op_pin_state_pinned);
 
 		/* the push must have SP out register */
 		arch_set_irn_register(curr_sp, arch_env->sp);
@@ -311,11 +311,14 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
 
 		/* move esp to ebp */
 		curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
+		arch_irn_add_flags(curr_bp, arch_irn_flags_prolog);
 		be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
 		                             arch_register_req_type_ignore);
+		set_irn_pinned(curr_bp, op_pin_state_pinned);
 
 		/* beware: the copy must be done before any other sp use */
 		curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
+		arch_irn_add_flags(curr_sp, arch_irn_flags_prolog);
 		be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
 				                     arch_register_req_type_produces_sp);
 
@@ -340,7 +343,7 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
  */
 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
 {
-	ia32_abi_env_t   *env      = self;
+	ia32_abi_env_t   *env      = (ia32_abi_env_t*)self;
 	const arch_env_t *arch_env = be_get_irg_arch_env(env->irg);
 	ir_node          *curr_sp  = be_abi_reg_map_get(reg_map, arch_env->sp);
 	ir_node          *curr_bp  = be_abi_reg_map_get(reg_map, arch_env->bp);
@@ -348,6 +351,8 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
 	if (env->flags.try_omit_fp) {
 		/* simply remove the stack frame here */
 		curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
+		arch_irn_add_flags(curr_sp, arch_irn_flags_epilog);
+		set_irn_pinned(curr_sp, op_pin_state_pinned);
 	} else {
 		ir_mode *mode_bp = arch_env->bp->reg_class->mode;
 
@@ -358,23 +363,25 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
 			leave   = new_bd_ia32_Leave(NULL, bl, curr_bp);
 			curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
 			curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
+			arch_irn_add_flags(leave, arch_irn_flags_epilog);
+			set_irn_pinned(leave, op_pin_state_pinned);
 		} else {
 			ir_node *pop;
 
-			/* the old SP is not needed anymore (kill the proj) */
-			assert(is_Proj(curr_sp));
-			kill_node(curr_sp);
-
 			/* copy ebp to esp */
 			curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
 			arch_set_irn_register(curr_sp, arch_env->sp);
 			be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
 				                         arch_register_req_type_ignore);
+			arch_irn_add_flags(curr_sp, arch_irn_flags_epilog);
+			set_irn_pinned(curr_sp, op_pin_state_pinned);
 
 			/* pop ebp */
 			pop     = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
 			curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
 			curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
+			arch_irn_add_flags(pop, arch_irn_flags_epilog);
+			set_irn_pinned(pop, op_pin_state_pinned);
 
 			*mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
 		}
@@ -446,7 +453,7 @@ static void ia32_build_between_type(void)
  */
 static ir_type *ia32_abi_get_between_type(void *self)
 {
-	ia32_abi_env_t *env = self;
+	ia32_abi_env_t *env = (ia32_abi_env_t*)self;
 
 	ia32_build_between_type();
 	return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
@@ -508,8 +515,8 @@ static int ia32_get_op_estimated_cost(const ir_node *irn)
 			cycles.
 		*/
 		if (is_ia32_use_frame(irn) || (
-		    	is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
-		    	is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
+		    is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
+		    is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
 		    )) {
 			cost += 5;
 		} else {
@@ -564,7 +571,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
 	mode     = get_irn_mode(irn);
 	irn_mode = get_irn_mode(irn);
 	noreg    = get_irn_n(irn, 0);
-	nomem    = new_NoMem();
+	nomem    = new_r_NoMem(irg);
 	dbg      = get_irn_dbg_info(irn);
 
 	/* initialize structure */
@@ -716,7 +723,7 @@ static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
 					/* we can't swap left/right for limited registers
 					 * (As this (currently) breaks constraint handling copies)
 					 */
-					req = get_ia32_in_req(irn, n_ia32_binary_left);
+					req = arch_get_in_register_req(irn, n_ia32_binary_left);
 					if (req->type & arch_register_req_type_limited)
 						return 0;
 					break;
@@ -772,7 +779,7 @@ static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
 
 	set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
 	set_irn_n(irn, n_ia32_mem,  spill);
-	set_irn_n(irn, i,           ia32_get_admissible_noreg(ia32_current_cg, irn, i));
+	set_irn_n(irn, i,           ia32_get_admissible_noreg(irn, i));
 	set_ia32_is_reload(irn);
 }
 
@@ -786,7 +793,6 @@ static const be_abi_callbacks_t ia32_abi_callbacks = {
 
 /* register allocator interface */
 static const arch_irn_ops_t ia32_irn_ops = {
-	get_ia32_in_req,
 	ia32_classify,
 	ia32_get_frame_entity,
 	ia32_set_frame_offset,
@@ -797,43 +803,21 @@ static const arch_irn_ops_t ia32_irn_ops = {
 	ia32_perform_memory_operand,
 };
 
-/* special register allocator interface for SwitchJmp
-   as it possibly has a WIDE range of Proj numbers.
-   We don't want to allocate output for register constraints for
-   all these. */
-static const arch_irn_ops_t ia32_SwitchJmp_irn_ops = {
-	/* Note: we also use SwitchJmp_out_req for the inputs too:
-	   This is because the bearch API has a conceptual problem at the moment.
-	   Querying for negative proj numbers which can happen for switchs
-	   isn't possible and will result in inputs getting queried */
-	get_ia32_SwitchJmp_out_req,
-	ia32_classify,
-	ia32_get_frame_entity,
-	ia32_set_frame_offset,
-	ia32_get_sp_bias,
-	ia32_get_inverse,
-	ia32_get_op_estimated_cost,
-	ia32_possible_memory_operand,
-	ia32_perform_memory_operand,
-};
-
-
 static ir_entity *mcount = NULL;
+static int gprof = 0;
 
-#define ID(s) new_id_from_chars(s, sizeof(s) - 1)
-
-static void ia32_before_abi(void *self)
+static void ia32_before_abi(ir_graph *irg)
 {
-	ia32_code_gen_t *cg = self;
-	if (cg->gprof) {
+	if (gprof) {
 		if (mcount == NULL) {
 			ir_type *tp = new_type_method(0, 0);
-			mcount = new_entity(get_glob_type(), ID("mcount"), tp);
+			ident   *id = new_id_from_str("mcount");
+			mcount = new_entity(get_glob_type(), id, tp);
 			/* FIXME: enter the right ld_ident here */
 			set_entity_ld_ident(mcount, get_entity_ident(mcount));
 			set_entity_visibility(mcount, ir_visibility_external);
 		}
-		instrument_initcall(cg->irg, mcount);
+		instrument_initcall(irg, mcount);
 	}
 }
 
@@ -841,49 +825,50 @@ static void ia32_before_abi(void *self)
  * Transforms the standard firm graph into
  * an ia32 firm graph
  */
-static void ia32_prepare_graph(void *self)
+static void ia32_prepare_graph(ir_graph *irg)
 {
-	ia32_code_gen_t *cg = self;
+	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
 
 #ifdef FIRM_GRGEN_BE
 	switch (be_transformer) {
 	case TRANSFORMER_DEFAULT:
 		/* transform remaining nodes into assembler instructions */
-		ia32_transform_graph(cg);
+		ia32_transform_graph(irg);
 		break;
 
 	case TRANSFORMER_PBQP:
 	case TRANSFORMER_RAND:
 		/* transform nodes into assembler instructions by PBQP magic */
-		ia32_transform_graph_by_pbqp(cg);
+		ia32_transform_graph_by_pbqp(irg);
 		break;
 
 	default:
 		panic("invalid transformer");
 	}
 #else
-	ia32_transform_graph(cg);
+	ia32_transform_graph(irg);
 #endif
 
 	/* do local optimizations (mainly CSE) */
-	optimize_graph_df(cg->irg);
+	optimize_graph_df(irg);
 
-	if (cg->dump)
-		dump_ir_graph(cg->irg, "transformed");
+	if (irg_data->dump)
+		dump_ir_graph(irg, "transformed");
 
 	/* optimize address mode */
-	ia32_optimize_graph(cg);
+	ia32_optimize_graph(irg);
 
 	/* do code placement, to optimize the position of constants */
-	place_code(cg->irg);
+	place_code(irg);
 
-	if (cg->dump)
-		dump_ir_graph(cg->irg, "place");
+	if (irg_data->dump)
+		dump_ir_graph(irg, "place");
 }
 
-ir_node *turn_back_am(ir_node *node)
+ir_node *ia32_turn_back_am(ir_node *node)
 {
 	dbg_info *dbgi  = get_irn_dbg_info(node);
+	ir_graph *irg   = get_irn_irg(node);
 	ir_node  *block = get_nodes_block(node);
 	ir_node  *base  = get_irn_n(node, n_ia32_base);
 	ir_node  *index = get_irn_n(node, n_ia32_index);
@@ -896,7 +881,7 @@ ir_node *turn_back_am(ir_node *node)
 	ia32_copy_am_attrs(load, node);
 	if (is_ia32_is_reload(node))
 		set_ia32_is_reload(load);
-	set_irn_n(node, n_ia32_mem, new_NoMem());
+	set_irn_n(node, n_ia32_mem, new_r_NoMem(irg));
 
 	switch (get_ia32_am_support(node)) {
 		case ia32_am_unary:
@@ -914,7 +899,7 @@ ir_node *turn_back_am(ir_node *node)
 		default:
 			panic("Unknown AM type");
 	}
-	noreg = ia32_new_NoReg_gp(ia32_current_cg);
+	noreg = ia32_new_NoReg_gp(current_ir_graph);
 	set_irn_n(node, n_ia32_base,  noreg);
 	set_irn_n(node, n_ia32_index, noreg);
 	set_ia32_am_offs_int(node, 0);
@@ -958,7 +943,7 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
 	type = get_ia32_op_type(node);
 	switch (type) {
 		case ia32_AddrModeS:
-			turn_back_am(node);
+			ia32_turn_back_am(node);
 			break;
 
 		case ia32_AddrModeD:
@@ -979,25 +964,23 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
 /**
  * Called before the register allocator.
  */
-static void ia32_before_ra(void *self)
+static void ia32_before_ra(ir_graph *irg)
 {
-	ia32_code_gen_t *cg = self;
-
 	/* setup fpu rounding modes */
-	ia32_setup_fpu_mode(cg);
+	ia32_setup_fpu_mode(irg);
 
 	/* fixup flags */
-	be_sched_fix_flags(cg->irg, &ia32_reg_classes[CLASS_ia32_flags],
+	be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
 	                   &flags_remat, NULL);
 
-	be_add_missing_keeps(cg->irg);
+	be_add_missing_keeps(irg);
 }
 
 
 /**
  * Transforms a be_Reload into a ia32 Load.
  */
-static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
+static void transform_to_Load(ir_node *node)
 {
 	ir_graph *irg        = get_irn_irg(node);
 	dbg_info *dbg        = get_irn_dbg_info(node);
@@ -1005,7 +988,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
 	ir_entity *ent       = be_get_frame_entity(node);
 	ir_mode *mode        = get_irn_mode(node);
 	ir_mode *spillmode   = get_spill_mode(node);
-	ir_node *noreg       = ia32_new_NoReg_gp(cg);
+	ir_node *noreg       = ia32_new_NoReg_gp(irg);
 	ir_node *sched_point = NULL;
 	ir_node *ptr         = get_irg_frame(irg);
 	ir_node *mem         = get_irn_n(node, be_pos_Reload_mem);
@@ -1056,7 +1039,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
 /**
  * Transforms a be_Spill node into a ia32 Store.
  */
-static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
+static void transform_to_Store(ir_node *node)
 {
 	ir_graph *irg  = get_irn_irg(node);
 	dbg_info *dbg  = get_irn_dbg_info(node);
@@ -1064,8 +1047,8 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
 	ir_entity *ent = be_get_frame_entity(node);
 	const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
 	ir_mode *mode  = get_spill_mode(spillval);
-	ir_node *noreg = ia32_new_NoReg_gp(cg);
-	ir_node *nomem = new_NoMem();
+	ir_node *noreg = ia32_new_NoReg_gp(irg);
+	ir_node *nomem = new_r_NoMem(irg);
 	ir_node *ptr   = get_irg_frame(irg);
 	ir_node *val   = get_irn_n(node, be_pos_Spill_val);
 	ir_node *store;
@@ -1105,12 +1088,12 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
 	exchange(node, store);
 }
 
-static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
+static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
 {
 	dbg_info *dbg = get_irn_dbg_info(node);
 	ir_node *block = get_nodes_block(node);
-	ir_node *noreg = ia32_new_NoReg_gp(cg);
 	ir_graph *irg = get_irn_irg(node);
+	ir_node *noreg = ia32_new_NoReg_gp(irg);
 	ir_node *frame = get_irg_frame(irg);
 
 	ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
@@ -1125,15 +1108,15 @@ static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpo
 	return push;
 }
 
-static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
+static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
 {
-	dbg_info *dbg = get_irn_dbg_info(node);
-	ir_node *block = get_nodes_block(node);
-	ir_node *noreg = ia32_new_NoReg_gp(cg);
-	ir_graph *irg  = get_irn_irg(node);
-	ir_node *frame = get_irg_frame(irg);
+	dbg_info *dbg   = get_irn_dbg_info(node);
+	ir_node  *block = get_nodes_block(node);
+	ir_graph *irg   = get_irn_irg(node);
+	ir_node  *noreg = ia32_new_NoReg_gp(irg);
+	ir_node  *frame = get_irg_frame(irg);
 
-	ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
+	ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_r_NoMem(irg), sp);
 
 	set_ia32_frame_ent(pop, ent);
 	set_ia32_use_frame(pop);
@@ -1150,7 +1133,7 @@ static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
 {
 	dbg_info *dbg = get_irn_dbg_info(node);
 	ir_mode *spmode = mode_Iu;
-	const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
+	const arch_register_t *spreg = &ia32_registers[REG_ESP];
 	ir_node *sp;
 
 	sp = new_rd_Proj(dbg, pred, spmode, pos);
@@ -1164,10 +1147,11 @@ static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
  * push/pop into/from memory cascades. This is possible without using
  * any registers.
  */
-static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
+static void transform_MemPerm(ir_node *node)
 {
 	ir_node         *block = get_nodes_block(node);
-	ir_node         *sp    = be_abi_get_ignore_irn(be_get_irg_abi(cg->irg), &ia32_gp_regs[REG_ESP]);
+	ir_graph        *irg   = get_irn_irg(node);
+	ir_node         *sp    = be_abi_get_ignore_irn(be_get_irg_abi(irg), &ia32_registers[REG_ESP]);
 	int              arity = be_get_MemPerm_entity_arity(node);
 	ir_node        **pops  = ALLOCAN(ir_node*, arity);
 	ir_node         *in[1];
@@ -1191,16 +1175,16 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 			entsize = entsize2;
 		assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
 
-		push = create_push(cg, node, node, sp, mem, inent);
+		push = create_push(node, node, sp, mem, inent);
 		sp = create_spproj(node, push, pn_ia32_Push_stack);
 		if (entsize == 8) {
 			/* add another push after the first one */
-			push = create_push(cg, node, node, sp, mem, inent);
+			push = create_push(node, node, sp, mem, inent);
 			add_ia32_am_offs_int(push, 4);
 			sp = create_spproj(node, push, pn_ia32_Push_stack);
 		}
 
-		set_irn_n(node, i, new_Bad());
+		set_irn_n(node, i, new_r_Bad(irg));
 	}
 
 	/* create pops */
@@ -1217,13 +1201,13 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 			entsize = entsize2;
 		assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
 
-		pop = create_pop(cg, node, node, sp, outent);
+		pop = create_pop(node, node, sp, outent);
 		sp = create_spproj(node, pop, pn_ia32_Pop_stack);
 		if (entsize == 8) {
 			add_ia32_am_offs_int(pop, 4);
 
 			/* add another pop after the first one */
-			pop = create_pop(cg, node, node, sp, outent);
+			pop = create_pop(node, node, sp, outent);
 			sp = create_spproj(node, pop, pn_ia32_Pop_stack);
 		}
 
@@ -1248,7 +1232,7 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 	/* remove memperm */
 	arity = get_irn_arity(node);
 	for (i = 0; i < arity; ++i) {
-		set_irn_n(node, i, new_Bad());
+		set_irn_n(node, i, new_r_Bad(irg));
 	}
 	sched_remove(node);
 }
@@ -1259,18 +1243,18 @@ static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
 static void ia32_after_ra_walker(ir_node *block, void *env)
 {
 	ir_node *node, *prev;
-	ia32_code_gen_t *cg = env;
+	(void) env;
 
 	/* beware: the schedule is changed here */
 	for (node = sched_last(block); !sched_is_begin(node); node = prev) {
 		prev = sched_prev(node);
 
 		if (be_is_Reload(node)) {
-			transform_to_Load(cg, node);
+			transform_to_Load(node);
 		} else if (be_is_Spill(node)) {
-			transform_to_Store(cg, node);
+			transform_to_Store(node);
 		} else if (be_is_MemPerm(node)) {
-			transform_MemPerm(cg, node);
+			transform_MemPerm(node);
 		}
 	}
 }
@@ -1280,7 +1264,7 @@ static void ia32_after_ra_walker(ir_node *block, void *env)
  */
 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
 {
-	be_fec_env_t  *env = data;
+	be_fec_env_t  *env = (be_fec_env_t*)data;
 	const ir_mode *mode;
 	int            align;
 
@@ -1353,18 +1337,18 @@ need_stackent:
  * We transform Spill and Reload here. This needs to be done before
  * stack biasing otherwise we would miss the corrected offset for these nodes.
  */
-static void ia32_after_ra(void *self)
+static void ia32_after_ra(ir_graph *irg)
 {
-	ia32_code_gen_t *cg = self;
-	ir_graph *irg = cg->irg;
-	be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->irg);
+	be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
+	bool               at_begin     = stack_layout->sp_relative ? true : false;
+	be_fec_env_t      *fec_env      = be_new_frame_entity_coalescer(irg);
 
 	/* create and coalesce frame entities */
 	irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
-	be_assign_entities(fec_env, ia32_set_frame_entity);
+	be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
 	be_free_frame_entity_coalescer(fec_env);
 
-	irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
+	irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
 }
 
 /**
@@ -1372,118 +1356,72 @@ static void ia32_after_ra(void *self)
  * virtual with real x87 instructions, creating a block schedule and peephole
  * optimisations.
  */
-static void ia32_finish(void *self)
+static void ia32_finish(ir_graph *irg)
 {
-	ia32_code_gen_t *cg = self;
-	ir_graph        *irg = cg->irg;
+	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
 
-	ia32_finish_irg(irg, cg);
+	ia32_finish_irg(irg);
 
 	/* we might have to rewrite x87 virtual registers */
-	if (cg->do_x87_sim) {
-		x87_simulate_graph(cg->irg);
+	if (irg_data->do_x87_sim) {
+		ia32_x87_simulate_graph(irg);
 	}
 
 	/* do peephole optimisations */
-	ia32_peephole_optimization(cg);
+	ia32_peephole_optimization(irg);
 
 	/* create block schedule, this also removes empty blocks which might
 	 * produce critical edges */
-	cg->blk_sched = be_create_block_schedule(irg);
+	irg_data->blk_sched = be_create_block_schedule(irg);
 }
 
 /**
  * Emits the code, closes the output file and frees
  * the code generator interface.
  */
-static void ia32_codegen(void *self)
+static void ia32_emit(ir_graph *irg)
 {
-	ia32_code_gen_t *cg = self;
-	ir_graph        *irg = cg->irg;
-
 	if (ia32_cg_config.emit_machcode) {
-		ia32_gen_binary_routine(cg, irg);
+		ia32_gen_binary_routine(irg);
 	} else {
-		ia32_gen_routine(cg, irg);
+		ia32_gen_routine(irg);
 	}
-
-	/* remove it from the isa */
-	cg->isa->cg = NULL;
-
-	assert(ia32_current_cg == cg);
-	ia32_current_cg = NULL;
-
-	/* de-allocate code generator */
-	free(cg);
 }
 
 /**
  * Returns the node representing the PIC base.
  */
-static ir_node *ia32_get_pic_base(void *self)
+static ir_node *ia32_get_pic_base(ir_graph *irg)
 {
+	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
 	ir_node         *block;
-	ia32_code_gen_t *cg      = self;
-	ir_node         *get_eip = cg->get_eip;
+	ir_node         *get_eip = irg_data->get_eip;
 	if (get_eip != NULL)
 		return get_eip;
 
-	block       = get_irg_start_block(cg->irg);
-	get_eip     = new_bd_ia32_GetEIP(NULL, block);
-	cg->get_eip = get_eip;
+	block             = get_irg_start_block(irg);
+	get_eip           = new_bd_ia32_GetEIP(NULL, block);
+	irg_data->get_eip = get_eip;
 
-	be_dep_on_frame(get_eip);
 	return get_eip;
 }
 
-static void *ia32_cg_init(ir_graph *irg);
-
-static const arch_code_generator_if_t ia32_code_gen_if = {
-	ia32_cg_init,
-	ia32_get_pic_base,   /* return node used as base in pic code addresses */
-	ia32_before_abi,     /* before abi introduce hook */
-	ia32_prepare_graph,
-	NULL,                /* spill */
-	ia32_before_ra,      /* before register allocation hook */
-	ia32_after_ra,       /* after register allocation hook */
-	ia32_finish,         /* called before codegen */
-	ia32_codegen         /* emit && done */
-};
-
 /**
  * Initializes a IA32 code generator.
  */
-static void *ia32_cg_init(ir_graph *irg)
+static void ia32_init_graph(ir_graph *irg)
 {
-	ia32_isa_t      *isa = (ia32_isa_t *)be_get_irg_arch_env(irg);
-	ia32_code_gen_t *cg  = XMALLOCZ(ia32_code_gen_t);
+	struct obstack  *obst     = be_get_be_obst(irg);
+	ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
 
-	cg->impl      = &ia32_code_gen_if;
-	cg->irg       = irg;
-	cg->isa       = isa;
-	cg->blk_sched = NULL;
-	cg->dump      = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
-	cg->gprof     = (be_get_irg_options(irg)->gprof) ? 1 : 0;
+	irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
 
-	if (cg->gprof) {
+	if (gprof) {
 		/* Linux gprof implementation needs base pointer */
 		be_get_irg_options(irg)->omit_fp = 0;
 	}
 
-	/* enter it */
-	isa->cg = cg;
-
-#ifndef NDEBUG
-	if (isa->name_obst) {
-		obstack_free(isa->name_obst, NULL);
-		obstack_init(isa->name_obst);
-	}
-#endif /* NDEBUG */
-
-	assert(ia32_current_cg == NULL);
-	ia32_current_cg = cg;
-
-	return (arch_code_generator_t *)cg;
+	be_birg_from_irg(irg)->isa_link = irg_data;
 }
 
 
@@ -1501,17 +1439,17 @@ static const tarval_mode_info mo_integer = {
  */
 static void set_tarval_output_modes(void)
 {
-	int i;
+	size_t i;
 
-	for (i = get_irp_n_modes() - 1; i >= 0; --i) {
-		ir_mode *mode = get_irp_mode(i);
+	for (i = get_irp_n_modes(); i > 0;) {
+		ir_mode *mode = get_irp_mode(--i);
 
 		if (mode_is_int(mode))
 			set_tarval_mode_output_option(mode, &mo_integer);
 	}
 }
 
-const arch_isa_if_t ia32_isa_if;
+extern const arch_isa_if_t ia32_isa_if;
 
 /**
  * The template that generates a new ISA object.
@@ -1521,8 +1459,12 @@ const arch_isa_if_t ia32_isa_if;
 static ia32_isa_t ia32_isa_template = {
 	{
 		&ia32_isa_if,            /* isa interface implementation */
-		&ia32_gp_regs[REG_ESP],  /* stack pointer register */
-		&ia32_gp_regs[REG_EBP],  /* base pointer register */
+		N_IA32_REGISTERS,
+		ia32_registers,
+		N_IA32_CLASSES,
+		ia32_reg_classes,
+		&ia32_registers[REG_ESP],  /* stack pointer register */
+		&ia32_registers[REG_EBP],  /* base pointer register */
 		&ia32_reg_classes[CLASS_ia32_gp],  /* static link pointer register class */
 		-1,                      /* stack direction */
 		2,                       /* power of two stack alignment, 2^2 == 4 */
@@ -1531,16 +1473,9 @@ static ia32_isa_t ia32_isa_template = {
 		5,                       /* costs for a reload instruction */
 		false,                   /* no custom abi handling */
 	},
-	NULL,                    /* 16bit register names */
-	NULL,                    /* 8bit register names */
-	NULL,                    /* 8bit register names high */
 	NULL,                    /* types */
 	NULL,                    /* tv_ents */
-	NULL,                    /* current code generator */
 	NULL,                    /* abstract machine */
-#ifndef NDEBUG
-	NULL,                    /* name obstack */
-#endif
 };
 
 static void init_asm_constraints(void)
@@ -1595,61 +1530,27 @@ static void init_asm_constraints(void)
  */
 static arch_env_t *ia32_init(FILE *file_handle)
 {
-	static int inited = 0;
-	ia32_isa_t *isa;
-	int        i, n;
-
-	if (inited)
-		return NULL;
-	inited = 1;
+	ia32_isa_t *isa = XMALLOC(ia32_isa_t);
 
 	set_tarval_output_modes();
 
-	isa = XMALLOC(ia32_isa_t);
 	memcpy(isa, &ia32_isa_template, sizeof(*isa));
 
-	if (mode_fpcw == NULL) {
-		mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
+	if (ia32_mode_fpcw == NULL) {
+		ia32_mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
 	}
 
 	ia32_register_init();
 	ia32_create_opcodes(&ia32_irn_ops);
-	/* special handling for SwitchJmp */
-	op_ia32_SwitchJmp->ops.be_ops = &ia32_SwitchJmp_irn_ops;
 
 	be_emit_init(file_handle);
-	isa->regs_16bit     = pmap_create();
-	isa->regs_8bit      = pmap_create();
-	isa->regs_8bit_high = pmap_create();
 	isa->types          = pmap_create();
 	isa->tv_ent         = pmap_create();
 	isa->cpu            = ia32_init_machine_description();
 
-	ia32_build_16bit_reg_map(isa->regs_16bit);
-	ia32_build_8bit_reg_map(isa->regs_8bit);
-	ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
-
-#ifndef NDEBUG
-	isa->name_obst = XMALLOC(struct obstack);
-	obstack_init(isa->name_obst);
-#endif /* NDEBUG */
-
 	/* enter the ISA object into the intrinsic environment */
 	intrinsic_env.isa = isa;
 
-	/* emit asm includes */
-	n = get_irp_n_asms();
-	for (i = 0; i < n; ++i) {
-		be_emit_cstring("#APP\n");
-		be_emit_ident(get_irp_asm(i));
-		be_emit_cstring("\n#NO_APP\n");
-	}
-
-	/* needed for the debug support */
-	be_gas_emit_switch_section(GAS_SECTION_TEXT);
-	be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
-	be_emit_write_line();
-
 	return &isa->base;
 }
 
@@ -1660,49 +1561,20 @@ static arch_env_t *ia32_init(FILE *file_handle)
  */
 static void ia32_done(void *self)
 {
-	ia32_isa_t *isa = self;
+	ia32_isa_t *isa = (ia32_isa_t*)self;
 
 	/* emit now all global declarations */
 	be_gas_emit_decls(isa->base.main_env);
 
-	pmap_destroy(isa->regs_16bit);
-	pmap_destroy(isa->regs_8bit);
-	pmap_destroy(isa->regs_8bit_high);
 	pmap_destroy(isa->tv_ent);
 	pmap_destroy(isa->types);
 
-#ifndef NDEBUG
-	obstack_free(isa->name_obst, NULL);
-#endif /* NDEBUG */
-
 	be_emit_exit();
 
 	free(self);
 }
 
 
-/**
- * Return the number of register classes for this architecture.
- * We report always these:
- *  - the general purpose registers
- *  - the SSE floating point register set
- *  - the virtual floating point registers
- *  - the SSE vector register set
- */
-static unsigned ia32_get_n_reg_class(void)
-{
-	return N_CLASSES;
-}
-
-/**
- * Return the register class for index i.
- */
-static const arch_register_class_t *ia32_get_reg_class(unsigned i)
-{
-	assert(i < N_CLASSES);
-	return &ia32_reg_classes[i];
-}
-
 /**
  * Get the register class which shall be used to store a value of a given mode.
  * @param self The this pointer.
@@ -1725,33 +1597,33 @@ static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
                                                     const ir_mode *mode)
 {
 	static const arch_register_t *gpreg_param_reg_fastcall[] = {
-		&ia32_gp_regs[REG_ECX],
-		&ia32_gp_regs[REG_EDX],
+		&ia32_registers[REG_ECX],
+		&ia32_registers[REG_EDX],
 		NULL
 	};
 	static const unsigned MAXNUM_GPREG_ARGS = 3;
 
 	static const arch_register_t *gpreg_param_reg_regparam[] = {
-		&ia32_gp_regs[REG_EAX],
-		&ia32_gp_regs[REG_EDX],
-		&ia32_gp_regs[REG_ECX]
+		&ia32_registers[REG_EAX],
+		&ia32_registers[REG_EDX],
+		&ia32_registers[REG_ECX]
 	};
 
 	static const arch_register_t *gpreg_param_reg_this[] = {
-		&ia32_gp_regs[REG_ECX],
+		&ia32_registers[REG_ECX],
 		NULL,
 		NULL
 	};
 
 	static const arch_register_t *fpreg_sse_param_reg_std[] = {
-		&ia32_xmm_regs[REG_XMM0],
-		&ia32_xmm_regs[REG_XMM1],
-		&ia32_xmm_regs[REG_XMM2],
-		&ia32_xmm_regs[REG_XMM3],
-		&ia32_xmm_regs[REG_XMM4],
-		&ia32_xmm_regs[REG_XMM5],
-		&ia32_xmm_regs[REG_XMM6],
-		&ia32_xmm_regs[REG_XMM7]
+		&ia32_registers[REG_XMM0],
+		&ia32_registers[REG_XMM1],
+		&ia32_registers[REG_XMM2],
+		&ia32_registers[REG_XMM3],
+		&ia32_registers[REG_XMM4],
+		&ia32_registers[REG_XMM5],
+		&ia32_registers[REG_XMM6],
+		&ia32_registers[REG_XMM7]
 	};
 
 	static const arch_register_t *fpreg_sse_param_reg_this[] = {
@@ -1897,8 +1769,8 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 
 		assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
 
-		be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX], ABI_CONTEXT_BOTH);
-		be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX], ABI_CONTEXT_BOTH);
+		be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
+		be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
 	}
 	else if (n == 1) {
 		const arch_register_t *reg;
@@ -1907,66 +1779,12 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
 		assert(is_atomic_type(tp));
 		mode = get_type_mode(tp);
 
-		reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
+		reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
 
 		be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
 	}
 }
 
-static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
-{
-	(void) block_env;
-
-	if (!is_ia32_irn(irn)) {
-		return -1;
-	}
-
-	if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
-	    || is_ia32_ChangeCW(irn) || is_ia32_Immediate(irn))
-		return 0;
-
-	return 1;
-}
-
-/**
- * Initializes the code generator interface.
- */
-static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
-{
-	(void) self;
-	return &ia32_code_gen_if;
-}
-
-/**
- * Returns the estimated execution time of an ia32 irn.
- */
-static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
-{
-	(void) env;
-	return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
-}
-
-list_sched_selector_t ia32_sched_selector;
-
-/**
- * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
- */
-static const list_sched_selector_t *ia32_get_list_sched_selector(
-		const void *self, list_sched_selector_t *selector)
-{
-	(void) self;
-	memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
-	ia32_sched_selector.exectime              = ia32_sched_exectime;
-	ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
-	return &ia32_sched_selector;
-}
-
-static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
-{
-	(void) self;
-	return NULL;
-}
-
 /**
  * Returns the necessary byte alignment for storing a register of given class.
  */
@@ -1980,69 +1798,6 @@ static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
 	return bytes;
 }
 
-static const be_execution_unit_t ***ia32_get_allowed_execution_units(
-		const ir_node *irn)
-{
-	static const be_execution_unit_t *_allowed_units_BRANCH[] = {
-		&ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
-		&ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
-		NULL,
-	};
-	static const be_execution_unit_t *_allowed_units_GP[] = {
-		&ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
-		&ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
-		&ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
-		&ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
-		&ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
-		&ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
-		&ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
-		NULL,
-	};
-	static const be_execution_unit_t *_allowed_units_DUMMY[] = {
-		&be_machine_execution_units_DUMMY[0],
-		NULL,
-	};
-	static const be_execution_unit_t **_units_callret[] = {
-		_allowed_units_BRANCH,
-		NULL
-	};
-	static const be_execution_unit_t **_units_other[] = {
-		_allowed_units_GP,
-		NULL
-	};
-	static const be_execution_unit_t **_units_dummy[] = {
-		_allowed_units_DUMMY,
-		NULL
-	};
-	const be_execution_unit_t ***ret;
-
-	if (is_ia32_irn(irn)) {
-		ret = get_ia32_exec_units(irn);
-	} else if (is_be_node(irn)) {
-		if (be_is_Return(irn)) {
-			ret = _units_callret;
-		} else if (be_is_Barrier(irn)) {
-			ret = _units_dummy;
-		} else {
-			ret = _units_other;
-		}
-	}
-	else {
-		ret = _units_dummy;
-	}
-
-	return ret;
-}
-
-/**
- * Return the abstract ia32 machine.
- */
-static const be_machine_t *ia32_get_machine(const void *self)
-{
-	const ia32_isa_t *isa = self;
-	return isa->cpu;
-}
-
 /**
  * Return irp irgs in the desired order.
  */
@@ -2066,19 +1821,15 @@ static void ia32_mark_remat(ir_node *node)
 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
                                  ir_node *mux_false)
 {
-	ir_node *cmp_l;
-	ir_node *cmp_r;
-	ir_node *cmp;
-	pn_Cmp  pnc;
+	ir_node    *cmp_l;
+	ir_node    *cmp_r;
+	ir_relation relation;
 
-	if (!is_Proj(sel))
-		return false;
-	cmp = get_Proj_pred(sel);
-	if (!is_Cmp(cmp))
+	if (!is_Cmp(sel))
 		return false;
 
-	cmp_l = get_Cmp_left(cmp);
-	cmp_r = get_Cmp_right(cmp);
+	cmp_l = get_Cmp_left(sel);
+	cmp_r = get_Cmp_right(sel);
 	if (!mode_is_float(get_irn_mode(cmp_l)))
 		return false;
 
@@ -2089,28 +1840,28 @@ static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
 	 *  or max(a, b) = a >= b ? a : b
 	 * (Note we only handle float min/max here)
 	 */
-	pnc = get_Proj_proj(sel);
-	switch (pnc) {
-	case pn_Cmp_Ge:
-	case pn_Cmp_Gt:
+	relation = get_Cmp_relation(sel);
+	switch (relation) {
+	case ir_relation_greater_equal:
+	case ir_relation_greater:
 		/* this is a max */
 		if (cmp_l == mux_true && cmp_r == mux_false)
 			return true;
 		break;
-	case pn_Cmp_Le:
-	case pn_Cmp_Lt:
+	case ir_relation_less_equal:
+	case ir_relation_less:
 		/* this is a min */
 		if (cmp_l == mux_true && cmp_r == mux_false)
 			return true;
 		break;
-	case pn_Cmp_Uge:
-	case pn_Cmp_Ug:
+	case ir_relation_unordered_greater_equal:
+	case ir_relation_unordered_greater:
 		/* this is a min */
 		if (cmp_l == mux_false && cmp_r == mux_true)
 			return true;
 		break;
-	case pn_Cmp_Ule:
-	case pn_Cmp_Ul:
+	case ir_relation_unordered_less_equal:
+	case ir_relation_unordered_less:
 		/* this is a max */
 		if (cmp_l == mux_false && cmp_r == mux_true)
 			return true;
@@ -2133,7 +1884,8 @@ static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
 		return false;
 
 	if (is_Const(mux_true) && is_Const(mux_false)) {
-		/* we can create a set plus up two 3 instructions for any combination of constants */
+		/* we can create a set plus up two 3 instructions for any combination
+		 * of constants */
 		return true;
 	}
 
@@ -2153,35 +1905,30 @@ static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
 
 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
 {
-	ir_node *cmp;
-	ir_node *cmp_left;
-	ir_node *cmp_right;
-	ir_node *sub_left;
-	ir_node *sub_right;
-	ir_mode *mode;
-	long     pn;
+	ir_node    *cmp_left;
+	ir_node    *cmp_right;
+	ir_node    *sub_left;
+	ir_node    *sub_right;
+	ir_mode    *mode;
+	ir_relation relation;
 
-	if (!is_Proj(sel))
-		return false;
-
-	cmp = get_Proj_pred(sel);
-	if (!is_Cmp(cmp))
+	if (!is_Cmp(sel))
 		return false;
 
 	mode = get_irn_mode(mux_true);
 	if (mode_is_signed(mode) || mode_is_float(mode))
 		return false;
 
-	pn        = get_Proj_proj(sel);
-	cmp_left  = get_Cmp_left(cmp);
-	cmp_right = get_Cmp_right(cmp);
+	relation  = get_Cmp_relation(sel);
+	cmp_left  = get_Cmp_left(sel);
+	cmp_right = get_Cmp_right(sel);
 
 	/* "move" zero constant to false input */
 	if (is_Const(mux_true) && is_Const_null(mux_true)) {
 		ir_node *tmp = mux_false;
 		mux_false = mux_true;
 		mux_true  = tmp;
-		pn = get_negated_pnc(pn, mode);
+		relation = get_negated_relation(relation);
 	}
 	if (!is_Const(mux_false) || !is_Const_null(mux_false))
 		return false;
@@ -2191,11 +1938,11 @@ static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
 	sub_right = get_Sub_right(mux_true);
 
 	/* Mux(a >=u b, 0, a-b) */
-	if ((pn == pn_Cmp_Gt || pn == pn_Cmp_Ge)
+	if ((relation & ir_relation_greater)
 			&& sub_left == cmp_left && sub_right == cmp_right)
 		return true;
 	/* Mux(a <=u b, 0, b-a) */
-	if ((pn == pn_Cmp_Lt || pn == pn_Cmp_Le)
+	if ((relation & ir_relation_less)
 			&& sub_left == cmp_right && sub_right == cmp_left)
 		return true;
 
@@ -2241,19 +1988,16 @@ static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
 		return true;
 
 	/* Check Cmp before the node */
-	if (is_Proj(sel)) {
-		ir_node *cmp = get_Proj_pred(sel);
-		if (is_Cmp(cmp)) {
-			ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
-
-			/* we can't handle 64bit compares */
-			if (get_mode_size_bits(cmp_mode) > 32)
-				return false;
-
-			/* we can't handle float compares */
-			if (mode_is_float(cmp_mode))
-				return false;
-		}
+	if (is_Cmp(sel)) {
+		ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
+
+		/* we can't handle 64bit compares */
+		if (get_mode_size_bits(cmp_mode) > 32)
+			return false;
+
+		/* we can't handle float compares */
+		if (mode_is_float(cmp_mode))
+			return false;
 	}
 
 	/* did we disable cmov generation? */
@@ -2278,15 +2022,29 @@ static int ia32_is_valid_clobber(const char *clobber)
 	return ia32_get_clobber_register(clobber) != NULL;
 }
 
+static ir_node *ia32_create_set(ir_node *cond)
+{
+	/* ia32-set function produces 8-bit results which have to be converted */
+	ir_node *set   = ir_create_mux_set(cond, mode_Bu);
+	ir_node *block = get_nodes_block(set);
+	return new_r_Conv(block, set, mode_Iu);
+}
+
 static void ia32_lower_for_target(void)
 {
-	int n_irgs = get_irp_n_irgs();
-	int i;
+	size_t i, n_irgs = get_irp_n_irgs();
 	lower_mode_b_config_t lower_mode_b_config = {
 		mode_Iu,  /* lowered mode */
-		mode_Bu,  /* preferred mode for set */
+		ia32_create_set,
 		0,        /* don't lower direct compares */
 	};
+	lower_params_t params = {
+		4,                                     /* def_ptr_alignment */
+		LF_COMPOUND_RETURN | LF_RETURN_HIDDEN, /* flags */
+		ADD_HIDDEN_ALWAYS_IN_FRONT,            /* hidden_params */
+		NULL,                                  /* find pointer type */
+		NULL,                                  /* ret_compound_in_regs */
+	};
 
 	/* perform doubleword lowering */
 	lwrdw_param_t lower_dw_params = {
@@ -2295,12 +2053,18 @@ static void ia32_lower_for_target(void)
 		ia32_create_intrinsic_fkt,
 		&intrinsic_env,
 	};
+
+	/* lower compound param handling */
+	lower_calls_with_compounds(&params);
+
 	lower_dw_ops(&lower_dw_params);
 
-	/* lower for mode_b stuff */
 	for (i = 0; i < n_irgs; ++i) {
 		ir_graph *irg = get_irp_irg(i);
+		/* lower for mode_b stuff */
 		ir_lower_mode_b(irg, &lower_mode_b_config);
+		/* break up switches with wide ranges */
+		lower_switch(irg, 256, true);
 	}
 }
 
@@ -2309,23 +2073,25 @@ static void ia32_lower_for_target(void)
  */
 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
 {
-	ir_node  *st, *p = trampoline;
-	ir_mode *mode    = get_irn_mode(p);
+	ir_graph *irg  = get_irn_irg(block);
+	ir_node  *p    = trampoline;
+	ir_mode  *mode = get_irn_mode(p);
+	ir_node  *st;
 
 	/* mov  ecx,<env> */
-	st  = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
+	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
 	mem = new_r_Proj(st, mode_M, pn_Store_M);
-	p   = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
-	st  = new_r_Store(block, mem, p, env, 0);
+	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
+	st  = new_r_Store(block, mem, p, env, cons_none);
 	mem = new_r_Proj(st, mode_M, pn_Store_M);
-	p   = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
+	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
 	/* jmp  <callee> */
-	st  = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
+	st  = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
 	mem = new_r_Proj(st, mode_M, pn_Store_M);
-	p   = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
-	st  = new_r_Store(block, mem, p, callee, 0);
+	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 1), mode);
+	st  = new_r_Store(block, mem, p, callee, cons_none);
 	mem = new_r_Proj(st, mode_M, pn_Store_M);
-	p   = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
+	p   = new_r_Add(block, p, new_r_Const_long(irg, mode_Iu, 4), mode);
 
 	return mem;
 }
@@ -2338,7 +2104,7 @@ static const backend_params *ia32_get_libfirm_params(void)
 	static const ir_settings_arch_dep_t ad = {
 		1,                   /* also use subs */
 		4,                   /* maximum shifts */
-		31,                  /* maximum shift amount */
+		63,                  /* maximum shift amount */
 		ia32_evaluate_insn,  /* evaluate the instruction sequence */
 
 		1,  /* allow Mulhs */
@@ -2349,7 +2115,6 @@ static const backend_params *ia32_get_libfirm_params(void)
 		1,     /* support inline assembly */
 		1,     /* support Rotl nodes */
 		0,     /* little endian */
-		ia32_lower_for_target,
 		NULL,  /* will be set later */
 		ia32_is_mux_allowed,
 		NULL,  /* float arithmetic mode, will be set below */
@@ -2400,30 +2165,34 @@ static const lc_opt_table_entry_t ia32_options[] = {
 #ifdef FIRM_GRGEN_BE
 	LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
 #endif
-	LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
-	               &ia32_isa_template.base.stack_alignment),
+	LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
+	                &ia32_isa_template.base.stack_alignment),
+	LC_OPT_ENT_BOOL("gprof",      "create gprof profiling code",                                    &gprof),
 	LC_OPT_LAST
 };
 
 const arch_isa_if_t ia32_isa_if = {
 	ia32_init,
+	ia32_lower_for_target,
 	ia32_done,
 	ia32_handle_intrinsics,
-	ia32_get_n_reg_class,
-	ia32_get_reg_class,
 	ia32_get_reg_class_for_mode,
 	ia32_get_call_abi,
-	ia32_get_code_generator_if,
-	ia32_get_list_sched_selector,
-	ia32_get_ilp_sched_selector,
 	ia32_get_reg_class_alignment,
 	ia32_get_libfirm_params,
-	ia32_get_allowed_execution_units,
-	ia32_get_machine,
 	ia32_get_irg_list,
 	ia32_mark_remat,
 	ia32_parse_asm_constraint,
-	ia32_is_valid_clobber
+	ia32_is_valid_clobber,
+
+	ia32_init_graph,
+	ia32_get_pic_base,   /* return node used as base in pic code addresses */
+	ia32_before_abi,     /* before abi introduce hook */
+	ia32_prepare_graph,
+	ia32_before_ra,      /* before register allocation hook */
+	ia32_after_ra,       /* after register allocation hook */
+	ia32_finish,         /* called before codegen */
+	ia32_emit,           /* emit && done */
 };
 
 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);