X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=269901cf73883a5ebd98c5fcc7feda566185650e;hb=927eac90f1c28092a5406def6540bb9fae752360;hp=73704d61dc6baf36c56f81645cd38699fe59f2fa;hpb=79a07d6d7bcf59fc06b1e6dbf724f01fbd7e3236;p=libfirm

diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c
index 73704d61d..269901cf7 100644
--- a/ir/be/ia32/bearch_ia32.c
+++ b/ir/be/ia32/bearch_ia32.c
@@ -1,6 +1,6 @@
 /**
  * This is the main ia32 firm backend driver.
- *
+ * @author Christian Wuerdig
  * $Id$
  */
 
@@ -29,8 +29,8 @@
 #include "ircons.h"
 #include "irgmod.h"
 #include "irgopt.h"
-
-#include "bitset.h"
+#include "irbitset.h"
+#include "pdeq.h"
 #include "debug.h"
 
 #include "../beabi.h"                 /* the general register allocator interface */
@@ -48,6 +48,9 @@
 #include "ia32_map_regs.h"
 #include "ia32_optimize.h"
 #include "ia32_x87.h"
+#include "ia32_dbg_stat.h"
+#include "ia32_finish.h"
+#include "ia32_util.h"
 
 #define DEBUG_MODULE "firm.be.ia32.isa"
 
@@ -146,23 +149,23 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_re
 		}
 	}
 	else {
-		/* treat Phi like Const with default requirements */
-		if (is_Phi(irn)) {
-			DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
+		/* treat Unknowns like Const with default requirements */
+		if (is_Unknown(irn)) {
+			DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
 			if (mode_is_float(mode)) {
 				if (USE_SSE2(ops->cg))
-					memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req));
+					memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
 				else
-					memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req));
+					memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
 			}
 			else if (mode_is_int(mode) || mode_is_reference(mode))
-				memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
+				memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
 			else if (mode == mode_T || mode == mode_M) {
-				DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
+				DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
 				return NULL;
 			}
 			else
-				assert(0 && "unsupported Phi-Mode");
+				assert(0 && "unsupported Unknown-Mode");
 		}
 		else {
 			DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
@@ -229,6 +232,12 @@ static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
 	irn = my_skip_proj(irn);
 	if (is_cfop(irn))
 		return arch_irn_class_branch;
+	else if (is_ia32_Cnst(irn))
+		return arch_irn_class_const;
+	else if (is_ia32_Ld(irn))
+		return arch_irn_class_load;
+	else if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
+		return arch_irn_class_store;
 	else if (is_ia32_irn(irn))
 		return arch_irn_class_normal;
 	else
@@ -240,6 +249,8 @@ static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
 	if (is_ia32_irn(irn))
 		return get_ia32_flags(irn);
 	else {
+		if (is_Unknown(irn))
+			return arch_irn_flags_ignore;
 		return 0;
 	}
 }
@@ -287,6 +298,12 @@ static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir
 	return env;
 }
 
+/**
+ * Put all registers which are saved by the prologue/epilogue in a set.
+ *
+ * @param self  The callback object.
+ * @param s     The result set.
+ */
 static void ia32_abi_dont_save_regs(void *self, pset *s)
 {
 	ia32_abi_env_t *env = self;
@@ -295,10 +312,12 @@ static void ia32_abi_dont_save_regs(void *self, pset *s)
 }
 
 /**
- * Generate the prologue.
+ * Generate the routine prologue.
+ *
  * @param self    The callback object.
  * @param mem     A pointer to the mem node. Update this if you define new memory.
- * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ *
  * @return        The register which shall be used as a stack frame base.
  *
  * All nodes which define registers in @p reg_map must keep @p reg_map current.
@@ -308,27 +327,31 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
 	ia32_abi_env_t *env              = self;
 
 	if (!env->flags.try_omit_fp) {
-		int reg_size         = get_mode_size_bytes(env->isa->bp->reg_class->mode);
 		ir_node *bl          = get_irg_start_block(env->irg);
 		ir_node *curr_sp     = be_abi_reg_map_get(reg_map, env->isa->sp);
 		ir_node *curr_bp     = be_abi_reg_map_get(reg_map, env->isa->bp);
-		ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
-		ir_node *store_bp;
+		ir_node *push;
 
 		/* push ebp */
-		curr_sp  = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
-		store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
-		set_ia32_am_support(store_bp, ia32_am_Dest);
-		set_ia32_am_flavour(store_bp, ia32_B);
-		set_ia32_op_type(store_bp, ia32_AddrModeD);
-		set_ia32_ls_mode(store_bp, env->isa->bp->reg_class->mode);
-		*mem     = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
+		push    = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
+		curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
+		*mem    = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
+
+		/* the push must have SP out register */
+		arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+		set_ia32_flags(push, arch_irn_flags_ignore);
 
 		/* move esp to ebp */
 		curr_bp  = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
 		be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
 		arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
-		be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_dont_spill);
+		be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
+
+		/* beware: the copy must be done before any other sp use */
+		curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
+		be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
+		arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+		be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
 
 		be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
 		be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
@@ -339,37 +362,56 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap
 	return env->isa->sp;
 }
 
+/**
+ * Generate the routine epilogue.
+ * @param self    The callback object.
+ * @param bl      The block for the epilog
+ * @param mem     A pointer to the mem node. Update this if you define new memory.
+ * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
+ * @return        The register which shall be used as a stack frame base.
+ *
+ * All nodes which define registers in @p reg_map must keep @p reg_map current.
+ */
 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
 {
 	ia32_abi_env_t *env  = self;
 	ir_node *curr_sp     = be_abi_reg_map_get(reg_map, env->isa->sp);
 	ir_node *curr_bp     = be_abi_reg_map_get(reg_map, env->isa->bp);
-	ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
 
 	if (env->flags.try_omit_fp) {
 		/* simply remove the stack frame here */
 		curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
 	}
-
 	else {
-		ir_node *load_bp;
+		const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
 		ir_mode *mode_bp = env->isa->bp->reg_class->mode;
-		int reg_size     = get_mode_size_bytes(env->isa->bp->reg_class->mode);
-
-		/* copy ebp to esp */
-		curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
-
-		/* pop ebp */
-		load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
-		set_ia32_am_support(load_bp, ia32_am_Source);
-		set_ia32_am_flavour(load_bp, ia32_B);
-		set_ia32_op_type(load_bp, ia32_AddrModeS);
-		set_ia32_ls_mode(load_bp, mode_bp);
-		curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
-		*mem    = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
-		arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
 
-		curr_sp  = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_shrink);
+		/* gcc always emits a leave at the end of a routine */
+		if (1 || ARCH_AMD(isa->opt_arch)) {
+			ir_node *leave;
+
+			/* leave */
+			leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
+			set_ia32_flags(leave, arch_irn_flags_ignore);
+			curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
+			curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
+			*mem    = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
+		}
+		else {
+			ir_node *pop;
+
+			/* copy ebp to esp */
+			curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
+
+			/* pop ebp */
+			pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
+			set_ia32_flags(pop, arch_irn_flags_ignore);
+			curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
+			curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
+			*mem    = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
+		}
+		arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
+		arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
 	}
 
 	be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
@@ -383,35 +425,283 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_
  */
 static ir_type *ia32_abi_get_between_type(void *self)
 {
+#define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
 	static ir_type *omit_fp_between_type = NULL;
 	static ir_type *between_type         = NULL;
 
 	ia32_abi_env_t *env = self;
 
-	if(!between_type) {
+	if ( !between_type) {
 		entity *old_bp_ent;
 		entity *ret_addr_ent;
 		entity *omit_fp_ret_addr_ent;
 
-		ir_type *old_bp_type   = new_type_primitive(new_id_from_str("bp"), mode_P);
-		ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
+		ir_type *old_bp_type   = new_type_primitive(IDENT("bp"), mode_P);
+		ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
 
-		between_type           = new_type_class(new_id_from_str("ia32_between_type"));
-		old_bp_ent             = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
-		ret_addr_ent           = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
+		between_type           = new_type_struct(IDENT("ia32_between_type"));
+		old_bp_ent             = new_entity(between_type, IDENT("old_bp"), old_bp_type);
+		ret_addr_ent           = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
 
 		set_entity_offset_bytes(old_bp_ent, 0);
 		set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
 		set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
+		set_type_state(between_type, layout_fixed);
 
-		omit_fp_between_type   = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
-		omit_fp_ret_addr_ent   = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
+		omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
+		omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
 
 		set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
 		set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
+		set_type_state(omit_fp_between_type, layout_fixed);
 	}
 
 	return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
+#undef IDENT
+}
+
+/**
+ * Get the estimated cycle count for @p irn.
+ *
+ * @param self The this pointer.
+ * @param irn  The node.
+ *
+ * @return     The estimated cycle count for this operation
+ */
+static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
+{
+	int cost;
+
+	if(is_Proj(irn))
+	  return 0;
+
+	switch (get_ia32_irn_opcode(irn)) {
+	case iro_ia32_xDiv:
+	case iro_ia32_DivMod:
+		cost = 8;
+		break;
+
+	case iro_ia32_xLoad:
+	case iro_ia32_l_Load:
+	case iro_ia32_Load:
+		cost = 25;
+		break;
+
+	case iro_ia32_Push:
+	case iro_ia32_Pop:
+		cost = 5;
+		break;
+
+	case iro_ia32_xStore:
+	case iro_ia32_l_Store:
+	case iro_ia32_Store:
+	case iro_ia32_Store8Bit:
+		cost = 50;
+		break;
+
+	case iro_ia32_MulS:
+	case iro_ia32_Mul:
+	case iro_ia32_Mulh:
+	case iro_ia32_xMul:
+	case iro_ia32_l_MulS:
+	case iro_ia32_l_Mul:
+		cost = 2;
+		break;
+
+	default:
+		cost = 1;
+	}
+
+	return cost;
+}
+
+/**
+ * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
+ *
+ * @param irn       The original operation
+ * @param i         Index of the argument we want the inverse operation to yield
+ * @param inverse   struct to be filled with the resulting inverse op
+ * @param obstack   The obstack to use for allocation of the returned nodes array
+ * @return          The inverse operation or NULL if operation invertible
+ */
+static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
+	ir_graph *irg;
+	ir_mode  *mode;
+	ir_node  *block, *noreg, *nomem;
+	int      pnc;
+
+	/* we cannot invert non-ia32 irns */
+	if (! is_ia32_irn(irn))
+		return NULL;
+
+	/* operand must always be a real operand (not base, index or mem) */
+	if (i != 2 && i != 3)
+		return NULL;
+
+	/* we don't invert address mode operations */
+	if (get_ia32_op_type(irn) != ia32_Normal)
+		return NULL;
+
+	irg   = get_irn_irg(irn);
+	block = get_nodes_block(irn);
+	mode  = get_ia32_res_mode(irn);
+	noreg = get_irn_n(irn, 0);
+	nomem = new_r_NoMem(irg);
+
+	/* initialize structure */
+	inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
+	inverse->costs = 0;
+	inverse->n     = 2;
+
+	switch (get_ia32_irn_opcode(irn)) {
+		case iro_ia32_Add:
+			if (get_ia32_immop_type(irn) == ia32_ImmConst) {
+				/* we have an add with a const here */
+				/* invers == add with negated const */
+				inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+				pnc               = pn_ia32_Add_res;
+				inverse->costs   += 1;
+				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
+				set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
+				set_ia32_commutative(inverse->nodes[0]);
+			}
+			else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
+				/* we have an add with a symconst here */
+				/* invers == sub with const */
+				inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+				pnc               = pn_ia32_Sub_res;
+				inverse->costs   += 2;
+				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
+			}
+			else {
+				/* normal add: inverse == sub */
+				ir_node *proj = ia32_get_res_proj(irn);
+				assert(proj);
+
+				inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
+				pnc               = pn_ia32_Sub_res;
+				inverse->costs   += 2;
+			}
+			break;
+		case iro_ia32_Sub:
+			if (get_ia32_immop_type(irn) != ia32_ImmNone) {
+				/* we have a sub with a const/symconst here */
+				/* invers == add with this const */
+				inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+				pnc               = pn_ia32_Add_res;
+				inverse->costs   += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
+				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
+			}
+			else {
+				/* normal sub */
+				ir_node *proj = ia32_get_res_proj(irn);
+				assert(proj);
+
+				if (i == 2) {
+					inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
+				}
+				else {
+					inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
+				}
+				pnc             = pn_ia32_Sub_res;
+				inverse->costs += 1;
+			}
+			break;
+		case iro_ia32_Eor:
+			if (get_ia32_immop_type(irn) != ia32_ImmNone) {
+				/* xor with const: inverse = xor */
+				inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
+				pnc               = pn_ia32_Eor_res;
+				inverse->costs   += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
+				copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
+			}
+			else {
+				/* normal xor */
+				inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
+				pnc               = pn_ia32_Eor_res;
+				inverse->costs   += 1;
+			}
+			break;
+		case iro_ia32_Not: {
+			ir_node *proj = ia32_get_res_proj(irn);
+			assert(proj);
+
+			inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
+			pnc = pn_ia32_Not_res;
+			inverse->costs   += 1;
+			break;
+		}
+		case iro_ia32_Minus: {
+			ir_node *proj = ia32_get_res_proj(irn);
+			assert(proj);
+
+			inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
+			pnc               = pn_ia32_Minus_res;
+			inverse->costs   += 1;
+			break;
+		}
+		default:
+			/* inverse operation not supported */
+			return NULL;
+	}
+
+	set_ia32_res_mode(inverse->nodes[0], mode);
+	inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
+
+	return inverse;
+}
+
+/**
+ * Check if irn can load it's operand at position i from memory (source addressmode).
+ * @param self   Pointer to irn ops itself
+ * @param irn    The irn to be checked
+ * @param i      The operands position
+ * @return Non-Zero if operand can be loaded
+ */
+static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
+	if (! is_ia32_irn(irn)                            ||  /* must be an ia32 irn */
+		get_irn_arity(irn) != 5                       ||  /* must be a binary operation */
+		get_ia32_op_type(irn) != ia32_Normal          ||  /* must not already be a addressmode irn */
+		! (get_ia32_am_support(irn) & ia32_am_Source) ||  /* must be capable of source addressmode */
+        (i != 2 && i != 3)                            ||  /* a "real" operand position must be requested */
+		(i == 2 && ! is_ia32_commutative(irn))        ||  /* if first operand requested irn must be commutative */
+		is_ia32_use_frame(irn))                           /* must not already use frame */
+		return 0;
+
+	return 1;
+}
+
+static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *reload, unsigned int i) {
+	assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
+	assert(get_nodes_block(reload) == get_nodes_block(irn) && "Reload must be in same block as irn.");
+
+	if (get_irn_n_edges(reload) > 1)
+		return;
+
+	if (i == 2) {
+		ir_node *tmp = get_irn_n(irn, 3);
+		set_irn_n(irn, 3, get_irn_n(irn, 2));
+		set_irn_n(irn, 2, tmp);
+	}
+
+	set_ia32_am_support(irn, ia32_am_Source);
+	set_ia32_op_type(irn, ia32_AddrModeS);
+	set_ia32_am_flavour(irn, ia32_B);
+	set_ia32_ls_mode(irn, get_irn_mode(reload));
+	set_ia32_frame_ent(irn, be_get_frame_entity(reload));
+	set_ia32_use_frame(irn);
+
+	set_irn_n(irn, 0, be_get_Reload_frame(reload));
+	set_irn_n(irn, 4, be_get_Reload_mem(reload));
+
+	/*
+		Input at position one is index register, which is NoReg.
+		We would need cg object to get a real noreg, but we cannot
+		access it from here.
+	 */
+	set_irn_n(irn, 3, get_irn_n(irn, 1));
+
+	DBG_OPT_AM_S(reload, irn);
 }
 
 static const be_abi_callbacks_t ia32_abi_callbacks = {
@@ -432,7 +722,11 @@ static const arch_irn_ops_if_t ia32_irn_ops_if = {
 	ia32_classify,
 	ia32_get_flags,
 	ia32_get_frame_entity,
-	ia32_set_stack_bias
+	ia32_set_stack_bias,
+	ia32_get_inverse,
+	ia32_get_op_estimated_cost,
+	ia32_possible_memory_operand,
+	ia32_perform_memory_operand,
 };
 
 ia32_irn_ops_t ia32_irn_ops = {
@@ -459,135 +753,92 @@ ia32_irn_ops_t ia32_irn_ops = {
  */
 static void ia32_prepare_graph(void *self) {
 	ia32_code_gen_t *cg = self;
+	dom_front_info_t *dom;
 	DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
 
 	FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
-	irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
-	be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
 
-	if (cg->opt.doam) {
-		edges_deactivate(cg->irg);
-		//dead_node_elimination(cg->irg);
-		edges_activate(cg->irg);
+	/* 1st: transform constants and psi condition trees */
+	ia32_pre_transform_phase(cg);
+
+	/* 2nd: transform all remaining nodes */
+	ia32_register_transformers();
+	dom = be_compute_dominance_frontiers(cg->irg);
+	irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
+	be_free_dominance_frontiers(dom);
 
-		FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
+	if (cg->dump)
+		be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
 
-		irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
+	/* 3rd: optimize address mode */
+	FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
+	ia32_optimize_addressmode(cg);
+
+	if (cg->dump)
 		be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
-	}
 
 	DEBUG_ONLY(cg->mod = old_mod;)
 }
 
-
 /**
- * Insert copies for all ia32 nodes where the should_be_same requirement
- * is not fulfilled.
- * Transform Sub into Neg -- Add if IN2 == OUT
+ * Dummy functions for hooks we don't need but which must be filled.
  */
-static void ia32_finish_node(ir_node *irn, void *env) {
-	ia32_code_gen_t            *cg = env;
-	const ia32_register_req_t **reqs;
-	const arch_register_t      *out_reg, *in_reg, *in2_reg;
-	int                         n_res, i;
-	ir_node                    *copy, *in_node, *block, *in2_node;
-	ia32_op_type_t              op_tp;
+static void ia32_before_sched(void *self) {
+}
 
-	if (is_ia32_irn(irn)) {
-		/* AM Dest nodes don't produce any values  */
-		op_tp = get_ia32_op_type(irn);
-		if (op_tp == ia32_AddrModeD)
-			goto end;
-
-		reqs  = get_ia32_out_req_all(irn);
-		n_res = get_ia32_n_res(irn);
-		block = get_nodes_block(irn);
-
-		/* check all OUT requirements, if there is a should_be_same */
-		if (op_tp == ia32_Normal) {
-			for (i = 0; i < n_res; i++) {
-				if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
-					/* get in and out register */
-					out_reg  = get_ia32_out_reg(irn, i);
-					in_node  = get_irn_n(irn, reqs[i]->same_pos);
-					in_reg   = arch_get_irn_register(cg->arch_env, in_node);
-					in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
-					in2_reg  = arch_get_irn_register(cg->arch_env, in2_node);
-
-					/* don't copy ignore nodes */
-					if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
-						continue;
-
-					/* check if in and out register are equal */
-					if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
-						/* in case of a commutative op: just exchange the in's */
-						if (is_ia32_commutative(irn) && REGS_ARE_EQUAL(out_reg, in2_reg)) {
-							set_irn_n(irn, reqs[i]->same_pos, in2_node);
-							set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
-						}
-						else {
-							DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
-							/* create copy from in register */
-							copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
-
-							/* destination is the out register */
-							arch_set_irn_register(cg->arch_env, copy, out_reg);
-
-							/* insert copy before the node into the schedule */
-							sched_add_before(irn, copy);
-
-							/* set copy as in */
-							set_irn_n(irn, reqs[i]->same_pos, copy);
-						}
-					}
-				}
-			}
-		}
+static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
+	int i;
+	ir_mode *mode;
+	ir_node *mem_proj;
 
-		/* If we have a CondJmp with immediate, we need to    */
-		/* check if it's the right operand, otherwise we have */
-		/* to change it, as CMP doesn't support immediate as  */
-		/* left operands.                                     */
-		if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
-			long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
-			set_ia32_op_type(irn, ia32_AddrModeD);
-			set_ia32_pncode(irn, pnc);
-		}
+	if (is_Block(irn))
+		return;
 
-		/* check if there is a sub which need to be transformed */
-		ia32_transform_sub_to_neg_add(irn, cg);
+	mode = get_irn_mode(irn);
 
-		/* transform a LEA into an Add if possible */
-		ia32_transform_lea_to_add(irn, cg);
-	}
-end:
+	/* check if we already saw this node or the node has more than one user */
+	if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1)
+		return;
 
-	/* check for peephole optimization */
-	ia32_peephole_optimization(irn, cg);
-}
+	/* mark irn visited */
+	bitset_add_irn(already_visited, irn);
 
-static void ia32_finish_irg_walker(ir_node *block, void *env) {
-	ir_node *irn, *next;
+	/* non-Tuple nodes with one user: ok, return */
+	if (get_irn_n_edges(irn) >= 1 && mode != mode_T)
+		return;
 
-	for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
-		next = sched_next(irn);
-		ia32_finish_node(irn, env);
+	/* tuple node has one user which is not the mem proj-> ok */
+	if (mode == mode_T && get_irn_n_edges(irn) == 1) {
+		mem_proj = ia32_get_proj_for_mode(irn, mode_M);
+		if (! mem_proj)
+			return;
 	}
-}
 
-/**
- * Add Copy nodes for not fulfilled should_be_equal constraints
- */
-static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
-	irg_block_walk_graph(irg, NULL, ia32_finish_irg_walker, cg);
-}
+	for (i = get_irn_arity(irn) - 1; i >= 0; i--) {
+		ir_node *pred = get_irn_n(irn, i);
 
+		/* do not follow memory edges or we will accidentally remove stores */
+		if (is_Proj(pred) && get_irn_mode(pred) == mode_M)
+			continue;
 
+		set_irn_n(irn, i, new_Bad());
 
-/**
- * Dummy functions for hooks we don't need but which must be filled.
- */
-static void ia32_before_sched(void *self) {
+		/*
+			The current node is about to be removed: if the predecessor
+			has only this node as user, it need to be removed as well.
+		*/
+		if (get_irn_n_edges(pred) <= 1)
+			remove_unused_nodes(pred, already_visited);
+	}
+
+	if (sched_is_scheduled(irn))
+		sched_remove(irn);
+}
+
+static void remove_unused_loads_walker(ir_node *irn, void *env) {
+	bitset_t *already_visited = env;
+	if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
+		remove_unused_nodes(irn, env);
 }
 
 /**
@@ -596,9 +847,19 @@ static void ia32_before_sched(void *self) {
  * simulator and the emitter.
  */
 static void ia32_before_ra(void *self) {
-	ia32_code_gen_t *cg = self;
+	ia32_code_gen_t *cg              = self;
+	bitset_t        *already_visited = bitset_irg_malloc(cg->irg);
 
 	cg->blk_sched = sched_create_block_schedule(cg->irg);
+
+	/*
+		Handle special case:
+		There are sometimes unused loads, only pinned by memory.
+		We need to remove those Loads and all other nodes which won't be used
+		after removing the Load from schedule.
+	*/
+	irg_walk_graph(cg->irg, remove_unused_loads_walker, NULL, already_visited);
+	bitset_free(already_visited);
 }
 
 
@@ -623,12 +884,12 @@ static void transform_to_Load(ia32_transform_env_t *env) {
 
 	if (mode_is_float(mode)) {
 		if (USE_SSE2(env->cg))
-			new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+			new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
 		else
-			new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+			new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
 	}
 	else {
-		new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+		new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
 	}
 
 	set_ia32_am_support(new_op, ia32_am_Source);
@@ -638,6 +899,8 @@ static void transform_to_Load(ia32_transform_env_t *env) {
 	set_ia32_frame_ent(new_op, ent);
 	set_ia32_use_frame(new_op);
 
+	DBG_OPT_RELOAD2LD(irn, new_op);
+
 	proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
 
 	if (sched_point) {
@@ -651,7 +914,7 @@ static void transform_to_Load(ia32_transform_env_t *env) {
 	reg = arch_get_irn_register(env->cg->arch_env, irn);
 	arch_set_irn_register(env->cg->arch_env, new_op, reg);
 
-	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
+	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
 
 	exchange(irn, proj);
 }
@@ -676,15 +939,15 @@ static void transform_to_Store(ia32_transform_env_t *env) {
 
 	if (mode_is_float(mode)) {
 		if (USE_SSE2(env->cg))
-			new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+			new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
 		else
-			new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+			new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
 	}
 	else if (get_mode_size_bits(mode) == 8) {
-		new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+		new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
 	}
 	else {
-		new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
+		new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
 	}
 
 	set_ia32_am_support(new_op, ia32_am_Dest);
@@ -694,16 +957,16 @@ static void transform_to_Store(ia32_transform_env_t *env) {
 	set_ia32_frame_ent(new_op, ent);
 	set_ia32_use_frame(new_op);
 
-	proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
+	DBG_OPT_SPILL2ST(irn, new_op);
+
+	proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
 
 	if (sched_point) {
 		sched_add_after(sched_point, new_op);
-		sched_add_after(new_op, proj);
-
 		sched_remove(irn);
 	}
 
-	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
+	SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
 
 	exchange(irn, proj);
 }
@@ -748,10 +1011,11 @@ static void ia32_after_ra_walker(ir_node *block, void *env) {
 			transform_to_Load(&tenv);
 		}
 		else if (be_is_Spill(node)) {
+			ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
 			/* we always spill the whole register  */
 			tenv.dbg  = get_irn_dbg_info(node);
 			tenv.irn  = node;
-			tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
+			tenv.mode = fix_spill_mode(cg, get_irn_mode(spillval));
 			transform_to_Store(&tenv);
 		}
 	}
@@ -766,10 +1030,11 @@ static void ia32_after_ra_walker(ir_node *block, void *env) {
  */
 static void ia32_after_ra(void *self) {
 	ia32_code_gen_t *cg = self;
+
 	irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
 
 	/* if we do x87 code generation, rewrite all the virtual instructions and registers */
-	if (cg->used_fp == fp_x87) {
+	if (cg->used_fp == fp_x87 || cg->force_sim) {
 		x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
 	}
 }
@@ -784,7 +1049,8 @@ static void ia32_codegen(void *self) {
 	ir_graph        *irg = cg->irg;
 
 	ia32_finish_irg(irg, cg);
-	be_dump(irg, "-finished", dump_ir_block_graph_sched);
+	if (cg->dump)
+		be_dump(irg, "-finished", dump_ir_block_graph_sched);
 	ia32_gen_routine(cg->isa->out, irg, cg);
 
 	cur_reg_set = NULL;
@@ -824,17 +1090,18 @@ static void *ia32_cg_init(const be_irg_t *birg) {
 	cg->isa       = isa;
 	cg->birg      = birg;
 	cg->blk_sched = NULL;
+	cg->fp_to_gp  = NULL;
+	cg->gp_to_fp  = NULL;
 	cg->fp_kind   = isa->fp_kind;
 	cg->used_fp   = fp_none;
+	cg->dump      = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
 
 	FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
 
-	/* set optimizations */
-	cg->opt.incdec    = 0;
-	cg->opt.doam      = 1;
-	cg->opt.placecnst = 1;
-	cg->opt.immops    = 1;
-	cg->opt.extbb     = 1;
+	/* copy optimizations from isa for easier access */
+	cg->opt      = isa->opt;
+	cg->arch     = isa->arch;
+	cg->opt_arch = isa->opt_arch;
 
 	/* enter it */
 	isa->cg = cg;
@@ -848,13 +1115,6 @@ static void *ia32_cg_init(const be_irg_t *birg) {
 	}
 #endif /* NDEBUG */
 
-	isa->num_codegens++;
-
-	if (isa->num_codegens > 1)
-		cg->emit_decls = 0;
-	else
-		cg->emit_decls = 1;
-
 	cur_reg_set = cg->reg_set;
 
 	ia32_irn_ops.cg = cg;
@@ -874,21 +1134,57 @@ static void *ia32_cg_init(const be_irg_t *birg) {
  *
  *****************************************************************/
 
+/**
+ * Set output modes for GCC
+ */
+static const tarval_mode_info mo_integer = {
+	TVO_DECIMAL,
+	NULL,
+	NULL,
+};
+
+/*
+* set the tarval output mode to C-semantics
+*/
+static void set_tarval_output_modes(void)
+{
+	set_tarval_mode_output_option(get_modeLs(), &mo_integer);
+	set_tarval_mode_output_option(get_modeLu(), &mo_integer);
+	set_tarval_mode_output_option(get_modeIs(), &mo_integer);
+	set_tarval_mode_output_option(get_modeIu(), &mo_integer);
+	set_tarval_mode_output_option(get_modeHs(), &mo_integer);
+	set_tarval_mode_output_option(get_modeHu(), &mo_integer);
+	set_tarval_mode_output_option(get_modeBs(), &mo_integer);
+	set_tarval_mode_output_option(get_modeBu(), &mo_integer);
+	set_tarval_mode_output_option(get_modeC(),  &mo_integer);
+	set_tarval_mode_output_option(get_modeU(),  &mo_integer);
+	set_tarval_mode_output_option(get_modeIu(), &mo_integer);
+}
+
+
 /**
  * The template that generates a new ISA object.
  * Note that this template can be changed by command line
  * arguments.
  */
 static ia32_isa_t ia32_isa_template = {
-	&ia32_isa_if,            /* isa interface implementation */
-	&ia32_gp_regs[REG_ESP],  /* stack pointer register */
-	&ia32_gp_regs[REG_EBP],  /* base pointer register */
-	-1,                      /* stack direction */
-	0,                       /* number of code generator objects so far */
+	{
+		&ia32_isa_if,            /* isa interface implementation */
+		&ia32_gp_regs[REG_ESP],  /* stack pointer register */
+		&ia32_gp_regs[REG_EBP],  /* base pointer register */
+		-1,                      /* stack direction */
+	},
 	NULL,                    /* 16bit register names */
 	NULL,                    /* 8bit register names */
 	NULL,                    /* types */
 	NULL,                    /* tv_ents */
+	(0                 |
+	IA32_OPT_INCDEC    |     /* optimize add 1, sub 1 into inc/dec               default: on  */
+	IA32_OPT_DOAM      |     /* optimize address mode                            default: on  */
+	IA32_OPT_LEA       |     /* optimize for LEAs                                default: on  */
+	IA32_OPT_PLACECNST |     /* place constants immediately before instructions, default: on  */
+	IA32_OPT_IMMOPS    |     /* operations can use immediates,                   default: on  */
+	IA32_OPT_EXTBB),         /* use extended basic block scheduling,             default: on  */
 	arch_pentium_4,          /* instruction architecture */
 	arch_pentium_4,          /* optimize for architecture */
 	fp_sse2,                 /* use sse2 unit */
@@ -909,12 +1205,23 @@ static void *ia32_init(FILE *file_handle) {
 	if (inited)
 		return NULL;
 
+	set_tarval_output_modes();
+
 	isa = xmalloc(sizeof(*isa));
 	memcpy(isa, &ia32_isa_template, sizeof(*isa));
 
 	ia32_register_init(isa);
 	ia32_create_opcodes();
-	ia32_register_copy_attr_func();
+
+	if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
+	    (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
+		/* no SSE2 for these cpu's */
+		isa->fp_kind = fp_x87;
+
+	if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
+		/* Pentium 4 don't like inc and dec instructions */
+		isa->opt &= ~IA32_OPT_INCDEC;
+	}
 
 	isa->regs_16bit = pmap_create();
 	isa->regs_8bit  = pmap_create();
@@ -927,14 +1234,14 @@ static void *ia32_init(FILE *file_handle) {
 
 	/* patch register names of x87 registers */
 	if (USE_x87(isa)) {
-	  ia32_st_regs[0].name = "st";
-	  ia32_st_regs[1].name = "st(1)";
-	  ia32_st_regs[2].name = "st(2)";
-	  ia32_st_regs[3].name = "st(3)";
-	  ia32_st_regs[4].name = "st(4)";
-	  ia32_st_regs[5].name = "st(5)";
-	  ia32_st_regs[6].name = "st(6)";
-	  ia32_st_regs[7].name = "st(7)";
+		ia32_st_regs[0].name = "st";
+		ia32_st_regs[1].name = "st(1)";
+		ia32_st_regs[2].name = "st(2)";
+		ia32_st_regs[3].name = "st(3)";
+		ia32_st_regs[4].name = "st(4)";
+		ia32_st_regs[5].name = "st(5)";
+		ia32_st_regs[6].name = "st(6)";
+		ia32_st_regs[7].name = "st(7)";
 	}
 
 #ifndef NDEBUG
@@ -943,6 +1250,8 @@ static void *ia32_init(FILE *file_handle) {
 	isa->name_obst_size = 0;
 #endif /* NDEBUG */
 
+	ia32_handle_intrinsics();
+	ia32_switch_section(NULL, NO_SECTION);
 	fprintf(isa->out, "\t.intel_syntax\n");
 
 	inited = 1;
@@ -979,22 +1288,24 @@ static void ia32_done(void *self) {
  * Return the number of register classes for this architecture.
  * We report always these:
  *  - the general purpose registers
- *  - the floating point register set (depending on the unit used for FP)
- *  - MMX/SSE registers (currently not supported)
+ *  - the SSE floating point register set
+ *  - the virtual floating point registers
  */
 static int ia32_get_n_reg_class(const void *self) {
-	return 2;
+	return 3;
 }
 
 /**
  * Return the register class for index i.
  */
 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
-	const ia32_isa_t *isa = self;
-	assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
+	assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
 	if (i == 0)
 		return &ia32_reg_classes[CLASS_ia32_gp];
-	return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
+	else if (i == 1)
+		return &ia32_reg_classes[CLASS_ia32_xmm];
+	else
+		return &ia32_reg_classes[CLASS_ia32_vfp];
 }
 
 /**
@@ -1031,9 +1342,11 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_cal
 	const arch_register_t *reg;
 	be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
 
+	unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
+
 	/* set abi flags for calls */
 	call_flags.bits.left_to_right         = 0;  /* always last arg first on stack */
-	call_flags.bits.store_args_sequential = 0;  /* use stores instead of push */
+	call_flags.bits.store_args_sequential = use_push;
 	/* call_flags.bits.try_omit_fp                 not changed: can handle both settings */
 	call_flags.bits.fp_free               = 0;  /* the frame pointer is fixed in IA32 */
 	call_flags.bits.call_has_imm          = 1;  /* IA32 calls can have immediate address */
@@ -1120,7 +1433,7 @@ const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
 }
 
 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
-	return is_ia32_irn(irn);
+	return is_ia32_irn(irn) ? 1 : -1;
 }
 
 /**
@@ -1154,6 +1467,32 @@ static int ia32_get_reg_class_alignment(const void *self, const arch_register_cl
 	return bytes;
 }
 
+static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
+
+/**
+ * Returns the libFirm configuration parameter for this backend.
+ */
+static const backend_params *ia32_get_libfirm_params(void) {
+	static const arch_dep_params_t ad = {
+		1, /* also use subs */
+		4, /* maximum shifts */
+		31, /* maximum shift amount */
+
+		1, /* allow Mulhs */
+		1, /* allow Mulus */
+		32  /* Mulh allowed up to 32 bit */
+	};
+	static backend_params p = {
+		NULL,  /* no additional opcodes */
+		NULL,  /* will be set later */
+		1,     /* need dword lowering */
+		ia32_create_intrinsic_fkt,
+		&intrinsic_env,  /* context for ia32_create_intrinsic_fkt */
+	};
+
+	p.dep_param = &ad;
+	return &p;
+}
 #ifdef WITH_LIBCORE
 
 /* instruction set architectures. */
@@ -1199,10 +1538,26 @@ static lc_opt_enum_int_var_t fp_unit_var = {
 	&ia32_isa_template.fp_kind, fp_unit_items
 };
 
+static const lc_opt_enum_int_items_t gas_items[] = {
+	{ "linux",   ASM_LINUX_GAS },
+	{ "mingw",   ASM_MINGW_GAS },
+	{ NULL,      0 }
+};
+
+static lc_opt_enum_int_var_t gas_var = {
+	(int *)&asm_flavour, gas_items
+};
+
 static const lc_opt_table_entry_t ia32_options[] = {
-	LC_OPT_ENT_ENUM_INT("arch",   "select the instruction architecture", &arch_var),
-	LC_OPT_ENT_ENUM_INT("opt",    "optimize for instruction architecture", &opt_arch_var),
-	LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
+	LC_OPT_ENT_ENUM_INT("arch",      "select the instruction architecture", &arch_var),
+	LC_OPT_ENT_ENUM_INT("opt",       "optimize for instruction architecture", &opt_arch_var),
+	LC_OPT_ENT_ENUM_INT("fpunit",    "select the floating point unit", &fp_unit_var),
+	LC_OPT_ENT_NEGBIT("noaddrmode",  "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
+	LC_OPT_ENT_NEGBIT("nolea",       "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
+	LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
+	LC_OPT_ENT_NEGBIT("noimmop",     "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
+	LC_OPT_ENT_NEGBIT("noextbb",     "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
+	LC_OPT_ENT_ENUM_INT("gasmode",   "set the GAS compatibility mode", &gas_var),
 	{ NULL }
 };
 
@@ -1214,6 +1569,13 @@ static const lc_opt_table_entry_t ia32_options[] = {
  * ia32-arch=arch    create instruction for arch
  * ia32-opt=arch     optimize for run on arch
  * ia32-fpunit=unit  select floating point unit (x87 or SSE2)
+ * ia32-incdec       optimize for inc/dec
+ * ia32-noaddrmode   do not use address mode
+ * ia32-nolea        do not optimize for LEAs
+ * ia32-noplacecnst  do not place constants,
+ * ia32-noimmop      no operations with immediates
+ * ia32-noextbb      do not use extended basic block scheduling
+ * ia32-gasmode      set the GAS compatibility mode
  */
 static void ia32_register_options(lc_opt_entry_t *ent)
 {
@@ -1233,6 +1595,7 @@ const arch_isa_if_t ia32_isa_if = {
 	ia32_get_code_generator_if,
 	ia32_get_list_sched_selector,
 	ia32_get_reg_class_alignment,
+	ia32_get_libfirm_params,
 #ifdef WITH_LIBCORE
 	ia32_register_options
 #endif