X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fia32%2Fbearch_ia32.c;h=1db15bf5b0a66ff46c95b909ebf5f9d9d55b755b;hb=577e990a5c85673d69ff5eee46d438be2bf50f44;hp=7d9cf66b6e5ad6327a03639dcd9974f8e8d00027;hpb=fdef2b39113f0615d0e715a884be2833f05b8ee5;p=libfirm diff --git a/ir/be/ia32/bearch_ia32.c b/ir/be/ia32/bearch_ia32.c index 7d9cf66b6..1db15bf5b 100644 --- a/ir/be/ia32/bearch_ia32.c +++ b/ir/be/ia32/bearch_ia32.c @@ -39,11 +39,11 @@ #include "irprintf.h" #include "iredges_t.h" #include "ircons.h" +#include "irflag.h" #include "irgmod.h" #include "irgopt.h" #include "irbitset.h" #include "irgopt.h" -#include "irdump_grgen.h" #include "pdeq.h" #include "pset.h" #include "debug.h" @@ -76,6 +76,7 @@ #include "ia32_new_nodes.h" #include "gen_ia32_regalloc_if.h" #include "gen_ia32_machine.h" +#include "ia32_common_transform.h" #include "ia32_transform.h" #include "ia32_emitter.h" #include "ia32_map_regs.h" @@ -210,14 +211,12 @@ ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) { * If the node returns a tuple (mode_T) then the proj's * will be asked for this information. */ -static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, - const ir_node *node, +static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node, int pos) { ir_mode *mode = get_irn_mode(node); long node_pos; - (void)self; if (mode == mode_X || is_Block(node)) { return arch_no_register_req; } @@ -253,11 +252,9 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, return arch_no_register_req; } -static void ia32_set_irn_reg(const void *self, ir_node *irn, - const arch_register_t *reg) +static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg) { int pos = 0; - (void) self; if (get_irn_mode(irn) == mode_X) { return; @@ -278,12 +275,10 @@ static void ia32_set_irn_reg(const void *self, ir_node *irn, } } -static const arch_register_t *ia32_get_irn_reg(const void *self, - const ir_node *irn) +static const arch_register_t *ia32_get_irn_reg(const ir_node *irn) { int pos = 0; const arch_register_t *reg = NULL; - (void) self; if (is_Proj(irn)) { @@ -307,9 +302,8 @@ static const arch_register_t *ia32_get_irn_reg(const void *self, return reg; } -static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) { +static arch_irn_class_t ia32_classify(const ir_node *irn) { arch_irn_class_t classification = arch_irn_class_normal; - (void) self; irn = skip_Proj_const(irn); @@ -331,9 +325,8 @@ static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) { return classification; } -static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) { +static arch_irn_flags_t ia32_get_flags(const ir_node *irn) { arch_irn_flags_t flags = arch_irn_flags_none; - (void) self; if (is_Unknown(irn)) return arch_irn_flags_ignore; @@ -360,30 +353,26 @@ static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) { */ typedef struct { be_abi_call_flags_bits_t flags; /**< The call flags. */ - const arch_isa_t *isa; /**< The ISA handle. */ const arch_env_t *aenv; /**< The architecture environment. */ ir_graph *irg; /**< The associated graph. */ } ia32_abi_env_t; -static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) { - (void) self; +static ir_entity *ia32_get_frame_entity(const ir_node *irn) { return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL; } -static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) { - (void) self; +static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) { set_ia32_frame_ent(irn, ent); } -static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) +static void ia32_set_frame_offset(ir_node *irn, int bias) { - const ia32_irn_ops_t *ops = self; - if (get_ia32_frame_ent(irn) == NULL) return; if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) { - int omit_fp = be_abi_omit_fp(ops->cg->birg->abi); + ia32_code_gen_t *cg = ia32_current_cg; + int omit_fp = be_abi_omit_fp(cg->birg->abi); if (omit_fp) { /* Pop nodes modify the stack pointer before calculating the * destination address, so fix this here @@ -394,10 +383,8 @@ static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) add_ia32_am_offs_int(irn, bias); } -static int ia32_get_sp_bias(const void *self, const ir_node *node) +static int ia32_get_sp_bias(const ir_node *node) { - (void) self; - if (is_ia32_Push(node)) return 4; @@ -417,7 +404,7 @@ static void ia32_abi_dont_save_regs(void *self, pset *s) { ia32_abi_env_t *env = self; if(env->flags.try_omit_fp) - pset_insert_ptr(s, env->isa->bp); + pset_insert_ptr(s, env->aenv->bp); } /** @@ -433,48 +420,49 @@ static void ia32_abi_dont_save_regs(void *self, pset *s) */ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map) { - ia32_abi_env_t *env = self; - const ia32_isa_t *isa = (ia32_isa_t *)env->isa; - ia32_code_gen_t *cg = isa->cg; + ia32_abi_env_t *env = self; + ia32_code_gen_t *cg = ia32_current_cg; + const arch_env_t *arch_env = env->aenv; if (! env->flags.try_omit_fp) { - ir_node *bl = get_irg_start_block(env->irg); - ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp); - ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp); - ir_node *noreg = ia32_new_NoReg_gp(cg); - ir_node *push; + ir_graph *irg =env->irg; + ir_node *bl = get_irg_start_block(irg); + ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp); + ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp); + ir_node *noreg = ia32_new_NoReg_gp(cg); + ir_node *push; /* ALL nodes representing bp must be set to ignore. */ be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore); /* push ebp */ - push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_bp, curr_sp); - curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack); - *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M); + push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp); + curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack); + *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M); /* the push must have SP out register */ - arch_set_irn_register(env->aenv, curr_sp, env->isa->sp); + arch_set_irn_register(arch_env, curr_sp, arch_env->sp); set_ia32_flags(push, arch_irn_flags_ignore); /* move esp to ebp */ - curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp); - be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp); - arch_set_irn_register(env->aenv, curr_bp, env->isa->bp); + curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp); + be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp); + arch_set_irn_register(arch_env, curr_bp, arch_env->bp); be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore); /* beware: the copy must be done before any other sp use */ - curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp)); - be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp); - arch_set_irn_register(env->aenv, curr_sp, env->isa->sp); + curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp)); + be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp); + arch_set_irn_register(arch_env, curr_sp, arch_env->sp); be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore); - be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp); - be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp); + be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp); + be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp); - return env->isa->bp; + return arch_env->bp; } - return env->isa->sp; + return arch_env->sp; } /** @@ -489,17 +477,17 @@ static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap */ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) { - ia32_abi_env_t *env = self; - ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp); - ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp); + ia32_abi_env_t *env = self; + const arch_env_t *arch_env = env->aenv; + ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp); + ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp); + ir_graph *irg = env->irg; if (env->flags.try_omit_fp) { /* simply remove the stack frame here */ - curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0); - add_irn_dep(curr_sp, *mem); + curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0); } else { - ir_mode *mode_bp = env->isa->bp->reg_class->mode; - ir_graph *irg = current_ir_graph; + ir_mode *mode_bp = arch_env->bp->reg_class->mode; if (ia32_cg_config.use_leave) { ir_node *leave; @@ -514,11 +502,11 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ /* the old SP is not needed anymore (kill the proj) */ assert(is_Proj(curr_sp)); - be_kill_node(curr_sp); + kill_node(curr_sp); /* copy ebp to esp */ curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp); - arch_set_irn_register(env->aenv, curr_sp, env->isa->sp); + arch_set_irn_register(arch_env, curr_sp, arch_env->sp); be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore); /* pop ebp */ @@ -529,12 +517,12 @@ static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_ *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M); } - arch_set_irn_register(env->aenv, curr_sp, env->isa->sp); - arch_set_irn_register(env->aenv, curr_bp, env->isa->bp); + arch_set_irn_register(arch_env, curr_sp, arch_env->sp); + arch_set_irn_register(arch_env, curr_bp, arch_env->bp); } - be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp); - be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp); + be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp); + be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp); } /** @@ -551,7 +539,6 @@ static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir env->flags = fl.bits; env->irg = irg; env->aenv = aenv; - env->isa = aenv->isa; return env; } @@ -613,11 +600,10 @@ static ir_type *ia32_abi_get_between_type(void *self) * * @return The estimated cycle count for this operation */ -static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn) +static int ia32_get_op_estimated_cost(const ir_node *irn) { int cost; ia32_op_type_t op_tp; - (void) self; if (is_Proj(irn)) return 0; @@ -643,9 +629,10 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn) (we assume they are in cache), other memory operations cost 20 cycles. */ - if(is_ia32_use_frame(irn) || - (is_ia32_NoReg_GP(get_irn_n(irn, 0)) && - is_ia32_NoReg_GP(get_irn_n(irn, 1)))) { + if (is_ia32_use_frame(irn) || ( + is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) && + is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index)) + )) { cost += 5; } else { cost += 20; @@ -664,13 +651,12 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn) * @param obstack The obstack to use for allocation of the returned nodes array * @return The inverse operation or NULL if operation invertible */ -static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) { +static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) { ir_graph *irg; ir_mode *mode; ir_mode *irn_mode; ir_node *block, *noreg, *nomem; dbg_info *dbg; - (void) self; /* we cannot invert non-ia32 irns */ if (! is_ia32_irn(irn)) @@ -819,11 +805,10 @@ static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spil * @param i The operands position * @return Non-Zero if operand can be loaded */ -static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) { +static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) { ir_node *op = get_irn_n(irn, i); const ir_mode *mode = get_irn_mode(op); const ir_mode *spillmode = get_spill_mode(op); - (void) self; if ( (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */ @@ -851,25 +836,34 @@ static int ia32_possible_memory_operand(const void *self, const ir_node *irn, un return 1; } -static void ia32_perform_memory_operand(const void *self, ir_node *irn, - ir_node *spill, unsigned int i) +static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill, + unsigned int i) { - const ia32_irn_ops_t *ops = self; + ir_mode *load_mode; + ir_mode *dest_op_mode; - assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change"); + ia32_code_gen_t *cg = ia32_current_cg; + + assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change"); if (i == n_ia32_binary_left) { ia32_swap_left_right(irn); } set_ia32_op_type(irn, ia32_AddrModeS); - set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i))); + + load_mode = get_irn_mode(get_irn_n(irn, i)); + dest_op_mode = get_ia32_ls_mode(irn); + if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) { + set_ia32_ls_mode(irn, load_mode); + } set_ia32_use_frame(irn); set_ia32_need_stackent(irn); set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn))); - set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(ops->cg, irn, n_ia32_binary_right)); + set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right)); set_irn_n(irn, n_ia32_mem, spill); + set_ia32_is_reload(irn); /* immediates are only allowed on the right side */ if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) { @@ -888,7 +882,7 @@ static const be_abi_callbacks_t ia32_abi_callbacks = { /* fill register allocator interface */ -static const arch_irn_ops_if_t ia32_irn_ops_if = { +static const arch_irn_ops_t ia32_irn_ops = { ia32_get_irn_reg_req, ia32_set_irn_reg, ia32_get_irn_reg, @@ -904,13 +898,6 @@ static const arch_irn_ops_if_t ia32_irn_ops_if = { ia32_perform_memory_operand, }; -static ia32_irn_ops_t ia32_irn_ops = { - &ia32_irn_ops_if, - NULL -}; - - - /************************************************** * _ _ __ * | | (_)/ _| @@ -949,6 +936,8 @@ static void ia32_before_abi(void *self) { } } +transformer_t be_transformer = TRANSFORMER_DEFAULT; + /** * Transforms the standard firm graph into * an ia32 firm graph @@ -956,7 +945,7 @@ static void ia32_before_abi(void *self) { static void ia32_prepare_graph(void *self) { ia32_code_gen_t *cg = self; - /* do local optimisations */ + /* do local optimizations */ optimize_graph_df(cg->irg); /* TODO: we often have dead code reachable through out-edges here. So for @@ -970,18 +959,30 @@ static void ia32_prepare_graph(void *self) { if (cg->dump) be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched); + switch (be_transformer) { + case TRANSFORMER_DEFAULT: + /* transform remaining nodes into assembler instructions */ + ia32_transform_graph(cg); + break; + #ifdef FIRM_GRGEN_BE - /* transform nodes into assembler instructions by PBQP magic */ - ia32_transform_graph_by_pbqp(cg); -#endif + case TRANSFORMER_PBQP: + // disable CSE, because of two-step node-construction + set_opt_cse(0); - if (cg->dump) - be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched); + /* transform nodes into assembler instructions by PBQP magic */ + ia32_transform_graph_by_pbqp(cg); - /* transform remaining nodes into assembler instructions */ - ia32_transform_graph(cg); + if (cg->dump) + be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched); + set_opt_cse(1); + break; +#endif + + default: panic("invalid transformer"); + } - /* do local optimisations (mainly CSE) */ + /* do local optimizations (mainly CSE) */ optimize_graph_df(cg->irg); if (cg->dump) @@ -1060,9 +1061,9 @@ static void turn_back_am(ir_node *node) mem_proj = NULL; foreach_out_edge(node, edge) { ir_node *out = get_edge_src_irn(edge); - if(get_Proj_proj(out) == pn_ia32_mem) { + if(get_irn_mode(out) == mode_M) { + assert(mem_proj == NULL); mem_proj = out; - break; } } @@ -1092,7 +1093,9 @@ static ir_node *flags_remat(ir_node *node, ir_node *after) type = get_ia32_op_type(node); switch (type) { - case ia32_AddrModeS: turn_back_am(node); break; + case ia32_AddrModeS: + turn_back_am(node); + break; case ia32_AddrModeD: /* TODO implement this later... */ @@ -1431,7 +1434,11 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) if (is_ia32_need_stackent(node) || is_ia32_Load(node)) { const ir_mode *mode = get_ia32_ls_mode(node); const ia32_attr_t *attr = get_ia32_attr_const(node); - int align = get_mode_size_bytes(mode); + int align; + + if (is_ia32_is_reload(node)) { + mode = get_spill_mode_mode(mode); + } if(attr->data.need_64bit_stackent) { mode = mode_Ls; @@ -1439,6 +1446,7 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) if(attr->data.need_32bit_stackent) { mode = mode_Is; } + align = get_mode_size_bytes(mode); be_node_needs_frame_entity(env, node, mode, align); } else if (is_ia32_vfild(node) || is_ia32_xLoad(node) || is_ia32_vfld(node)) { @@ -1565,14 +1573,14 @@ static const arch_code_generator_if_t ia32_code_gen_if = { * Initializes a IA32 code generator. */ static void *ia32_cg_init(be_irg_t *birg) { - ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env.isa; + ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env; ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg)); cg->impl = &ia32_code_gen_if; cg->irg = birg->irg; cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024); - cg->arch_env = &birg->main_env->arch_env; cg->isa = isa; + cg->arch_env = birg->main_env->arch_env; cg->birg = birg; cg->blk_sched = NULL; cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; @@ -1595,8 +1603,6 @@ static void *ia32_cg_init(be_irg_t *birg) { cur_reg_set = cg->reg_set; - ia32_irn_ops.cg = cg; - assert(ia32_current_cg == NULL); ia32_current_cg = cg; @@ -1652,7 +1658,7 @@ static ia32_isa_t ia32_isa_template = { &ia32_gp_regs[REG_ESP], /* stack pointer register */ &ia32_gp_regs[REG_EBP], /* base pointer register */ -1, /* stack direction */ - 16, /* stack alignment */ + 4, /* power of two stack alignment, 2^4 == 16 */ NULL, /* main environment */ 7, /* costs for a spill instruction */ 5, /* costs for a reload instruction */ @@ -1669,12 +1675,60 @@ static ia32_isa_t ia32_isa_template = { #endif }; +static void init_asm_constraints(void) +{ + be_init_default_asm_constraint_flags(); + + asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER; + asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE; + asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE; + + /* no support for autodecrement/autoincrement */ + asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + /* no float consts */ + asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + /* makes no sense on x86 */ + asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + /* no support for sse consts yet */ + asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + /* no support for x87 consts yet */ + asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + /* no support for mmx registers yet */ + asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + /* not available in 32bit mode */ + asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; + + /* no code yet to determine register class needed... */ + asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT; +} + /** * Initializes the backend ISA. */ -static void *ia32_init(FILE *file_handle) { +static arch_env_t *ia32_init(FILE *file_handle) { static int inited = 0; ia32_isa_t *isa; + int i, n; if (inited) return NULL; @@ -1690,7 +1744,7 @@ static void *ia32_init(FILE *file_handle) { } ia32_register_init(); - ia32_create_opcodes(); + ia32_create_opcodes(&ia32_irn_ops); be_emit_init(file_handle); isa->regs_16bit = pmap_create(); @@ -1713,6 +1767,14 @@ static void *ia32_init(FILE *file_handle) { intrinsic_env.isa = isa; ia32_handle_intrinsics(); + /* emit asm includes */ + n = get_irp_n_asms(); + for (i = 0; i < n; ++i) { + be_emit_cstring("#APP\n"); + be_emit_ident(get_irp_asm(i)); + be_emit_cstring("\n#NO_APP\n"); + } + /* needed for the debug support */ be_gas_emit_switch_section(GAS_SECTION_TEXT); be_emit_cstring(".Ltext0:\n"); @@ -1724,7 +1786,7 @@ static void *ia32_init(FILE *file_handle) { */ inc_master_type_visited(); - return isa; + return &isa->arch_env; } @@ -1736,7 +1798,7 @@ static void ia32_done(void *self) { ia32_isa_t *isa = self; /* emit now all global declarations */ - be_gas_emit_decls(isa->arch_isa.main_env, 1); + be_gas_emit_decls(isa->arch_env.main_env, 1); pmap_destroy(isa->regs_16bit); pmap_destroy(isa->regs_8bit); @@ -1809,7 +1871,9 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, ir_mode *mode; unsigned cc; int n, i, regnum; + int pop_amount = 0; be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi); + (void) self; /* set abi flags for calls */ @@ -1817,7 +1881,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, call_flags.bits.store_args_sequential = 0; /* call_flags.bits.try_omit_fp not changed: can handle both settings */ call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */ - call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */ + call_flags.bits.call_has_imm = 1; /* No call immediates, we handle this by ourselves */ /* set parameter passing style */ be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks); @@ -1827,8 +1891,8 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, cc = cc_cdecl_set; } else { cc = get_method_calling_convention(method_type); - if (get_method_additional_properties(method_type) & mtp_property_private - && (ia32_cg_config.optimize_cc)) { + if (get_method_additional_properties(method_type) & mtp_property_private && + ia32_cg_config.optimize_cc) { /* set the calling conventions to register parameter */ cc = (cc & ~cc_bits) | cc_reg_param; } @@ -1837,7 +1901,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, /* we have to pop the shadow parameter ourself for compound calls */ if( (get_method_calling_convention(method_type) & cc_compound_ret) && !(cc & cc_reg_param)) { - be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data)); + pop_amount += get_mode_size_bytes(mode_P_data); } n = get_method_n_params(method_type); @@ -1857,11 +1921,23 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes. * movl has a shorter opcode than mov[sz][bw]l */ ir_mode *load_mode = mode; - if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu; + + if (mode != NULL) { + unsigned size = get_mode_size_bytes(mode); + + if (cc & cc_callee_clear_stk) { + pop_amount += (size + 3U) & ~3U; + } + + if (size < 4) load_mode = mode_Iu; + } + be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0); } } + be_abi_call_set_pop(abi, pop_amount); + /* set return registers */ n = get_method_n_ress(method_type); @@ -1895,19 +1971,6 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type, } } - -static const void *ia32_get_irn_ops(const ir_node *irn) -{ - (void) irn; - return &ia32_irn_ops; -} - -arch_get_irn_ops_t *ia32_get_irn_handler(const void *self) -{ - (void) self; - return &ia32_get_irn_ops; -} - int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) { (void) block_env; @@ -1938,8 +2001,8 @@ static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) * Returns the estimated execution time of an ia32 irn. */ static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) { - const arch_env_t *arch_env = env; - return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1; + (void) env; + return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1; } list_sched_selector_t ia32_sched_selector; @@ -2060,31 +2123,30 @@ static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) */ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) { - ir_node *phi, *left; + ir_node *phi; ir_node *cmp = NULL; - ir_mode *cmp_mode; - if (ia32_cg_config.use_cmov) { - /* we can't handle psis with 64bit compares yet */ - if (is_Proj(sel)) { - cmp = get_Proj_pred(sel); - if (is_Cmp(cmp)) { - left = get_Cmp_left(cmp); - cmp_mode = get_irn_mode(left); - if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) - return 0; - } else { - cmp = NULL; - } + /* we can't handle psis with 64bit compares yet */ + if (is_Proj(sel)) { + cmp = get_Proj_pred(sel); + if (is_Cmp(cmp)) { + ir_node *left = get_Cmp_left(cmp); + ir_mode *cmp_mode = get_irn_mode(left); + if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) + return 0; + } else { + cmp = NULL; } + } + if (ia32_cg_config.use_cmov) { if (ia32_cg_config.use_sse2 && cmp != NULL) { pn_Cmp pn = get_Proj_proj(sel); ir_node *cl = get_Cmp_left(cmp); ir_node *cr = get_Cmp_right(cmp); /* check the Phi nodes: no 64bit and no floating point cmov */ - for (phi = phi_list; phi; phi = get_irn_link(phi)) { + for (phi = phi_list; phi; phi = get_Phi_next(phi)) { ir_mode *mode = get_irn_mode(phi); if (mode_is_float(mode)) { @@ -2111,7 +2173,7 @@ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) } } else { /* check the Phi nodes: no 64bit and no floating point cmov */ - for (phi = phi_list; phi; phi = get_irn_link(phi)) { + for (phi = phi_list; phi; phi = get_Phi_next(phi)) { ir_mode *mode = get_irn_mode(phi); if (mode_is_float(mode) || get_mode_size_bits(mode) > 32) @@ -2125,21 +2187,15 @@ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) pn_Cmp pn; /* No cmov, only some special cases */ - if (! is_Proj(sel)) - return 0; - cmp = get_Proj_pred(sel); - if (! is_Cmp(cmp)) + if (cmp == NULL) return 0; - left = get_Cmp_left(cmp); - cmp_mode = get_irn_mode(left); - /* Now some supported cases here */ pn = get_Proj_proj(sel); cl = get_Cmp_left(cmp); cr = get_Cmp_right(cmp); - for (phi = phi_list; phi; phi = get_irn_link(phi)) { + for (phi = phi_list; phi; phi = get_Phi_next(phi)) { ir_mode *mode = get_irn_mode(phi); int res = 0; ir_node *t, *f; @@ -2195,6 +2251,23 @@ static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) return 0; } +static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c) +{ + (void) self; + (void) c; + + /* we already added all our simple flags to the flags modifier list in + * init, so this flag we don't know. */ + return ASM_CONSTRAINT_FLAG_INVALID; +} + +static int ia32_is_valid_clobber(const void *self, const char *clobber) +{ + (void) self; + + return ia32_get_clobber_register(clobber) != NULL; +} + /** * Returns the libFirm configuration parameter for this backend. */ @@ -2216,15 +2289,21 @@ static const backend_params *ia32_get_libfirm_params(void) { static backend_params p = { 1, /* need dword lowering */ 1, /* support inline assembly */ + 0, /* no immediate floating point mode. */ NULL, /* no additional opcodes */ NULL, /* will be set later */ ia32_create_intrinsic_fkt, &intrinsic_env, /* context for ia32_create_intrinsic_fkt */ NULL, /* will be set below */ + NULL /* will be set below */ }; ia32_setup_cg_config(); + /* doesn't really belong here, but this is the earliest place the backend + * is called... */ + init_asm_constraints(); + p.dep_param = &ad; p.if_conv_info = &ifconv; return &p; @@ -2242,10 +2321,23 @@ static lc_opt_enum_int_var_t gas_var = { (int*) &be_gas_flavour, gas_items }; +static const lc_opt_enum_int_items_t transformer_items[] = { + { "default", TRANSFORMER_DEFAULT }, +#ifdef FIRM_GRGEN_BE + { "pbqp", TRANSFORMER_PBQP }, +#endif + { NULL, 0 } +}; + +static lc_opt_enum_int_var_t transformer_var = { + (int*)&be_transformer, transformer_items +}; + static const lc_opt_table_entry_t ia32_options[] = { LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var), - LC_OPT_ENT_INT("stackalign", "set stack alignment for calls", - &ia32_isa_template.arch_isa.stack_alignment), + LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var), + LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls", + &ia32_isa_template.arch_env.stack_alignment), LC_OPT_LAST }; @@ -2256,7 +2348,6 @@ const arch_isa_if_t ia32_isa_if = { ia32_get_reg_class, ia32_get_reg_class_for_mode, ia32_get_call_abi, - ia32_get_irn_handler, ia32_get_code_generator_if, ia32_get_list_sched_selector, ia32_get_ilp_sched_selector, @@ -2265,6 +2356,8 @@ const arch_isa_if_t ia32_isa_if = { ia32_get_allowed_execution_units, ia32_get_machine, ia32_get_irg_list, + ia32_parse_asm_constraint, + ia32_is_valid_clobber }; void ia32_init_emitter(void);