X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fbespill.c;h=7dd59cd999f95f7f2aade6b37eceaee5ee4e852a;hb=30369d28b8fabe4f66cee12f42ee475d9444cf9e;hp=b38967ad6abe06b41219ec158c965de02fb80428;hpb=ce6161a7e42a48f7422b7babcc64d8ace18e2687;p=libfirm diff --git a/ir/be/bespill.c b/ir/be/bespill.c index b38967ad6..7dd59cd99 100644 --- a/ir/be/bespill.c +++ b/ir/be/bespill.c @@ -22,7 +22,6 @@ * @brief Spill module selection; Preparation steps * @author Matthias Braun * @date 29.09.2005 - * @version $Id$ */ #include "config.h" @@ -64,18 +63,19 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) unsigned *tmp = NULL; unsigned *def_constr = NULL; int arity = get_irn_arity(node); + ir_node *def; int i, i2; /* Insert a copy for constraint inputs attached to a value which can't - * fullfil the constraint + * fulfill the constraint * (typical example: stack pointer as input to copyb) * TODO: This really just checks precolored registers at the moment and * ignores the general case of not matching in/out constraints */ for (i = 0; i < arity; ++i) { ir_node *op = get_irn_n(node, i); - const arch_register_req_t *req = arch_get_register_req(node, i); + const arch_register_req_t *req = arch_get_irn_register_req_in(node, i); const arch_register_t *reg; ir_node *copy; @@ -87,8 +87,8 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) /* precolored with an ignore register (which is not a joker like unknown/noreg) */ - if (arch_register_type_is(reg, joker) - || rbitset_is_set(birg->allocatable_regs, reg->global_index)) + if ((reg->type & arch_register_type_joker) || + rbitset_is_set(birg->allocatable_regs, reg->global_index)) continue; if (! (req->type & arch_register_req_type_limited)) @@ -96,7 +96,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) if (rbitset_is_set(req->limited, reg->index)) continue; - copy = be_new_Copy(cls, block, op); + copy = be_new_Copy(block, op); stat_ev_int("constr_copy", 1); sched_add_before(node, copy); set_irn_n(node, i, copy); @@ -110,7 +110,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) ir_node *copy; const arch_register_req_t *req; - req = arch_get_register_req(node, i); + req = arch_get_irn_register_req_in(node, i); if (req->cls != cls) continue; @@ -125,7 +125,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) ir_node *in2; const arch_register_req_t *req2; - req2 = arch_get_register_req(node, i2); + req2 = arch_get_irn_register_req_in(node, i2); if (req2->cls != cls) continue; if (! (req2->type & arch_register_req_type_limited)) @@ -140,7 +140,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) if (rbitsets_equal(req->limited, req2->limited, cls->n_regs)) continue; - copy = be_new_Copy(cls, block, in); + copy = be_new_Copy(block, in); stat_ev_int("constr_copy", 1); sched_add_before(node, copy); @@ -152,27 +152,14 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) } /* collect all registers occurring in out constraints. */ - if (get_irn_mode(node) == mode_T) { - const ir_edge_t *edge; - - foreach_out_edge(node, edge) { - ir_node *proj = get_edge_src_irn(edge); - const arch_register_req_t *req = arch_get_register_req_out(proj); - if (! (req->type & arch_register_req_type_limited)) - continue; - - if (def_constr == NULL) { - rbitset_alloca(def_constr, cls->n_regs); - } - rbitset_or(def_constr, req->limited, cls->n_regs); - } - } else { - const arch_register_req_t *req = arch_get_register_req_out(node); - if (req->type & arch_register_req_type_limited) { + be_foreach_definition(node, cls, def, + if (! (req_->type & arch_register_req_type_limited)) + continue; + if (def_constr == NULL) { rbitset_alloca(def_constr, cls->n_regs); - rbitset_or(def_constr, req->limited, cls->n_regs); } - } + rbitset_or(def_constr, req_->limited, cls->n_regs); + ); /* no output constraints => we're good */ if (def_constr == NULL) { @@ -195,7 +182,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) * 2) lives through the node. * 3) is constrained to a register occurring in out constraints. */ - req = arch_get_register_req(node, i); + req = arch_get_irn_register_req_in(node, i); if (req->cls != cls) continue; if (!(req->type & arch_register_req_type_limited)) @@ -222,7 +209,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) if (be_is_Copy(in)) continue; - copy = be_new_Copy(cls, block, in); + copy = be_new_Copy(block, in); sched_add_before(node, copy); set_irn_n(node, i, copy); DBG((dbg, LEVEL_3, "inserting constr copy %+F for %+F pos %d\n", @@ -234,7 +221,6 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node) static void pre_spill_prepare_constr_walker(ir_node *block, void *data) { be_pre_spill_env_t *env = (be_pre_spill_env_t*)data; - ir_node *node; sched_foreach(block, node) { prepare_constr_insn(env, node); } @@ -248,7 +234,7 @@ void be_pre_spill_prepare_constr(ir_graph *irg, env.irg = irg; env.cls = cls; - be_assure_liveness(irg); + be_assure_live_sets(irg); irg_block_walk_graph(irg, pre_spill_prepare_constr_walker, NULL, &env); } @@ -281,14 +267,14 @@ void be_do_spill(ir_graph *irg, const arch_register_class_t *cls) selected_spiller->spill(irg, cls); } -BE_REGISTER_MODULE_CONSTRUCTOR(be_init_spilloptions); +BE_REGISTER_MODULE_CONSTRUCTOR(be_init_spilloptions) void be_init_spilloptions(void) { lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be"); lc_opt_entry_t *spill_grp = lc_opt_get_grp(be_grp, "spill"); lc_opt_add_table(spill_grp, be_spill_options); - be_add_module_list_opt(spill_grp, "spiller", "spill algorithm", + be_add_module_list_opt(be_grp, "spiller", "spill algorithm", &spillers, (void**) &selected_spiller); FIRM_DBG_REGISTER(dbg, "firm.be.spillprepare");