X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fbechordal.c;h=a83c52a897e862deb4bcf8be5feed340206bf1eb;hb=6e3e499d6c68aee0c6a9ada6a99f16c4f6f8445b;hp=0c4334c584b764f60c089f6e0c8214d7e41c39dc;hpb=33be8f50c457cd2e6e8a4fc488248d0d47c7f491;p=libfirm

diff --git a/ir/be/bechordal.c b/ir/be/bechordal.c
index 0c4334c58..a83c52a89 100644
--- a/ir/be/bechordal.c
+++ b/ir/be/bechordal.c
@@ -26,6 +26,7 @@
 #include "list.h"
 #include "bitset.h"
 #include "iterator.h"
+#include "bipartite.h"
 
 #include "irmode_t.h"
 #include "irgraph_t.h"
@@ -43,6 +44,7 @@
 #include "belive_t.h"
 #include "benode_t.h"
 #include "bearch.h"
+#include "beirgmod.h"
 #include "beifg.h"
 
 #include "bechordal_t.h"
@@ -53,15 +55,22 @@
 
 #define NO_COLOR (-1)
 
-#undef DUMP_INTERVALS
+#define MAX(x, y) ((x) > (y) ? (x) : (y))
+#define MIN(x, y) ((x) < (y) ? (x) : (y))
+
+#define DUMP_INTERVALS
 
 typedef struct _be_chordal_alloc_env_t {
 	be_chordal_env_t *chordal_env;
 
-	bitset_t *live;				/**< A liveness bitset. */
-	bitset_t *colors;			/**< The color mask. */
-	bitset_t *in_colors;        /**< Colors used by live in values. */
-	int colors_n;               /**< The number of colors. */
+	firm_dbg_module_t *constr_dbg;  /**< Debug output for the constraint handler. */
+	pset *pre_colored;              /**< Set of precolored nodes. */
+	bitset_t *live;				    /**< A liveness bitset. */
+	bitset_t *tmp_colors;           /**< An auxiliary bitset which is as long as the number of colors in the class. */
+	bitset_t *colors;			    /**< The color mask. */
+	bitset_t *in_colors;            /**< Colors used by live in values. */
+	bitset_t *ignore_regs;          /**< A bitset of all ignore registers in the current class. */
+	int colors_n;                   /**< The number of colors. */
 } be_chordal_alloc_env_t;
 
 #include "fourcc.h"
@@ -158,93 +167,517 @@ static INLINE border_t *border_add(be_chordal_env_t *env, struct list_head *head
  */
 static INLINE int has_reg_class(const be_chordal_env_t *env, const ir_node *irn)
 {
-  return arch_irn_has_reg_class(env->main_env->arch_env, irn, -1, env->cls);
+	// return arch_irn_has_reg_class(env->main_env->arch_env, irn, -1, env->cls);
+	return arch_irn_consider_in_reg_alloc(env->birg->main_env->arch_env, env->cls, irn);
 }
 
-static border_t *handle_constraint_perm(be_chordal_alloc_env_t *alloc_env, border_t *perm_border)
+#define has_limited_constr(req, irn) \
+	(arch_get_register_req(arch_env, (req), irn, -1) && (req)->type == arch_register_req_type_limited)
+
+static int get_next_free_reg(const be_chordal_alloc_env_t *alloc_env, bitset_t *colors)
 {
-	const arch_env_t *arch_env = alloc_env->chordal_env->main_env->arch_env;
-	bitset_t *bs               = bitset_alloca(alloc_env->chordal_env->cls->n_regs);
-	ir_node *perm              = perm_border->irn;
-	int n                      = get_irn_arity(perm_border->irn);
-	int n_projs                = 0;
+	bitset_t *tmp = alloc_env->tmp_colors;
+	bitset_copy(tmp, colors);
+	bitset_or(tmp, alloc_env->ignore_regs);
+	return bitset_next_clear(tmp, 0);
+}
 
-	border_t *b, *next_border, *cnstr_border;
+typedef struct _operand_t operand_t;
 
+struct _operand_t {
+	ir_node *irn;
+	ir_node *carrier;
+	operand_t *partner;
+	bitset_t *regs;
+	int pos;
 	arch_register_req_t req;
-	ir_node *cnstr;
-	int has_cnstr = 0;
-	int i, m;
+	unsigned has_constraints : 1;
+};
+
+typedef struct {
+	operand_t *ops;
+	int n_ops;
+	int use_start;
+	ir_node *next_insn;
+	ir_node *irn;
+	unsigned in_constraints  : 1;
+	unsigned out_constraints : 1;
+	unsigned has_constraints : 1;
+	unsigned pre_colored     : 1;
+} insn_t;
+
+#define insn_n_defs(insn) ((insn)->use_start)
+#define insn_n_uses(insn) ((insn)->n_ops - (insn)->use_start)
+
+static insn_t *scan_insn(be_chordal_alloc_env_t *alloc_env, ir_node *irn, struct obstack *obst)
+{
+	const be_chordal_env_t *env = alloc_env->chordal_env;
+	const arch_env_t *arch_env  = env->birg->main_env->arch_env;
+	operand_t o;
+	insn_t *insn;
+	int i, n;
+	int pre_colored = 0;
+
+	insn = obstack_alloc(obst, sizeof(insn[0]));
+	memset(insn, 0, sizeof(insn[0]));
+
+	insn->irn       = irn;
+	insn->next_insn = sched_next(irn);
+	if(get_irn_mode(irn) == mode_T) {
+		ir_node *p;
+
+		for(p = sched_next(irn); is_Proj(p); p = sched_next(p)) {
+			if(arch_irn_consider_in_reg_alloc(arch_env, env->cls, p)) {
+				arch_get_register_req(arch_env, &o.req, p, -1);
+				o.carrier         = p;
+				o.irn             = irn;
+				o.pos             = -(get_Proj_proj(p) + 1);
+				o.partner         = NULL;
+				o.has_constraints = arch_register_req_is(&o.req, limited);
+				obstack_grow(obst, &o, sizeof(o));
+				insn->n_ops++;
+				insn->out_constraints |= o.has_constraints;
+				pre_colored += arch_get_irn_register(arch_env, p) != NULL;
+			}
+		}
+
+		insn->next_insn = p;
+	}
+
+	else if(arch_irn_consider_in_reg_alloc(arch_env, env->cls, irn)) {
+		arch_get_register_req(arch_env, &o.req, irn, -1);
+		o.carrier = irn;
+		o.irn     = irn;
+		o.pos     = -1;
+		o.partner = NULL;
+		o.has_constraints = arch_register_req_is(&o.req, limited);
+		obstack_grow(obst, &o, sizeof(o));
+		insn->n_ops++;
+		insn->out_constraints |= o.has_constraints;
+		pre_colored += arch_get_irn_register(arch_env, irn) != NULL;
+	}
+
+	insn->pre_colored = pre_colored == insn->n_ops && insn->n_ops > 0;
+	insn->use_start   = insn->n_ops;
+
+	for(i = 0, n = get_irn_arity(irn); i < n; ++i) {
+		ir_node *op = get_irn_n(irn, i);
+
+		if(arch_irn_consider_in_reg_alloc(arch_env, env->cls, op)) {
+			arch_get_register_req(arch_env, &o.req, irn, i);
+			o.carrier = op;
+			o.irn     = irn;
+			o.pos     = i;
+			o.partner = NULL;
+			o.has_constraints = arch_register_req_is(&o.req, limited);
+			obstack_grow(obst, &o, sizeof(o));
+			insn->n_ops++;
+			insn->in_constraints |= o.has_constraints;
+		}
+	}
+
+	insn->has_constraints = insn->in_constraints | insn->out_constraints;
+	insn->ops = obstack_finish(obst);
+
+	/* Compute the admissible registers bitsets. */
+	for(i = 0; i < insn->n_ops; ++i) {
+		operand_t *op = &insn->ops[i];
 
-	assert(is_Perm(perm));
+		assert(op->req.cls == env->cls);
+		op->regs   = bitset_obstack_alloc(obst, env->cls->n_regs);
+
+		if(arch_register_req_is(&op->req, limited))
+			op->req.limited(op->req.limited_env, op->regs);
+		else
+			arch_put_non_ignore_regs(env->birg->main_env->arch_env, env->cls, op->regs);
+	}
+
+	return insn;
+}
+
+static bitset_t *get_decisive_partner_regs(bitset_t *bs, const operand_t *o1, const operand_t *o2)
+{
+	bitset_t *res = bs;
+
+	if(!o1) {
+		bitset_copy(bs, o2->regs);
+		return bs;
+	}
+
+	if(!o2) {
+		bitset_copy(bs, o1->regs);
+		return bs;
+	}
+
+	assert(o1->req.cls == o2->req.cls);
+
+	if(bitset_contains(o1->regs, o2->regs))
+		bitset_copy(bs, o1->regs);
+	else if(bitset_contains(o2->regs, o1->regs))
+		bitset_copy(bs, o2->regs);
+	else
+		res = NULL;
+
+	return res;
+}
+
+static void pair_up_operands(const be_chordal_alloc_env_t *alloc_env, insn_t *insn)
+{
+	const be_chordal_env_t *env = alloc_env->chordal_env;
+
+	int n_uses         = insn_n_uses(insn);
+	int n_defs         = insn_n_defs(insn);
+	bitset_t *bs       = bitset_alloca(env->cls->n_regs);
+	bipartite_t *bp    = bipartite_new(n_defs, n_uses);
+	int *pairing       = alloca(MAX(n_defs, n_uses) * sizeof(pairing[0]));
+
+	int i, j;
 
 	/*
-	 * After the Perm, there must be a sequence of Projs
-	 * which extract the permuted values of the Perm.
-	 */
-	for(b = perm_border; is_Proj(b->irn); b = border_next(b)) {
-		assert(is_Proj(b->irn));
-		assert(b->is_def);
-		n_projs++;
+		For each out operand, try to find an in operand which can be assigned the
+		same register as the out operand.
+	*/
+	for(j = 0; j < insn->use_start; ++j) {
+		operand_t *out_op = &insn->ops[j];
+
+		/* Try to find an in operand which has ... */
+		for(i = insn->use_start; i < insn->n_ops; ++i) {
+			const operand_t *op = &insn->ops[i];
+
+			/*
+			The in operand can only be paired with a def, if the node defining the
+			operand's value does not interfere with the instruction itself. That
+			would mean, that it is live at the instruction, so no result of the instruction
+			can have the same register as the operand.
+
+			Furthermore, tow operands can be paired, if the admissible registers
+			of one are a subset of the other's. We record the operand whose constraints
+			count in the decisive array.
+			*/
+			if(!values_interfere(op->irn, op->carrier)) {
+				if(get_decisive_partner_regs(bs, out_op, op))
+					bipartite_add(bp, j, i - insn->use_start);
+			}
+		}
+	}
+
+	/* Compute the pairing. */
+	bipartite_matching(bp, pairing);
+	for(i = 0; i < insn->use_start; ++i) {
+		int p = pairing[i] + insn->use_start;
+
+		if(p >= insn->use_start) {
+			insn->ops[i].partner = &insn->ops[p];
+			insn->ops[p].partner = &insn->ops[i];
+		}
+	}
+
+	bipartite_free(bp);
+}
+
+
+static ir_node *pre_process_constraints(be_chordal_alloc_env_t *alloc_env, insn_t **the_insn)
+{
+	be_chordal_env_t *env       = alloc_env->chordal_env;
+	const arch_env_t *aenv      = env->birg->main_env->arch_env;
+	firm_dbg_module_t *dbg      = alloc_env->constr_dbg;
+	insn_t *insn                = *the_insn;
+	ir_node *bl                 = get_nodes_block(insn->irn);
+	ir_node *copy               = NULL;
+	ir_node *perm               = NULL;
+	bitset_t *out_constr        = bitset_alloca(env->cls->n_regs);
+	bitset_t *bs                = bitset_alloca(env->cls->n_regs);
+
+	int i;
+
+	assert(insn->has_constraints && "only do this for constrained nodes");
+
+	/*
+		Collect all registers that occur in output constraints.
+		This is necessary, since if the insn has one of these as an input constraint
+		and the corresponding operand interferes with the insn, the operand must
+		be copied.
+	*/
+	for(i = 0; i < insn->use_start; ++i) {
+		operand_t *op = &insn->ops[i];
+		if(op->has_constraints)
+			bitset_or(out_constr, op->regs);
 	}
 
-	cnstr_border = b;
-	next_border  = border_next(b);
-	cnstr        = b->irn;
+	/*
+		Now, figure out which input operand must be copied since it has input
+		constraints which are also output constraints.
+	*/
+	for(i = insn->use_start; i < insn->n_ops; ++i) {
+		operand_t *op = &insn->ops[i];
+		if(op->has_constraints && (values_interfere(op->carrier, insn->irn) || arch_irn_is(aenv, op->carrier, ignore))) {
+			bitset_copy(bs, op->regs);
+			bitset_and(bs, out_constr);
 
-	assert(n_projs == n && "There must be as many Projs as the Perm is wide");
+			/*
+				The operand (interfering with the node) has input constraints
+				which also occur as output constraints, so insert a copy.
+			*/
+			if(bitset_popcnt(bs) > 0) {
+				copy                 = be_new_Copy(op->req.cls, env->irg, bl, op->carrier);
+				insn->ops[i].carrier = copy;
+				sched_add_before(insn->irn, copy);
+
+				DBG((dbg, LEVEL_2, "adding copy for interfering and constrained op %+F\n", op->carrier));
+			}
+		}
+	}
 
-	/* The node after the last perm proj must be the constrained node. */
-	cnstr = b->irn;
-	for(i = -1, m = get_irn_arity(cnstr); i < m; ++i) {
-		req.type = arch_register_req_type_normal;
-		if(arch_get_register_req(arch_env, &req, cnstr, i) && req.type == arch_register_req_type_limited) {
-			has_cnstr = 1;
-			break;
+	/*
+		Make the Perm, recompute liveness and re-scan the insn since the
+		in operands are now the Projs of the Perm.
+	*/
+	perm = insert_Perm_after(aenv, env->cls, env->dom_front, sched_prev(insn->irn));
+
+	/* Registers are propagated by insert_Perm_after(). Clean them here! */
+	if(perm) {
+		const ir_edge_t *edge;
+
+		foreach_out_edge(perm, edge) {
+			ir_node *proj = get_edge_src_irn(edge);
+			arch_set_irn_register(aenv, proj, NULL);
+		}
+
+		/*
+			We also have to re-build the insn since the input operands are now the Projs of
+			the Perm. Recomputing liveness is also a good idea if a Perm is inserted, since
+			the live sets may change.
+		*/
+		be_liveness(env->irg);
+		obstack_free(&env->obst, insn);
+		*the_insn = insn = scan_insn(alloc_env, insn->irn, &env->obst);
+
+		/*
+			Copy the input constraints of the insn to the Perm as output
+			constraints. Succeeding phases (coalescing will need that).
+		*/
+		for(i = insn->use_start; i < insn->n_ops; ++i) {
+			operand_t *op = &insn->ops[i];
+			ir_node *proj = op->carrier;
+			/*
+				Note that the predecessor must not be a Proj of the Perm,
+				since ignore-nodes are not Perm'ed.
+			*/
+			if(op->has_constraints &&  is_Proj(proj) && get_Proj_pred(proj) == perm) {
+				be_set_constr_limited(perm, BE_OUT_POS(get_Proj_proj(proj)), &op->req);
+			}
 		}
 	}
 
-	assert(has_cnstr && "The node must have a register constraint");
+	return perm;
+}
+
+static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env, ir_node *irn, int *silent)
+{
+	be_chordal_env_t *env  = alloc_env->chordal_env;
+	void *base             = obstack_base(&env->obst);
+	insn_t *insn           = scan_insn(alloc_env, irn, &env->obst);
+	ir_node *res           = insn->next_insn;
+	int be_silent          = *silent;
+
+	if(insn->pre_colored) {
+		int i;
+		for(i = 0; i < insn->use_start; ++i)
+			pset_insert_ptr(alloc_env->pre_colored, insn->ops[i].carrier);
+	}
 
 	/*
-	 * Consider the code in beconstrperm.c
-	 * We turned each input constraint of a node into an output
-	 * constraint of the Perm's Proj. So we only have to
-	 * consider output constraints here.
-	 */
-	for(b = perm_border; b != next_border; b = border_next(b)) {
-		ir_node *irn = b->irn;
+		If the current node is a barrier toggle the silent flag.
+		If we are in the start block, we are ought to be silent at the beginning,
+		so the toggling activates the constraint handling but skips the barrier.
+		If we are in the end block we handle the in requirements of the barrier
+		and set the rest to silent.
+	*/
+	if(be_is_Barrier(irn))
+		*silent = !*silent;
+
+	if(be_silent)
+		goto end;
+
+	/*
+		Perms inserted before the constraint handling phase are considered to be
+		correctly precolored. These Perms arise during the ABI handling phase.
+	*/
+	if(insn->has_constraints) {
+		firm_dbg_module_t *dbg = alloc_env->constr_dbg;
+		const arch_env_t *aenv = env->birg->main_env->arch_env;
+		int n_regs             = env->cls->n_regs;
+		bitset_t *bs           = bitset_alloca(n_regs);
+		ir_node **alloc_nodes  = alloca(n_regs * sizeof(alloc_nodes[0]));
+		bipartite_t *bp        = bipartite_new(n_regs, n_regs);
+		int *assignment        = alloca(n_regs * sizeof(assignment[0]));
+		pmap *partners         = pmap_create();
+
+		int i, n_alloc;
+		long col;
+		const ir_edge_t *edge;
+		ir_node *perm = NULL;
+
+		/*
+			prepare the constraint handling of this node.
+			Perms are constructed and Copies are created for constrained values
+			interfering with the instruction.
+		*/
+		perm = pre_process_constraints(alloc_env, &insn);
+
+		/* find suitable in operands to the out operands of the node. */
+		pair_up_operands(alloc_env, insn);
+
+		/*
+			look at the in/out operands and add each operand (and its possible partner)
+			to a bipartite graph (left: nodes with partners, right: admissible colors).
+		*/
+		for(i = 0, n_alloc = 0; i < insn->n_ops; ++i) {
+			operand_t *op = &insn->ops[i];
+
+			/*
+				If the operand has no partner or the partner has not been marked
+				for allocation, determine the admissible registers and mark it
+				for allocation by associating the node and its partner with the
+				set of admissible registers via a bipartite graph.
+			*/
+			if(!op->partner || !pmap_contains(partners, op->partner->carrier)) {
 
-		req.type = arch_register_req_type_normal;
-		if(arch_get_register_req(arch_env, &req, irn, -1) && req.type == arch_register_req_type_limited) {
+				pmap_insert(partners, op->carrier, op->partner ? op->partner->carrier : NULL);
+				alloc_nodes[n_alloc] = op->carrier;
+
+				DBG((dbg, LEVEL_2, "\tassociating %+F and %+F\n", op->carrier, op->partner ? op->partner->carrier : NULL));
+
+ 				bitset_clear_all(bs);
+				get_decisive_partner_regs(bs, op, op->partner);
+
+				DBG((dbg, LEVEL_2, "\tallowed registers for %+F: %B\n", op->carrier, bs));
+
+				bitset_foreach(bs, col)
+					bipartite_add(bp, n_alloc, col);
+
+				n_alloc++;
+			}
+		}
+
+		/*
+			Put all nodes which live by the constrained instruction also to the
+			allocation bipartite graph. They are considered unconstrained.
+		*/
+		if(perm) {
+			foreach_out_edge(perm, edge) {
+				ir_node *proj = get_edge_src_irn(edge);
+
+				assert(is_Proj(proj));
+
+				if(values_interfere(proj, irn) && !pmap_contains(partners, proj)) {
+					assert(n_alloc < n_regs);
+					alloc_nodes[n_alloc] = proj;
+					pmap_insert(partners, proj, NULL);
+
+					bitset_clear_all(bs);
+					arch_put_non_ignore_regs(aenv, env->cls, bs);
+					bitset_foreach(bs, col)
+						bipartite_add(bp, n_alloc, col);
+
+					n_alloc++;
+				}
+			}
+		}
+
+		/* Compute a valid register allocation. */
+		bipartite_matching(bp, assignment);
+
+		/* Assign colors obtained from the matching. */
+		for(i = 0; i < n_alloc; ++i) {
 			const arch_register_t *reg;
-			int col;
+			ir_node *nodes[2];
+			int j;
 
-			bitset_clear_all(bs);
-			req.data.limited(irn, -1, bs);
-			col = bitset_next_set(bs, 0);
-			reg = arch_register_for_index(alloc_env->chordal_env->cls, col);
+			assert(assignment[i] >= 0 && "there must have been a register assigned");
+			reg = arch_register_for_index(env->cls, assignment[i]);
 
-			arch_set_irn_register(arch_env, irn, reg);
-			bitset_set(alloc_env->colors, col);
+			nodes[0] = alloc_nodes[i];
+			nodes[1] = pmap_get(partners, alloc_nodes[i]);
+
+			for(j = 0; j < 2; ++j) {
+				if(!nodes[j])
+					continue;
+
+				arch_set_irn_register(aenv, nodes[j], reg);
+				pset_hinsert_ptr(alloc_env->pre_colored, nodes[j]);
+				DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", nodes[j], reg->name));
+			}
 		}
-	}
 
-	for(b = perm_border; b != next_border; b = border_next(b)) {
-		ir_node *irn = b->irn;
-		int nr       = get_irn_graph_nr(irn);
 
-		bitset_set(alloc_env->live, nr);
+		/* Allocate the non-constrained Projs of the Perm. */
+		if(perm) {
 
-		if(arch_get_irn_register(arch_env, irn) == NULL) {
-			int col                    = bitset_next_clear(alloc_env->colors, 0);
-			const arch_register_t *reg = arch_register_for_index(alloc_env->chordal_env->cls, col);
+			bitset_clear_all(bs);
 
-			arch_set_irn_register(arch_env, irn, reg);
+			/* Put the colors of all Projs in a bitset. */
+			foreach_out_edge(perm, edge) {
+				ir_node *proj              = get_edge_src_irn(edge);
+				const arch_register_t *reg = arch_get_irn_register(aenv, proj);
+
+				if(reg != NULL)
+					bitset_set(bs, reg->index);
+			}
+
+			/* Assign the not yet assigned Projs of the Perm a suitable color. */
+			foreach_out_edge(perm, edge) {
+				ir_node *proj              = get_edge_src_irn(edge);
+				const arch_register_t *reg = arch_get_irn_register(aenv, proj);
+
+				DBG((dbg, LEVEL_2, "\tchecking reg of %+F: %s\n", proj, reg ? reg->name : "<none>"));
+
+				if(reg == NULL) {
+					col = get_next_free_reg(alloc_env, bs);
+					reg = arch_register_for_index(env->cls, col);
+					bitset_set(bs, reg->index);
+					arch_set_irn_register(aenv, proj, reg);
+					pset_insert_ptr(alloc_env->pre_colored, proj);
+					DBG((dbg, LEVEL_2, "\tsetting %+F to register %s\n", proj, reg->name));
+				}
+			}
 		}
+
+		pmap_destroy(partners);
 	}
 
-	return cnstr_border;
+end:
+	obstack_free(&env->obst, base);
+	return res;
+}
+
+/**
+ * Handle constraint nodes in each basic block.
+ * handle_constraints() inserts Perm nodes which perm
+ * over all values live at the constrained node right in front
+ * of the constrained node. These Perms signal a constrained node.
+ * For further comments, refer to handle_constraints().
+ */
+static void constraints(ir_node *bl, void *data)
+{
+	be_chordal_alloc_env_t *env = data;
+
+	/*
+		Start silent in the start block.
+		The silence remains until the first barrier is seen.
+		Each other block is begun loud.
+	*/
+	int silent                  = bl == get_irg_start_block(get_irn_irg(bl));
+	ir_node *irn;
+
+	/*
+		If the block is the start block search the barrier and
+		start handling constraints from there.
+	*/
+
+	for(irn = sched_first(bl); !sched_is_end(irn);) {
+		irn = handle_constraints(env, irn, &silent);
+	}
 }
 
 /**
@@ -366,15 +799,15 @@ static void assign(ir_node *block, void *env_ptr)
 	bitset_t *live              = alloc_env->live;
 	bitset_t *colors            = alloc_env->colors;
 	bitset_t *in_colors         = alloc_env->in_colors;
-	const arch_env_t *arch_env  = env->main_env->arch_env;
+	const arch_env_t *arch_env  = env->birg->main_env->arch_env;
 
 	const ir_node *irn;
 	border_t *b;
 	struct list_head *head = get_block_border_head(env, block);
 	pset *live_in = put_live_in(block, pset_new_ptr_default());
 
-	bitset_clear_all(live);
 	bitset_clear_all(colors);
+	bitset_clear_all(live);
 	bitset_clear_all(in_colors);
 
 	DBG((dbg, LEVEL_4, "Assigning colors for block %+F\n", block));
@@ -407,7 +840,8 @@ static void assign(ir_node *block, void *env_ptr)
 	}
 
 	/*
-	 * Mind that the sequence of defs from back to front defines a perfect
+	 * Mind that the sequence
+	 * of defs from back to front defines a perfect
 	 * elimination order. So, coloring the definitions from first to last
 	 * will work.
 	 */
@@ -423,20 +857,27 @@ static void assign(ir_node *block, void *env_ptr)
 			const arch_register_t *reg;
 			int col = NO_COLOR;
 
-			DBG((dbg, LEVEL_4, "\tcolors in use: %b\n", colors));
-
-			col = bitset_next_clear(colors, 0);
-			reg = arch_register_for_index(env->cls, col);
+			if(pset_find_ptr(alloc_env->pre_colored, irn)) {
+				reg = arch_get_irn_register(arch_env, irn);
+				col = reg->index;
+				assert(!bitset_is_set(colors, col) && "pre-colored register must be free");
+			}
 
-			assert(arch_get_irn_register(arch_env, irn) == NULL && "This node must not have been assigned a register yet");
-			assert(!bitset_is_set(live, nr) && "Value's definition must not have been encountered");
+			else {
+				col = get_next_free_reg(alloc_env, colors);
+				reg = arch_register_for_index(env->cls, col);
+				assert(arch_get_irn_register(arch_env, irn) == NULL && "This node must not have been assigned a register yet");
+				assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
+			}
 
 			bitset_set(colors, col);
-			bitset_set(live, nr);
-
 			arch_set_irn_register(arch_env, irn, reg);
+
 			DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n",
             arch_register_get_name(reg), col, irn));
+
+			assert(!bitset_is_set(live, nr) && "Value's definition must not have been encountered");
+			bitset_set(live, nr);
 		}
 
 		/* Clear the color upon a use. */
@@ -451,18 +892,6 @@ static void assign(ir_node *block, void *env_ptr)
 
 			bitset_clear(colors, col);
 			bitset_clear(live, nr);
-
-			/*
-			 * If we encounter a Perm, it is due to register constraints.
-			 * To achieve a valid coloring in the presence of register
-			 * constraints, we invoke a special function which takes care
-			 * that all constraints are fulfilled.
-			 * This function assigned valid colors to the projs of the
-			 * Perm and the constrained node itself and skips these
-			 * nodes in the border list.
-			 */
-			if(is_Perm(b->irn))
-				b = handle_constraint_perm(alloc_env, border_next(b));
 		}
 	}
 
@@ -471,20 +900,40 @@ static void assign(ir_node *block, void *env_ptr)
 
 void be_ra_chordal_color(be_chordal_env_t *chordal_env)
 {
-	int node_count        = get_graph_node_count(chordal_env->irg);
+	be_chordal_alloc_env_t env;
+	char buf[256];
+	int i;
+
 	int colors_n          = arch_register_class_n_regs(chordal_env->cls);
 	ir_graph *irg         = chordal_env->irg;
 
-	be_chordal_alloc_env_t env;
 
 	if(get_irg_dom_state(irg) != dom_consistent)
 		compute_doms(irg);
 
-	env.chordal_env  = chordal_env;
-	env.live         = bitset_malloc(node_count);
-	env.colors       = bitset_malloc(colors_n);
-	env.in_colors    = bitset_malloc(colors_n);
-	env.colors_n     = colors_n;
+	env.chordal_env   = chordal_env;
+	env.colors_n      = colors_n;
+	env.colors        = bitset_alloca(colors_n);
+	env.tmp_colors    = bitset_alloca(colors_n);
+	env.in_colors     = bitset_alloca(colors_n);
+	env.ignore_regs   = bitset_alloca(colors_n);
+	env.pre_colored   = pset_new_ptr_default();
+	FIRM_DBG_REGISTER(env.constr_dbg, "firm.be.chordal.constr");
+
+	for(i = 0; i < colors_n; ++i)
+		if(arch_register_type_is(&chordal_env->cls->regs[i], ignore))
+			bitset_set(env.ignore_regs, i);
+
+	/* Handle register targeting constraints */
+	dom_tree_walk_irg(irg, constraints, NULL, &env);
+
+	if(chordal_env->opts->dump_flags & BE_CH_DUMP_CONSTR) {
+		snprintf(buf, sizeof(buf), "-%s-constr", chordal_env->cls->name);
+		be_dump(chordal_env->irg, buf, dump_ir_block_graph_sched);
+	}
+
+	be_numbering(irg);
+	env.live = bitset_malloc(get_graph_node_count(chordal_env->irg));
 
 	/* First, determine the pressure */
 	dom_tree_walk_irg(irg, pressure, NULL, &env);
@@ -492,20 +941,15 @@ void be_ra_chordal_color(be_chordal_env_t *chordal_env)
 	/* Assign the colors */
 	dom_tree_walk_irg(irg, assign, NULL, &env);
 
-#ifdef DUMP_INTERVALS
-	{
-		char buf[128];
-    	plotter_t *plotter;
+	be_numbering_done(irg);
 
-		ir_snprintf(buf, sizeof(buf), "ifg_%s_%F.eps", cls->name, irg);
+	if(chordal_env->opts->dump_flags & BE_CH_DUMP_TREE_INTV) {
+    	plotter_t *plotter;
+		ir_snprintf(buf, sizeof(buf), "ifg_%s_%F.eps", chordal_env->cls->name, irg);
     	plotter = new_plotter_ps(buf);
-
-    	draw_interval_tree(&draw_chordal_def_opts, chordal_env, plotter, env->arch_env, cls);
+    	draw_interval_tree(&draw_chordal_def_opts, chordal_env, plotter);
     	plotter_free(plotter);
 	}
-#endif
 
-	free(env.live);
-	free(env.colors);
-	free(env.in_colors);
+	del_pset(env.pre_colored);
 }