X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fbechordal.c;h=48196ace517e6d974d70dff4bc9a7072c80cabd1;hb=7b2fdea15f812ae2c395540f34c0e722c71e3a82;hp=721a1765e76fd9abb9818877f5f1be245d1d753a;hpb=6760fa51d54112059342d9d892630e1eb91bff31;p=libfirm

diff --git a/ir/be/bechordal.c b/ir/be/bechordal.c
index 721a1765e..48196ace5 100644
--- a/ir/be/bechordal.c
+++ b/ir/be/bechordal.c
@@ -286,10 +286,8 @@ static insn_t *scan_insn(be_chordal_alloc_env_t *alloc_env, ir_node *irn, struct
 		assert(op->req.cls == env->cls);
 		op->regs   = bitset_obstack_alloc(obst, env->cls->n_regs);
 
-		if(arch_register_req_is(&op->req, limited)) {
+		if(arch_register_req_is(&op->req, limited))
 			op->req.limited(op->req.limited_env, op->regs);
-			bitset_andnot(op->regs, alloc_env->ignore_regs);
-		}
 		else
 			arch_put_non_ignore_regs(env->birg->main_env->arch_env, env->cls, op->regs);
 	}
@@ -477,12 +475,13 @@ static ir_node *pre_process_constraints(be_chordal_alloc_env_t *alloc_env, insn_
 	return perm;
 }
 
-static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env, ir_node *irn)
+static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env, ir_node *irn, int *silent)
 {
 	be_chordal_env_t *env  = alloc_env->chordal_env;
 	void *base             = obstack_base(&env->obst);
 	insn_t *insn           = scan_insn(alloc_env, irn, &env->obst);
 	ir_node *res           = insn->next_insn;
+	int be_silent          = *silent;
 
 	if(insn->pre_colored) {
 		int i;
@@ -490,7 +489,17 @@ static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env, ir_node *i
 			pset_insert_ptr(alloc_env->pre_colored, insn->ops[i].carrier);
 	}
 
-	if(be_is_Perm(irn) || be_is_RegParams(irn) || (be_is_Barrier(irn) && !insn->in_constraints))
+	/*
+		If the current node is a barrier toggle the silent flag.
+		If we are in the start block, we are ought to be silent at the beginning,
+		so the toggling activates the constraint handling but skips the barrier.
+		If we are in the end block we handle the in requirements of the barrier
+		and set the rest to silent.
+	*/
+	if(be_is_Barrier(irn))
+		*silent = !*silent;
+
+	if(be_silent)
 		goto end;
 
 	/*
@@ -565,7 +574,7 @@ static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env, ir_node *i
 
 				assert(is_Proj(proj));
 
-				if(values_interfere(proj, irn)) {
+				if(values_interfere(proj, irn) && !pmap_contains(partners, proj)) {
 					assert(n_alloc < n_regs);
 					alloc_nodes[n_alloc] = proj;
 					pmap_insert(partners, proj, NULL);
@@ -648,20 +657,32 @@ end:
 
 /**
  * Handle constraint nodes in each basic block.
- * be_insert_constr_perms() inserts Perm nodes which perm
+ * handle_constraints() inserts Perm nodes which perm
  * over all values live at the constrained node right in front
  * of the constrained node. These Perms signal a constrained node.
- * For further comments, refer to handle_constraints_at_perm().
+ * For further comments, refer to handle_constraints().
  */
 static void constraints(ir_node *bl, void *data)
 {
-	firm_dbg_module_t *dbg      = firm_dbg_register("firm.be.chordal.constr");
 	be_chordal_alloc_env_t *env = data;
+	firm_dbg_module_t *dbg      = firm_dbg_register("firm.be.chordal.constr");
 	arch_env_t *arch_env        = env->chordal_env->birg->main_env->arch_env;
+
+	/*
+		Start silent in the start block.
+		The silence remains until the first barrier is seen.
+		Each other block is begun loud.
+	*/
+	int silent                  = bl == get_irg_start_block(get_irn_irg(bl));
 	ir_node *irn;
 
+	/*
+		If the block is the start block search the barrier and
+		start handling constraints from there.
+	*/
+
 	for(irn = sched_first(bl); !sched_is_end(irn);) {
-		irn = handle_constraints(env, irn);
+		irn = handle_constraints(env, irn, &silent);
 	}
 }
 
@@ -853,11 +874,10 @@ static void assign(ir_node *block, void *env_ptr)
 				col = get_next_free_reg(alloc_env, colors);
 				reg = arch_register_for_index(env->cls, col);
 				assert(arch_get_irn_register(arch_env, irn) == NULL && "This node must not have been assigned a register yet");
+				assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
 			}
 
 			bitset_set(colors, col);
-
-			assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
 			arch_set_irn_register(arch_env, irn, reg);
 
 			DBG((dbg, LEVEL_1, "\tassigning register %s(%d) to %+F\n",