X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fbearch.h;h=6a688660e257772a6755459e283650e6698ced2a;hb=10e58f9669ea6c77e82bd3bc12c4ac5bbaa6bb15;hp=b6ffb7ff1607189ab558fe738f0ed9b6c38a45c2;hpb=b3cb8009dbbb225e0e047bec10c3c06339d1a430;p=libfirm diff --git a/ir/be/bearch.h b/ir/be/bearch.h index b6ffb7ff1..6a688660e 100644 --- a/ir/be/bearch.h +++ b/ir/be/bearch.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved. + * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved. * * This file is part of libFirm. * @@ -38,14 +38,23 @@ #include "beinfo.h" #include "be.h" #include "beirg.h" +#include "error.h" + +/** + * this constant is returned by the get_sp_bias functions if the stack + * is reset (usually because the frame pointer is copied to the stack + * pointer + */ +#define SP_BIAS_RESET INT_MIN typedef enum arch_register_class_flags_t { arch_register_class_flag_none = 0, - /**< don't do automatic register allocation for this class */ - arch_register_class_flag_manual_ra = 1U << 0, - /**< the register models an abstract state (example: fpu rounding mode) */ + /** don't do automatic register allocation for this class */ + arch_register_class_flag_manual_ra = 1U << 0, + /** the register models an abstract state (example: fpu rounding mode) */ arch_register_class_flag_state = 1U << 1 } arch_register_class_flags_t; +ENUM_BITSET(arch_register_class_flags_t) typedef enum arch_register_type_t { arch_register_type_none = 0, @@ -68,13 +77,14 @@ typedef enum arch_register_type_t { * code */ arch_register_type_state = 1U << 5, } arch_register_type_t; +ENUM_BITSET(arch_register_type_t) /** * Different types of register allocation requirements. */ typedef enum arch_register_req_type_t { /** No register requirement. */ - arch_register_req_type_none = 0, + arch_register_req_type_none = 0, /** All registers in the class are allowed. */ arch_register_req_type_normal = 1U << 0, /** Only a real subset of the class is allowed. */ @@ -83,13 +93,16 @@ typedef enum arch_register_req_type_t { arch_register_req_type_should_be_same = 1U << 2, /** The register must be unequal from some other at the node. */ arch_register_req_type_must_be_different = 1U << 3, + /** The registernumber should be aligned (in case of multiregister values)*/ + arch_register_req_type_aligned = 1U << 4, /** ignore while allocating registers */ - arch_register_req_type_ignore = 1U << 4, + arch_register_req_type_ignore = 1U << 5, /** the output produces a new value for the stack pointer * (this is not really a constraint but a marker to guide the stackpointer * rewiring logic) */ - arch_register_req_type_produces_sp = 1U << 5, + arch_register_req_type_produces_sp = 1U << 6, } arch_register_req_type_t; +ENUM_BITSET(arch_register_req_type_t) extern const arch_register_req_t *arch_no_register_req; @@ -105,20 +118,21 @@ void arch_dump_register_reqs(FILE *F, const ir_node *node); void arch_dump_reqs_and_registers(FILE *F, const ir_node *node); /** - * Node classification. Used for statistics. + * Node classification. Used for statistics and for detecting reload nodes. */ typedef enum arch_irn_class_t { + arch_irn_class_none = 0, arch_irn_class_spill = 1 << 0, arch_irn_class_reload = 1 << 1, arch_irn_class_remat = 1 << 2, arch_irn_class_copy = 1 << 3, arch_irn_class_perm = 1 << 4 } arch_irn_class_t; +ENUM_BITSET(arch_irn_class_t) void arch_set_frame_offset(ir_node *irn, int bias); ir_entity *arch_get_frame_entity(const ir_node *irn); -void arch_set_frame_entity(ir_node *irn, ir_entity *ent); int arch_get_sp_bias(ir_node *irn); int arch_get_op_estimated_cost(const ir_node *irn); @@ -143,15 +157,6 @@ void arch_perform_memory_operand(ir_node *irn, ir_node *spill, */ const arch_register_req_t *arch_get_register_req(const ir_node *irn, int pos); -/** - * Put all registers which shall not be ignored by the register - * allocator in a bit set. - * @param cls The register class to consider. - * @param bs The bit set to put the registers to. - */ -extern void arch_put_non_ignore_regs(const arch_register_class_t *cls, - bitset_t *bs); - /** * Check, if a register is assignable to an operand of a node. * @param irn The node. @@ -199,8 +204,6 @@ void arch_irn_set_register(ir_node *irn, int pos, const arch_register_t *reg); */ arch_irn_class_t arch_irn_classify(const ir_node *irn); -#define arch_irn_class_is(irn, irn_class) ((arch_irn_classify(irn) & arch_irn_class_ ## irn_class) != 0) - /** * Get the flags of a node. * @param irn The node. @@ -239,44 +242,33 @@ void be_register_isa_if(const char *name, const arch_isa_if_t *isa); * A register. */ struct arch_register_t { - const char *name; /**< The name of the register. */ - const arch_register_class_t *reg_class; /**< The class of the register */ - unsigned index; /**< The index of the register in - the class. */ - arch_register_type_t type; /**< The type of the register. */ + const char *name; /**< The name of the register. */ + const arch_register_class_t *reg_class; /**< The class of the register */ + unsigned short index; /**< The index of the register in + the class. */ + unsigned short global_index; /** The global index this register + in the architecture. */ + arch_register_type_t type; /**< The type of the register. */ /** register constraint allowing just this register */ const arch_register_req_t *single_req; }; -static inline const arch_register_class_t *_arch_register_get_class( +static inline const arch_register_class_t *arch_register_get_class( const arch_register_t *reg) { return reg->reg_class; } -static inline unsigned _arch_register_get_index(const arch_register_t *reg) +static inline unsigned arch_register_get_index(const arch_register_t *reg) { return reg->index; } -static inline const char *_arch_register_get_name(const arch_register_t *reg) +static inline const char *arch_register_get_name(const arch_register_t *reg) { return reg->name; } -#define arch_register_get_class(reg) _arch_register_get_class(reg) -#define arch_register_get_index(reg) _arch_register_get_index(reg) -#define arch_register_get_name(reg) _arch_register_get_name(reg) - -/** - * Convenience macro to check for register type. - * @param req A pointer to register. - * @param kind The kind of type to check for (see arch_register_type_t). - * @return 1, If register is of given kind, 0 if not. - */ -#define arch_register_type_is(reg, kind) \ - (((reg)->type & arch_register_type_ ## kind) != 0) - /** * A class of registers. * Like general purpose or floating point. @@ -307,15 +299,13 @@ struct arch_register_class_t { /** return the register class flags */ #define arch_register_class_flags(cls) ((cls)->flags) -static inline const arch_register_t *_arch_register_for_index( +static inline const arch_register_t *arch_register_for_index( const arch_register_class_t *cls, unsigned idx) { assert(idx < cls->n_regs); return &cls->regs[idx]; } -#define arch_register_for_index(cls, idx) _arch_register_for_index(cls, idx) - /** * Convenience macro to check for set constraints. * @param req A pointer to register requirements. @@ -339,6 +329,8 @@ struct arch_register_req_t { unsigned other_different; /**< Bitmask of ins which shall use a different register (must_be_different) */ + unsigned char width; /**< specifies how many sequential + registers are required */ }; static inline int reg_reqs_equal(const arch_register_req_t *req1, @@ -381,16 +373,6 @@ struct arch_inverse_t { struct arch_irn_ops_t { - /** - * Get the register requirements for a given operand. - * @param irn The node. - * @param pos The operand's position - * @return The register requirements for the selected operand. - * The pointer returned is never NULL. - */ - const arch_register_req_t *(*get_irn_reg_req_in)(const ir_node *irn, - int pos); - /** * Classify the node. * @param irn The node. @@ -406,13 +388,6 @@ struct arch_irn_ops_t { */ ir_entity *(*get_frame_entity)(const ir_node *irn); - /** - * Set the entity on the stack frame this node depends on. - * @param irn The node in question. - * @param ent The entity to set - */ - void (*set_frame_entity)(ir_node *irn, ir_entity *ent); - /** * Set the offset of a node carrying an entity on the stack frame. * @param irn The node. @@ -479,96 +454,6 @@ struct arch_irn_ops_t { unsigned int i); }; -/** - * The code generator interface. - */ -struct arch_code_generator_if_t { - /** - * Initialize the code generator. - * @param birg A backend IRG session. - * @return A newly created code generator. - */ - void *(*init)(be_irg_t *birg); - - /** - * return node used as base in pic code addresses - */ - ir_node* (*get_pic_base)(void *self); - - /** - * Called before abi introduce. - */ - void (*before_abi)(void *self); - - /** - * Called, when the graph is being normalized. - */ - void (*prepare_graph)(void *self); - - /** - * Backend may provide an own spiller. - * This spiller needs to spill all register classes. - */ - void (*spill)(void *self, be_irg_t *birg); - - /** - * Called before register allocation. - */ - void (*before_ra)(void *self); - - /** - * Called after register allocation. - */ - void (*after_ra)(void *self); - - /** - * Called directly before done is called. This should be the last place - * where the irg is modified. - */ - void (*finish)(void *self); - - /** - * Called after everything happened. This call should emit the final - * assembly code but avoid changing the irg. - * The code generator must also be de-allocated here. - */ - void (*done)(void *self); -}; - -/** - * helper macro: call function func from the code generator - * if it's implemented. - */ -#define _arch_cg_call(cg, func) \ -do { \ - if((cg)->impl->func) \ - (cg)->impl->func(cg); \ -} while(0) - -#define _arch_cg_call_env(cg, env, func) \ -do { \ - if((cg)->impl->func) \ - (cg)->impl->func(cg, env); \ -} while(0) - -#define arch_code_generator_before_abi(cg) _arch_cg_call(cg, before_abi) -#define arch_code_generator_prepare_graph(cg) _arch_cg_call(cg, prepare_graph) -#define arch_code_generator_before_ra(cg) _arch_cg_call(cg, before_ra) -#define arch_code_generator_after_ra(cg) _arch_cg_call(cg, after_ra) -#define arch_code_generator_finish(cg) _arch_cg_call(cg, finish) -#define arch_code_generator_done(cg) _arch_cg_call(cg, done) -#define arch_code_generator_spill(cg, birg) _arch_cg_call_env(cg, birg, spill) -#define arch_code_generator_has_spiller(cg) ((cg)->impl->spill != NULL) -#define arch_code_generator_get_pic_base(cg) \ - ((cg)->impl->get_pic_base != NULL ? (cg)->impl->get_pic_base(cg) : NULL) - -/** - * Code generator base class. - */ -struct arch_code_generator_t { - const arch_code_generator_if_t *impl; -}; - /** * Architecture interface. */ @@ -580,6 +465,12 @@ struct arch_isa_if_t { */ arch_env_t *(*init)(FILE *file_handle); + /** + * lowers current program for target. See the documentation for + * be_lower_for_target() for details. + */ + void (*lower_for_target)(void); + /** * Free the isa instance. */ @@ -591,19 +482,6 @@ struct arch_isa_if_t { */ void (*handle_intrinsics)(void); - /** - * Get the the number of register classes in the isa. - * @return The number of register classes. - */ - unsigned (*get_n_reg_class)(void); - - /** - * Get the i-th register class. - * @param i The number of the register class. - * @return The register class. - */ - const arch_register_class_t *(*get_reg_class)(unsigned i); - /** * Get the register class which shall be used to store a value of a given * mode. @@ -622,31 +500,6 @@ struct arch_isa_if_t { void (*get_call_abi)(const void *self, ir_type *call_type, be_abi_call_t *abi); - /** - * Get the code generator interface. - * @param self The this pointer. - * @return Some code generator interface. - */ - const arch_code_generator_if_t *(*get_code_generator_if)(void *self); - - /** - * Get the list scheduler to use. There is already a selector given, the - * backend is free to modify and/or ignore it. - * - * @param self The isa object. - * @param selector The selector given by options. - * @return The list scheduler selector. - */ - const list_sched_selector_t *(*get_list_sched_selector)(const void *self, - list_sched_selector_t *selector); - - /** - * Get the ILP scheduler to use. - * @param self The isa object. - * @return The ILP scheduler selector - */ - const ilp_sched_selector_t *(*get_ilp_sched_selector)(const void *self); - /** * Get the necessary alignment for storing a register of given class. * @param self The isa object. @@ -661,30 +514,6 @@ struct arch_isa_if_t { */ const backend_params *(*get_params)(void); - /** - * Returns an 2-dim array of execution units, @p irn can be executed on. - * The first dimension is the type, the second the allowed units of this - * type. - * Each dimension is a NULL terminated list. - * @param self The isa object. - * @param irn The node. - * @return An array of allowed execution units. - * exec_unit = { - * { unit1_of_tp1, ..., unitX1_of_tp1, NULL }, - * ..., - * { unit1_of_tpY, ..., unitXn_of_tpY, NULL }, - * NULL - * }; - */ - const be_execution_unit_t ***(*get_allowed_execution_units)( - const ir_node *irn); - - /** - * Return the abstract machine for this isa. - * @param self The isa object. - */ - const be_machine_t *(*get_machine)(const void *self); - /** * Return an ordered list of irgs where code should be generated for. * If NULL is returned, all irg will be taken into account and they will be @@ -714,18 +543,58 @@ struct arch_isa_if_t { * backend */ int (*is_valid_clobber)(const char *clobber); + + /** + * Initialize the code generator. + * @param irg A graph + * @return A newly created code generator. + */ + void (*init_graph)(ir_graph *irg); + + /** + * return node used as base in pic code addresses + */ + ir_node* (*get_pic_base)(ir_graph *irg); + + /** + * Called before abi introduce. + */ + void (*before_abi)(ir_graph *irg); + + /** + * Called, when the graph is being normalized. + */ + void (*prepare_graph)(ir_graph *irg); + + /** + * Called before register allocation. + */ + void (*before_ra)(ir_graph *irg); + + /** + * Called after register allocation. + */ + void (*after_ra)(ir_graph *irg); + + /** + * Called directly before done is called. This should be the last place + * where the irg is modified. + */ + void (*finish)(ir_graph *irg); + + /** + * Called after everything happened. This call should emit the final + * assembly code but avoid changing the irg. + * The code generator must also be de-allocated here. + */ + void (*emit)(ir_graph *irg); }; #define arch_env_done(env) ((env)->impl->done(env)) #define arch_env_handle_intrinsics(env) \ do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0) -#define arch_env_get_n_reg_class(env) ((env)->impl->get_n_reg_class()) -#define arch_env_get_reg_class(env,i) ((env)->impl->get_reg_class(i)) #define arch_env_get_reg_class_for_mode(env,mode) ((env)->impl->get_reg_class_for_mode((mode))) #define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((env), (tp), (abi))) -#define arch_env_get_code_generator_if(env) ((env)->impl->get_code_generator_if((env))) -#define arch_env_get_list_sched_selector(env,selector) ((env)->impl->get_list_sched_selector((env), (selector))) -#define arch_env_get_ilp_sched_selector(env) ((env)->impl->get_ilp_sched_selector(env)) #define arch_env_get_reg_class_alignment(env,cls) ((env)->impl->get_reg_class_alignment((cls))) #define arch_env_get_params(env) ((env)->impl->get_params()) #define arch_env_get_allowed_execution_units(env,irn) ((env)->impl->get_allowed_execution_units((irn))) @@ -741,16 +610,21 @@ struct arch_isa_if_t { */ struct arch_env_t { const arch_isa_if_t *impl; + unsigned n_registers; /**< number of registers */ + const arch_register_t *registers; /**< register array */ + unsigned n_register_classes; /**< number of register classes*/ + const arch_register_class_t *register_classes; /**< register classes */ const arch_register_t *sp; /**< The stack pointer register. */ const arch_register_t *bp; /**< The base pointer register. */ const arch_register_class_t *link_class; /**< The static link pointer register class. */ - int stack_dir; /**< -1 for decreasing, 1 for - increasing. */ int stack_alignment; /**< power of 2 stack alignment */ const be_main_env_t *main_env; /**< the be main environment */ int spill_cost; /**< cost for a be_Spill node */ int reload_cost; /**< cost for a be_Reload node */ + bool custom_abi : 1; /**< backend does all abi handling + and does not need the generic + stuff from beabi.h/.c */ }; static inline unsigned arch_irn_get_n_outs(const ir_node *node) @@ -759,7 +633,7 @@ static inline unsigned arch_irn_get_n_outs(const ir_node *node) if (info->out_infos == NULL) return 0; - return ARR_LEN(info->out_infos); + return (unsigned)ARR_LEN(info->out_infos); } static inline const arch_irn_ops_t *get_irn_ops_simple(const ir_node *node) @@ -776,13 +650,16 @@ static inline const arch_register_req_t *arch_get_register_req_out( int pos = 0; backend_info_t *info; + /* you have to query the Proj nodes for the constraints (or use + * arch_get_out_register_req. Querying a mode_T node and expecting + * arch_no_register_req is a bug in your code! */ + assert(get_irn_mode(irn) != mode_T); + if (is_Proj(irn)) { pos = get_Proj_proj(irn); irn = get_Proj_pred(irn); - } else if (get_irn_mode(irn) == mode_T) { - /* TODO: find out who does this and fix the caller! */ - return arch_no_register_req; } + info = be_get_info(irn); if (info->out_infos == NULL) return arch_no_register_req; @@ -811,8 +688,10 @@ static inline bool arch_irn_consider_in_reg_alloc( static inline const arch_register_req_t *arch_get_in_register_req( const ir_node *node, int pos) { - const arch_irn_ops_t *ops = get_irn_ops_simple(node); - return ops->get_irn_reg_req_in(node, pos); + const backend_info_t *info = be_get_info(node); + if (info->in_reqs == NULL) + return arch_no_register_req; + return info->in_reqs[pos]; } /** @@ -835,4 +714,52 @@ static inline void arch_set_out_register_req(ir_node *node, int pos, info->out_infos[pos].req = req; } +static inline void arch_set_in_register_reqs(ir_node *node, + const arch_register_req_t **in_reqs) +{ + backend_info_t *info = be_get_info(node); + info->in_reqs = in_reqs; +} + +static inline const arch_register_req_t **arch_get_in_register_reqs( + const ir_node *node) +{ + backend_info_t *info = be_get_info(node); + return info->in_reqs; +} + +/** + * Iterate over all values defined by an instruction. + * Only looks at values in a certain register class where the requirements + * are not marked as ignore. + * Executes @p code for each definition. + */ +#define be_foreach_definition_(node, cls, value, code) \ + do { \ + if (get_irn_mode(node) == mode_T) { \ + const ir_edge_t *edge_; \ + foreach_out_edge(node, edge_) { \ + const arch_register_req_t *req_; \ + value = get_edge_src_irn(edge_); \ + req_ = arch_get_register_req_out(value); \ + if (req_->cls != cls) \ + continue; \ + code \ + } \ + } else { \ + const arch_register_req_t *req_ = arch_get_register_req_out(node); \ + value = node; \ + if (req_->cls == cls) { \ + code \ + } \ + } \ + } while (0) + +#define be_foreach_definition(node, cls, value, code) \ + be_foreach_definition_(node, cls, value, \ + if (req_->type & arch_register_req_type_ignore) \ + continue; \ + code \ + ) + #endif