X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Fbearch.h;h=02daa70b4e125318c9fe59c12e551b6c46751f32;hb=29087feac9466883c278e53eec325d5e3099df1d;hp=9c56e5233e018d19ca176a65bfa0051bde40ebce;hpb=bb523cb9ad91bcdc9af9e8e23093b637f3cba096;p=libfirm diff --git a/ir/be/bearch.h b/ir/be/bearch.h index 9c56e5233..02daa70b4 100644 --- a/ir/be/bearch.h +++ b/ir/be/bearch.h @@ -21,7 +21,6 @@ * @file * @brief Processor architecture specification. * @author Sebastian Hack - * @version $Id$ */ #ifndef FIRM_BE_BEARCH_H #define FIRM_BE_BEARCH_H @@ -29,16 +28,11 @@ #include #include "firm_types.h" -#include "bitset.h" -#include "obst.h" #include "raw_bitset.h" -#include "irop_t.h" #include "be_types.h" #include "beinfo.h" #include "be.h" -#include "beirg.h" -#include "error.h" /** * this constant is returned by the get_sp_bias functions if the stack @@ -58,24 +52,15 @@ ENUM_BITSET(arch_register_class_flags_t) typedef enum arch_register_type_t { arch_register_type_none = 0, - /** The register must be saved by the caller upon a function call. It thus - * can be overwritten in the called function. */ - arch_register_type_caller_save = 1U << 0, - /** The register must be saved by the caller upon a function call. It thus - * can be overwritten in the called function. */ - arch_register_type_callee_save = 1U << 1, /** Do not consider this register when allocating. */ - arch_register_type_ignore = 1U << 2, - /** The emitter can choose an arbitrary register. The register fulfills any - * register constraints as long as the register class matches */ - arch_register_type_joker = 1U << 3, + arch_register_type_ignore = 1U << 0, /** This is just a virtual register. Virtual registers fulfill any register * constraints as long as the register class matches. It is a allowed to * have multiple definitions for the same virtual register at a point */ - arch_register_type_virtual = 1U << 4, + arch_register_type_virtual = 1U << 1, /** The register represents a state that should be handled by bestate * code */ - arch_register_type_state = 1U << 5, + arch_register_type_state = 1U << 2, } arch_register_type_t; ENUM_BITSET(arch_register_type_t) @@ -104,134 +89,128 @@ typedef enum arch_register_req_type_t { } arch_register_req_type_t; ENUM_BITSET(arch_register_req_type_t) -extern const arch_register_req_t *arch_no_register_req; - -/** - * Print information about a register requirement in human readable form - * @param F output stream/file - * @param req The requirements structure to format. - */ -void arch_dump_register_req(FILE *F, const arch_register_req_t *req, - const ir_node *node); +extern arch_register_req_t const arch_no_requirement; +#define arch_no_register_req (&arch_no_requirement) void arch_dump_register_reqs(FILE *F, const ir_node *node); void arch_dump_reqs_and_registers(FILE *F, const ir_node *node); -/** - * Node classification. Used for statistics and for detecting reload nodes. - */ -typedef enum arch_irn_class_t { - arch_irn_class_none = 0, - arch_irn_class_spill = 1 << 0, - arch_irn_class_reload = 1 << 1, - arch_irn_class_remat = 1 << 2, - arch_irn_class_copy = 1 << 3, - arch_irn_class_perm = 1 << 4 -} arch_irn_class_t; -ENUM_BITSET(arch_irn_class_t) - void arch_set_frame_offset(ir_node *irn, int bias); ir_entity *arch_get_frame_entity(const ir_node *irn); int arch_get_sp_bias(ir_node *irn); int arch_get_op_estimated_cost(const ir_node *irn); -arch_inverse_t *arch_get_inverse(const ir_node *irn, int i, - arch_inverse_t *inverse, - struct obstack *obstack); int arch_possible_memory_operand(const ir_node *irn, unsigned int i); void arch_perform_memory_operand(ir_node *irn, ir_node *spill, unsigned int i); /** - * Get the register requirements for a node. - * @note Deprecated API! Preferably use - * arch_get_in_register_req and - * arch_get_out_register_req. - * - * @param irn The node. - * @param pos The position of the operand you're interested in. - * @return A pointer to the register requirements. If NULL is returned, the - * operand was no register operand. + * Get the register allocated for a value. */ -const arch_register_req_t *arch_get_register_req(const ir_node *irn, int pos); +const arch_register_t *arch_get_irn_register(const ir_node *irn); /** - * Check, if a register is assignable to an operand of a node. - * @param irn The node. - * @param pos The position of the operand. - * @param reg The register. - * @return 1, if the register might be allocated to the operand 0 if not. + * Assign register to a value */ -int arch_reg_is_allocatable(const ir_node *irn, int pos, - const arch_register_t *reg); - -#define arch_reg_out_is_allocatable(irn, reg) arch_reg_is_allocatable(irn, -1, reg) +void arch_set_irn_register(ir_node *irn, const arch_register_t *reg); /** - * Get the register class of an operand of a node. - * @param irn The node. - * @param pos The position of the operand, -1 for the output. - * @return The register class of the operand or NULL, if - * operand is a non-register operand. + * Set the register for a certain output operand. */ -const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn, - int pos); +void arch_set_irn_register_out(ir_node *irn, unsigned pos, const arch_register_t *r); -#define arch_get_irn_reg_class_out(irn) arch_get_irn_reg_class(irn, -1) +const arch_register_t *arch_get_irn_register_out(const ir_node *irn, unsigned pos); +const arch_register_t *arch_get_irn_register_in(const ir_node *irn, int pos); /** - * Get the register allocated at a certain output operand of a node. - * @param irn The node. - * @return The register allocated for this operand + * Get register constraints for an operand at position @p */ -const arch_register_t *arch_get_irn_register(const ir_node *irn); -const arch_register_t *arch_irn_get_register(const ir_node *irn, int pos); +static inline const arch_register_req_t *arch_get_irn_register_req_in( + const ir_node *node, int pos) +{ + const backend_info_t *info = be_get_info(node); + return info->in_reqs[pos]; +} /** - * Set the register for a certain output operand. - * @param irn The node. - * @param reg The register. + * Get register constraint for a produced result (the @p pos result) */ -void arch_set_irn_register(ir_node *irn, const arch_register_t *reg); -void arch_irn_set_register(ir_node *irn, int pos, const arch_register_t *reg); +static inline const arch_register_req_t *arch_get_irn_register_req_out( + const ir_node *node, unsigned pos) +{ + const backend_info_t *info = be_get_info(node); + return info->out_infos[pos].req; +} -/** - * Classify a node. - * @param irn The node. - * @return A classification of the node. - */ -arch_irn_class_t arch_irn_classify(const ir_node *irn); +static inline void arch_set_irn_register_req_out(ir_node *node, unsigned pos, + const arch_register_req_t *req) +{ + backend_info_t *info = be_get_info(node); + assert(pos < (unsigned)ARR_LEN(info->out_infos)); + info->out_infos[pos].req = req; +} + +static inline void arch_set_irn_register_reqs_in(ir_node *node, + const arch_register_req_t **reqs) +{ + backend_info_t *info = be_get_info(node); + info->in_reqs = reqs; +} + +static inline const arch_register_req_t **arch_get_irn_register_reqs_in( + const ir_node *node) +{ + backend_info_t *info = be_get_info(node); + return info->in_reqs; +} + +static inline reg_out_info_t *get_out_info(const ir_node *node) +{ + size_t pos = 0; + const backend_info_t *info; + assert(get_irn_mode(node) != mode_T); + if (is_Proj(node)) { + pos = get_Proj_proj(node); + node = get_Proj_pred(node); + } + + info = be_get_info(node); + assert(pos < ARR_LEN(info->out_infos)); + return &info->out_infos[pos]; +} + +static inline const arch_register_req_t *arch_get_irn_register_req(const ir_node *node) +{ + reg_out_info_t *out = get_out_info(node); + return out->req; +} /** * Get the flags of a node. * @param irn The node. * @return The flags. */ -arch_irn_flags_t arch_irn_get_flags(const ir_node *irn); +static inline arch_irn_flags_t arch_get_irn_flags(const ir_node *node) +{ + backend_info_t const *const info = be_get_info(node); + return info->flags; +} -void arch_irn_set_flags(ir_node *node, arch_irn_flags_t flags); -void arch_irn_add_flags(ir_node *node, arch_irn_flags_t flags); +void arch_set_irn_flags(ir_node *node, arch_irn_flags_t flags); +void arch_add_irn_flags(ir_node *node, arch_irn_flags_t flags); -#define arch_irn_is(irn, flag) ((arch_irn_get_flags(irn) & arch_irn_flags_ ## flag) != 0) +#define arch_irn_is(irn, flag) ((arch_get_irn_flags(irn) & arch_irn_flags_ ## flag) != 0) -/** - * Get the operations of an irn. - * @param self The handler from which the method is invoked. - * @param irn Some node. - * @return Operations for that irn. - */ -typedef const void *(arch_get_irn_ops_t)(const ir_node *irn); +static inline unsigned arch_get_irn_n_outs(const ir_node *node) +{ + backend_info_t *const info = be_get_info(node); + return (unsigned)ARR_LEN(info->out_infos); +} -/** - * Initialize the architecture environment struct. - * @param isa The isa which shall be put into the environment. - * @param file_handle The file handle - * @return The environment. - */ -extern arch_env_t *arch_env_init(const arch_isa_if_t *isa, - FILE *file_handle, be_main_env_t *main_env); +#define be_foreach_out(node, i) \ + for (unsigned i = 0, i##__n = arch_get_irn_n_outs(node); i != i##__n; ++i) /** * Register an instruction set architecture @@ -246,29 +225,15 @@ struct arch_register_t { const arch_register_class_t *reg_class; /**< The class of the register */ unsigned short index; /**< The index of the register in the class. */ - unsigned short global_index; /** The global index this register - in the architecture. */ + unsigned short global_index; /**< The global index this + register in the architecture. */ arch_register_type_t type; /**< The type of the register. */ /** register constraint allowing just this register */ const arch_register_req_t *single_req; + /** register number in dwarf debugging format */ + unsigned short dwarf_number; }; -static inline const arch_register_class_t *arch_register_get_class( - const arch_register_t *reg) -{ - return reg->reg_class; -} - -static inline unsigned arch_register_get_index(const arch_register_t *reg) -{ - return reg->index; -} - -static inline const char *arch_register_get_name(const arch_register_t *reg) -{ - return reg->name; -} - /** * A class of registers. * Like general purpose or floating point. @@ -323,63 +288,42 @@ struct arch_register_req_t { arch_register_req_type_t type; /**< The type of the constraint. */ const arch_register_class_t *cls; /**< The register class this constraint belongs to. */ - const unsigned *limited; /**< allowed register bitset */ - unsigned other_same; /**< Bitmask of ins which should use the - same register (should_be_same). */ - unsigned other_different; /**< Bitmask of ins which shall use a - different register - (must_be_different) */ - unsigned char width; /**< specifies how many sequential - registers are required */ + const unsigned *limited; /**< allowed register bitset + (in case of wide-values this is + only about the first register) */ + unsigned other_same; /**< Bitmask of ins which should use the + same register (should_be_same). */ + unsigned other_different; /**< Bitmask of ins which shall use a + different register + (must_be_different) */ + unsigned char width; /**< specifies how many sequential + registers are required */ }; -static inline int reg_reqs_equal(const arch_register_req_t *req1, - const arch_register_req_t *req2) +static inline bool reg_reqs_equal(const arch_register_req_t *req1, + const arch_register_req_t *req2) { if (req1 == req2) - return 1; + return true; - if (req1->type != req2->type - || req1->cls != req2->cls - || req1->other_same != req2->other_same - || req1->other_different != req2->other_different) - return 0; + if (req1->type != req2->type || + req1->cls != req2->cls || + req1->other_same != req2->other_same || + req1->other_different != req2->other_different || + (req1->limited != NULL) != (req2->limited != NULL)) + return false; if (req1->limited != NULL) { - size_t n_regs; - - if (req2->limited == NULL) - return 0; - - n_regs = arch_register_class_n_regs(req1->cls); + size_t const n_regs = arch_register_class_n_regs(req1->cls); if (!rbitsets_equal(req1->limited, req2->limited, n_regs)) - return 0; + return false; } - return 1; + return true; } -/** - * An inverse operation returned by the backend - */ -struct arch_inverse_t { - int n; /**< count of nodes returned in nodes array */ - int costs; /**< costs of this remat */ - - /** nodes for this inverse operation. shall be in schedule order. - * last element is the target value */ - ir_node **nodes; -}; - struct arch_irn_ops_t { - /** - * Classify the node. - * @param irn The node. - * @return A classification. - */ - arch_irn_class_t (*classify)(const ir_node *irn); - /** * Get the entity on the stack frame this node depends on. * @param irn The node in question. @@ -408,22 +352,6 @@ struct arch_irn_ops_t { */ int (*get_sp_bias)(const ir_node *irn); - /** - * Returns an inverse operation which yields the i-th argument - * of the given node as result. - * - * @param irn The original operation - * @param i Index of the argument we want the inverse operation to - * yield - * @param inverse struct to be filled with the resulting inverse op - * @param obstack The obstack to use for allocation of the returned nodes - * array - * @return The inverse operation or NULL if operation invertible - */ - arch_inverse_t *(*get_inverse)(const ir_node *irn, int i, - arch_inverse_t *inverse, - struct obstack *obstack); - /** * Get the estimated cycle count for @p irn. * @@ -459,11 +387,20 @@ struct arch_irn_ops_t { */ struct arch_isa_if_t { /** - * Initialize the isa interface. - * @param file_handle the file handle to write the output to - * @return a new isa instance + * Initializes the isa interface. This is necessary before calling any + * other functions from this interface. */ - arch_env_t *(*init)(FILE *file_handle); + void (*init)(void); + + /** + * Fress resources allocated by this isa interface. + */ + void (*finish)(void); + + /** + * Returns the frontend settings needed for this backend. + */ + const backend_params *(*get_params)(void); /** * lowers current program for target. See the documentation for @@ -472,89 +409,84 @@ struct arch_isa_if_t { void (*lower_for_target)(void); /** - * Free the isa instance. + * parse an assembler constraint part and set flags according to its nature + * advances the *c pointer to point to the last parsed character (so if you + * parse a single character don't advance c) */ - void (*done)(void *self); + asm_constraint_flags_t (*parse_asm_constraint)(const char **c); /** - * Called directly after initialization. Backend should handle all - * intrinsics here. + * returns true if the string is a valid clobbered (register) in this + * backend */ - void (*handle_intrinsics)(void); + int (*is_valid_clobber)(const char *clobber); /** - * Get the register class which shall be used to store a value of a given - * mode. - * @param self The this pointer. - * @param mode The mode in question. - * @return A register class which can hold values of the given mode. + * Start codegeneration + * @return a new isa instance */ - const arch_register_class_t *(*get_reg_class_for_mode)(const ir_mode *mode); + arch_env_t *(*begin_codegeneration)(void); /** - * Get the ABI restrictions for procedure calls. - * @param self The this pointer. - * @param call_type The call type of the method (procedure) in question. - * @param p The array of parameter locations to be filled. + * Free the isa instance. */ - void (*get_call_abi)(const void *self, ir_type *call_type, - be_abi_call_t *abi); + void (*end_codegeneration)(void *self); /** - * Get the necessary alignment for storing a register of given class. - * @param self The isa object. - * @param cls The register class. - * @return The alignment in bytes. + * Initialize the code generator for a graph + * @param irg A graph */ - int (*get_reg_class_alignment)(const arch_register_class_t *cls); + void (*init_graph)(ir_graph *irg); /** - * A "static" function, returns the frontend settings - * needed for this backend. + * Get the ABI restrictions for procedure calls. + * @param call_type The call type of the method (procedure) in question. + * @param p The array of parameter locations to be filled. */ - const backend_params *(*get_params)(void); + void (*get_call_abi)(ir_type *call_type, be_abi_call_t *abi); /** - * Return an ordered list of irgs where code should be generated for. - * If NULL is returned, all irg will be taken into account and they will be - * generated in an arbitrary order. - * @param self The isa object. - * @param irgs A flexible array ARR_F of length 0 where the backend can - * append the desired irgs. - * @return A flexible array ARR_F containing all desired irgs in the - * desired order. + * mark node as rematerialized */ - ir_graph **(*get_backend_irg_list)(const void *self, ir_graph ***irgs); + void (*mark_remat)(ir_node *node); /** - * mark node as rematerialized + * return node used as base in pic code addresses */ - void (*mark_remat)(ir_node *node); + ir_node* (*get_pic_base)(ir_graph *irg); /** - * parse an assembler constraint part and set flags according to its nature - * advances the *c pointer to point to the last parsed character (so if you - * parse a single character don't advance c) + * Create a spill instruction. We assume that spill instructions + * do not need any additional registers and do not affect cpu-flags in any + * way. + * Construct a sequence of instructions after @p after (the resulting nodes + * are already scheduled). + * Returns a mode_M value which is used as input for a reload instruction. */ - asm_constraint_flags_t (*parse_asm_constraint)(const char **c); + ir_node *(*new_spill)(ir_node *value, ir_node *after); /** - * returns true if the string is a valid clobbered (register) in this - * backend + * Create a reload instruction. We assume that reload instructions do not + * need any additional registers and do not affect cpu-flags in any way. + * Constructs a sequence of instruction before @p before (the resulting + * nodes are already scheduled). A rewiring of users is not performed in + * this function. + * Returns a value representing the restored value. */ - int (*is_valid_clobber)(const char *clobber); + ir_node *(*new_reload)(ir_node *value, ir_node *spilled_value, + ir_node *before); /** - * Initialize the code generator. - * @param irg A graph - * @return A newly created code generator. + * Checks if the given register is callee/caller saved. + * @deprecated, only necessary if backend still uses beabi functions */ - void (*init_graph)(ir_graph *irg); + int (*register_saved_by)(const arch_register_t *reg, int callee); /** - * return node used as base in pic code addresses + * Called directly after initialization. Backend should handle all + * intrinsics here. */ - ir_node* (*get_pic_base)(ir_graph *irg); + void (*handle_intrinsics)(void); /** * Called before abi introduce. @@ -571,40 +503,29 @@ struct arch_isa_if_t { */ void (*before_ra)(ir_graph *irg); - /** - * Called after register allocation. - */ - void (*after_ra)(ir_graph *irg); - /** * Called directly before done is called. This should be the last place * where the irg is modified. */ - void (*finish)(ir_graph *irg); + void (*finish_graph)(ir_graph *irg); /** * Called after everything happened. This call should emit the final * assembly code but avoid changing the irg. - * The code generator must also be de-allocated here. */ void (*emit)(ir_graph *irg); }; -#define arch_env_done(env) ((env)->impl->done(env)) +#define arch_env_end_codegeneration(env) ((env)->impl->end_codegeneration(env)) #define arch_env_handle_intrinsics(env) \ do { if((env)->impl->handle_intrinsics != NULL) (env)->impl->handle_intrinsics(); } while(0) -#define arch_env_get_reg_class_for_mode(env,mode) ((env)->impl->get_reg_class_for_mode((mode))) -#define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((env), (tp), (abi))) -#define arch_env_get_reg_class_alignment(env,cls) ((env)->impl->get_reg_class_alignment((cls))) -#define arch_env_get_params(env) ((env)->impl->get_params()) -#define arch_env_get_allowed_execution_units(env,irn) ((env)->impl->get_allowed_execution_units((irn))) -#define arch_env_get_machine(env) ((env)->impl->get_machine(env)) -#define arch_env_get_backend_irg_list(env,irgs) ((env)->impl->get_backend_irg_list((env), (irgs))) -#define arch_env_parse_asm_constraint(env,c) ((env)->impl->parse_asm_constraint((c)) -#define arch_env_is_valid_clobber(env,clobber) ((env)->impl->is_valid_clobber((clobber)) +#define arch_env_get_call_abi(env,tp,abi) ((env)->impl->get_call_abi((tp), (abi))) #define arch_env_mark_remat(env,node) \ do { if ((env)->impl->mark_remat != NULL) (env)->impl->mark_remat((node)); } while(0) +#define arch_env_new_spill(env,value,after) ((env)->impl->new_spill(value, after)) +#define arch_env_new_reload(env,value,spilled,before) ((env)->impl->new_reload(value, spilled, before)) + /** * ISA base class. */ @@ -616,12 +537,7 @@ struct arch_env_t { const arch_register_class_t *register_classes; /**< register classes */ const arch_register_t *sp; /**< The stack pointer register. */ const arch_register_t *bp; /**< The base pointer register. */ - const arch_register_class_t *link_class; /**< The static link pointer - register class. */ - int stack_dir; /**< -1 for decreasing, 1 for - increasing. */ int stack_alignment; /**< power of 2 stack alignment */ - const be_main_env_t *main_env; /**< the be main environment */ int spill_cost; /**< cost for a be_Spill node */ int reload_cost; /**< cost for a be_Reload node */ bool custom_abi : 1; /**< backend does all abi handling @@ -629,139 +545,77 @@ struct arch_env_t { stuff from beabi.h/.c */ }; -static inline unsigned arch_irn_get_n_outs(const ir_node *node) -{ - backend_info_t *info = be_get_info(node); - if (info->out_infos == NULL) - return 0; - - return (unsigned)ARR_LEN(info->out_infos); -} - -static inline const arch_irn_ops_t *get_irn_ops_simple(const ir_node *node) -{ - const ir_op *ops = get_irn_op(node); - const arch_irn_ops_t *be_ops = get_op_ops(ops)->be_ops; - assert(!is_Proj(node)); - return be_ops; -} - -static inline const arch_register_req_t *arch_get_register_req_out( - const ir_node *irn) -{ - int pos = 0; - backend_info_t *info; - - /* you have to query the Proj nodes for the constraints (or use - * arch_get_out_register_req. Querying a mode_T node and expecting - * arch_no_register_req is a bug in your code! */ - assert(get_irn_mode(irn) != mode_T); - - if (is_Proj(irn)) { - pos = get_Proj_proj(irn); - irn = get_Proj_pred(irn); - } - - info = be_get_info(irn); - if (info->out_infos == NULL) - return arch_no_register_req; - - return info->out_infos[pos].req; -} - static inline bool arch_irn_is_ignore(const ir_node *irn) { - const arch_register_req_t *req = arch_get_register_req_out(irn); - return !!(req->type & arch_register_req_type_ignore); + const arch_register_req_t *req = arch_get_irn_register_req(irn); + return arch_register_req_is(req, ignore); } static inline bool arch_irn_consider_in_reg_alloc( const arch_register_class_t *cls, const ir_node *node) { - const arch_register_req_t *req = arch_get_register_req_out(node); - return - req->cls == cls && - !(req->type & arch_register_req_type_ignore); + const arch_register_req_t *req = arch_get_irn_register_req(node); + return req->cls == cls && !arch_register_req_is(req, ignore); } -/** - * Get register constraints for an operand at position @p - */ -static inline const arch_register_req_t *arch_get_in_register_req( - const ir_node *node, int pos) -{ - const backend_info_t *info = be_get_info(node); - if (info->in_reqs == NULL) - return arch_no_register_req; - return info->in_reqs[pos]; -} +#define be_foreach_value(node, value, code) \ + do { \ + if (get_irn_mode(node) == mode_T) { \ + foreach_out_edge(node, node##__edge) { \ + ir_node *const value = get_edge_src_irn(node##__edge); \ + if (!is_Proj(value)) \ + continue; \ + code \ + } \ + } else { \ + ir_node *const value = node; \ + code \ + } \ + } while (0) /** - * Get register constraint for a produced result (the @p pos result) + * Iterate over all values defined by an instruction. + * Only looks at values in a certain register class where the requirements + * are not marked as ignore. + * Executes @p code for each definition. */ -static inline const arch_register_req_t *arch_get_out_register_req( - const ir_node *node, int pos) -{ - const backend_info_t *info = be_get_info(node); - if (info->out_infos == NULL) - return arch_no_register_req; - return info->out_infos[pos].req; -} +#define be_foreach_definition_(node, ccls, value, req, code) \ + be_foreach_value(node, value, \ + arch_register_req_t const *const req = arch_get_irn_register_req(value); \ + if (req->cls != ccls) \ + continue; \ + code \ + ) -static inline void arch_set_out_register_req(ir_node *node, int pos, - const arch_register_req_t *req) -{ - backend_info_t *info = be_get_info(node); - assert(pos < (int) arch_irn_get_n_outs(node)); - info->out_infos[pos].req = req; -} +#define be_foreach_definition(node, ccls, value, req, code) \ + be_foreach_definition_(node, ccls, value, req, \ + if (arch_register_req_is(req, ignore)) \ + continue; \ + code \ + ) -static inline void arch_set_in_register_reqs(ir_node *node, - const arch_register_req_t **in_reqs) -{ - backend_info_t *info = be_get_info(node); - info->in_reqs = in_reqs; -} +#define be_foreach_use(node, ccls, in_req, value, value_req, code) \ + do { \ + for (int i_ = 0, n_ = get_irn_arity(node); i_ < n_; ++i_) { \ + const arch_register_req_t *in_req = arch_get_irn_register_req_in(node, i_); \ + if (in_req->cls != ccls) \ + continue; \ + ir_node *value = get_irn_n(node, i_); \ + const arch_register_req_t *value_req = arch_get_irn_register_req(value); \ + if (value_req->type & arch_register_req_type_ignore) \ + continue; \ + code \ + } \ + } while (0) -static inline const arch_register_req_t **arch_get_in_register_reqs( +static inline const arch_register_class_t *arch_get_irn_reg_class( const ir_node *node) { - backend_info_t *info = be_get_info(node); - return info->in_reqs; + const arch_register_req_t *req = arch_get_irn_register_req(node); + return req->cls; } -/** - * Iterate over all values defined by an instruction. - * Only looks at values in a certain register class where the requirements - * are not marked as ignore. - * Executes @p code for each definition. - */ -#define be_foreach_definition_(node, cls, value, code) \ - do { \ - if (get_irn_mode(node) == mode_T) { \ - const ir_edge_t *edge_; \ - foreach_out_edge(node, edge_) { \ - const arch_register_req_t *req_; \ - value = get_edge_src_irn(edge_); \ - req_ = arch_get_register_req_out(value); \ - if (req_->cls != cls) \ - continue; \ - code \ - } \ - } else { \ - const arch_register_req_t *req_ = arch_get_register_req_out(node); \ - value = node; \ - if (req_->cls == cls) { \ - code \ - } \ - } \ - } while (0) - -#define be_foreach_definition(node, cls, value, code) \ - be_foreach_definition_(node, cls, value, \ - if (req_->type & arch_register_req_type_ignore) \ - continue; \ - code \ - ) +bool arch_reg_is_allocatable(const arch_register_req_t *req, + const arch_register_t *reg); #endif