X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Fbearch_arm.c;h=e4a350e1808604b7a179f28d6942148b5cee990b;hb=78a7ccdf4f405f1bd41e82f60b6e996a75f631fb;hp=943e7da706d9ed606316dfc3d1e44047b1b9794c;hpb=208809bd4713035389ccb0575b2592f52db6816b;p=libfirm

diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c
index 943e7da70..e4a350e18 100644
--- a/ir/be/arm/bearch_arm.c
+++ b/ir/be/arm/bearch_arm.c
@@ -1,14 +1,34 @@
-/* The main arm backend driver file. */
-/* $Id$ */
+/*
+ * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
+ *
+ * This file is part of libFirm.
+ *
+ * This file may be distributed and/or modified under the terms of the
+ * GNU General Public License version 2 as published by the Free Software
+ * Foundation and appearing in the file LICENSE.GPL included in the
+ * packaging of this file.
+ *
+ * Licensees holding valid libFirm Professional Edition licenses may use
+ * this file in accordance with the libFirm Commercial License.
+ * Agreement provided with the Software.
+ *
+ * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE.
+ */
 
+/**
+ * @file
+ * @brief   The main arm backend driver file.
+ * @author  Oliver Richter, Tobias Gneist
+ * @version $Id$
+ */
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
 
-#ifdef WITH_LIBCORE
 #include <libcore/lc_opts.h>
 #include <libcore/lc_opts_enum.h>
-#endif /* WITH_LIBCORE */
 
 #include "pseudo_irg.h"
 #include "irgwalk.h"
@@ -16,25 +36,29 @@
 #include "irprintf.h"
 #include "ircons.h"
 #include "irgmod.h"
-#include "lower_intrinsics.h"
+#include "irgopt.h"
+#include "lowering.h"
 
 #include "bitset.h"
 #include "debug.h"
 
-#include "../bearch.h"                /* the general register allocator interface */
+#include "../bearch_t.h"                /* the general register allocator interface */
 #include "../benode_t.h"
 #include "../belower.h"
 #include "../besched_t.h"
-#include "../be.h"
+#include "be.h"
 #include "../beabi.h"
 #include "../bemachine.h"
 #include "../beilpsched.h"
+#include "../bemodule.h"
+#include "../beirg_t.h"
+#include "../bespillslots.h"
+#include "../begnuas.h"
 
 #include "bearch_arm_t.h"
 
 #include "arm_new_nodes.h"           /* arm nodes interface */
 #include "gen_arm_regalloc_if.h"     /* the generated interface (register type and class defenitions) */
-#include "arm_gen_decls.h"           /* interface declaration emitter */
 #include "arm_transform.h"
 #include "arm_emitter.h"
 #include "arm_map_regs.h"
@@ -55,113 +79,69 @@ static set *cur_reg_set = NULL;
  *           |___/
  **************************************************/
 
-static ir_node *my_skip_proj(const ir_node *n) {
-	while (is_Proj(n))
-		n = get_Proj_pred(n);
-	return (ir_node *)n;
-}
-
 /**
  * Return register requirements for a arm node.
  * If the node returns a tuple (mode_T) then the proj's
  * will be asked for this information.
  */
-static const arch_register_req_t *arm_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
-	const arm_register_req_t *irn_req;
+static const
+arch_register_req_t *arm_get_irn_reg_req(const void *self, const ir_node *node,
+                                         int pos)
+{
 	long               node_pos = pos == -1 ? 0 : pos;
-	ir_mode           *mode     = get_irn_mode(irn);
-	FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
+	ir_mode           *mode     = get_irn_mode(node);
+	(void) self;
 
-	if (is_Block(irn) || mode == mode_X || mode == mode_M) {
-		DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
-		return NULL;
+	if (is_Block(node) || mode == mode_X) {
+		return arch_no_register_req;
 	}
 
 	if (mode == mode_T && pos < 0) {
-		DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
-		return NULL;
+		return arch_no_register_req;
 	}
 
-	DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
+	if (is_Proj(node)) {
+		if(mode == mode_M)
+			return arch_no_register_req;
 
-	if (is_Proj(irn)) {
-		/* in case of a proj, we need to get the correct OUT slot */
-		/* of the node corresponding to the proj number */
-		if (pos == -1) {
-			node_pos = arm_translate_proj_pos(irn);
-		}
-		else {
-			node_pos = pos;
+		if(pos >= 0) {
+			return arch_no_register_req;
 		}
 
-		irn = my_skip_proj(irn);
-
-		DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
+		node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
+		node     = skip_Proj_const(node);
 	}
 
 	/* get requirements for our own nodes */
-	if (is_arm_irn(irn)) {
+	if (is_arm_irn(node)) {
+		const arch_register_req_t *req;
 		if (pos >= 0) {
-			irn_req = get_arm_in_req(irn, pos);
-		}
-		else {
-			irn_req = get_arm_out_req(irn, node_pos);
-		}
-
-		DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
-
-		memcpy(req, &(irn_req->req), sizeof(*req));
-
-		if (arch_register_req_is(&(irn_req->req), should_be_same)) {
-			assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
-			req->other_same = get_irn_n(irn, irn_req->same_pos);
+			req = get_arm_in_req(node, pos);
+		} else {
+			req = get_arm_out_req(node, node_pos);
 		}
 
-		if (arch_register_req_is(&(irn_req->req), should_be_different)) {
-			assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
-			req->other_different = get_irn_n(irn, irn_req->different_pos);
-		}
+		return req;
 	}
-	/* get requirements for FIRM nodes */
-	else {
-		/* treat Phi like Const with default requirements */
-		if (is_Phi(irn)) {
-			DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
 
-			if (mode_is_float(mode)) {
-				memcpy(req, &(arm_default_req_arm_fpa.req), sizeof(*req));
-			}
-			else if (mode_is_int(mode) || mode_is_reference(mode)) {
-				memcpy(req, &(arm_default_req_arm_gp.req), sizeof(*req));
-			}
-			else if (mode == mode_T || mode == mode_M) {
-				DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
-				return NULL;
-			}
-			else {
-				assert(0 && "unsupported Phi-Mode");
-			}
-		}
-		else {
-			DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
-			req = NULL;
-		}
-	}
-
-	return req;
+	/* unknown should be transformed by now */
+	assert(!is_Unknown(node));
+	return arch_no_register_req;
 }
 
-static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
+static void arm_set_irn_reg(const void *self, ir_node *irn,
+                            const arch_register_t *reg)
+{
 	int pos = 0;
+	(void) self;
 
-	if (is_Proj(irn)) {
-
-		if (get_irn_mode(irn) == mode_X) {
-			return;
-		}
+	if (get_irn_mode(irn) == mode_X) {
+		return;
+	}
 
-		pos = arm_translate_proj_pos(irn);
-		irn = my_skip_proj(irn);
+	if (is_Proj(irn)) {
+		pos = get_Proj_proj(irn);
+		irn = skip_Proj(irn);
 	}
 
 	if (is_arm_irn(irn)) {
@@ -176,9 +156,12 @@ static void arm_set_irn_reg(const void *self, ir_node *irn, const arch_register_
 	}
 }
 
-static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *irn) {
+static const arch_register_t *arm_get_irn_reg(const void *self,
+                                              const ir_node *irn)
+{
 	int pos = 0;
 	const arch_register_t *reg = NULL;
+	(void) self;
 
 	if (is_Proj(irn)) {
 
@@ -186,8 +169,8 @@ static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *i
 			return NULL;
 		}
 
-		pos = arm_translate_proj_pos(irn);
-		irn = my_skip_proj(irn);
+		pos = get_Proj_proj(irn);
+		irn = skip_Proj_const(irn);
 	}
 
 	if (is_arm_irn(irn)) {
@@ -202,8 +185,10 @@ static const arch_register_t *arm_get_irn_reg(const void *self, const ir_node *i
 	return reg;
 }
 
-static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
-	irn = my_skip_proj(irn);
+static arch_irn_class_t arm_classify(const void *self, const ir_node *irn)
+{
+	(void) self;
+	irn = skip_Proj_const(irn);
 
 	if (is_cfop(irn)) {
 		return arch_irn_class_branch;
@@ -215,8 +200,10 @@ static arch_irn_class_t arm_classify(const void *self, const ir_node *irn) {
 	return 0;
 }
 
-static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
-	irn = my_skip_proj(irn);
+static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn)
+{
+	(void) self;
+	irn = skip_Proj_const(irn);
 
 	if (is_arm_irn(irn)) {
 		return get_arm_flags(irn);
@@ -228,12 +215,19 @@ static arch_irn_flags_t arm_get_flags(const void *self, const ir_node *irn) {
 	return 0;
 }
 
-static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn) {
+static ir_entity *arm_get_frame_entity(const void *self, const ir_node *irn)
+{
+	(void) self;
+	(void) irn;
 	/* TODO: return the entity assigned to the frame */
 	return NULL;
 }
 
-static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
+static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
+{
+	(void) self;
+	(void) irn;
+	(void) ent;
 	/* TODO: set the entity assigned to the frame */
 }
 
@@ -241,11 +235,18 @@ static void arm_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
  * This function is called by the generic backend to correct offsets for
  * nodes accessing the stack.
  */
-static void arm_set_stack_bias(const void *self, ir_node *irn, int bias) {
+static void arm_set_stack_bias(const void *self, ir_node *irn, int bias)
+{
+	(void) self;
+	(void) irn;
+	(void) bias;
 	/* TODO: correct offset if irn accesses the stack */
 }
 
-static int arm_get_sp_bias(const void *self, const ir_node *irn) {
+static int arm_get_sp_bias(const void *self, const ir_node *irn)
+{
+	(void) self;
+	(void) irn;
 	return 0;
 }
 
@@ -292,16 +293,28 @@ arm_irn_ops_t arm_irn_ops = {
 static void arm_prepare_graph(void *self) {
 	arm_code_gen_t *cg = self;
 
-	arm_register_transformers();
-	irg_walk_blkwise_graph(cg->irg, arm_move_consts, arm_transform_node, cg);
-}
+	/* transform nodes into assembler instructions */
+	arm_transform_graph(cg);
 
+	/* do local optimizations (mainly CSE) */
+	local_optimize_graph(cg->irg);
 
+	if (cg->dump)
+		be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
+
+	/* do code placement, to optimize the position of constants */
+	place_code(cg->irg);
+
+	if (cg->dump)
+		be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
+}
 
 /**
  * Called immediately before emit phase.
  */
-static void arm_finish_irg(void *self) {
+static void arm_finish_irg(void *self)
+{
+	(void) self;
 	/* TODO: - fix offsets for nodes accessing stack
 			 - ...
 	*/
@@ -311,14 +324,27 @@ static void arm_finish_irg(void *self) {
 /**
  * These are some hooks which must be filled but are probably not needed.
  */
-static void arm_before_sched(void *self) {
+static void arm_before_sched(void *self)
+{
+	(void) self;
 	/* Some stuff you need to do after scheduling but before register allocation */
 }
 
-static void arm_before_ra(void *self) {
+static void arm_before_ra(void *self)
+{
+	(void) self;
 	/* Some stuff you need to do immediately after register allocation */
 }
 
+/**
+ * We transform Spill and Reload here. This needs to be done before
+ * stack biasing otherwise we would miss the corrected offset for these nodes.
+ */
+static void arm_after_ra(void *self)
+{
+	arm_code_gen_t *cg = self;
+	be_coalesce_spillslots(cg->birg);
+}
 
 /**
  * Emits the code, closes the output file and frees
@@ -326,16 +352,9 @@ static void arm_before_ra(void *self) {
  */
 static void arm_emit_and_done(void *self) {
 	arm_code_gen_t *cg = self;
-	ir_graph           *irg = cg->irg;
-	FILE               *out = cg->isa->out;
+	ir_graph       *irg = cg->irg;
 
-	if (cg->emit_decls) {
-		arm_gen_decls(out);
-		cg->emit_decls = 0;
-	}
-
-	dump_ir_block_graph_sched(irg, "-arm-finished");
-	arm_gen_routine(out, irg, cg);
+	arm_gen_routine(cg, irg);
 
 	cur_reg_set = NULL;
 
@@ -350,7 +369,7 @@ static void arm_emit_and_done(void *self) {
  *
  * Handle some special cases here:
  * 1.) A constant: simply split into two
- * 2.) A load: siply split into two
+ * 2.) A load: simply split into two
  */
 static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
                                    ir_node **resH, ir_node **resL) {
@@ -395,9 +414,12 @@ static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem,
  *
  * Handle some special cases here:
  * 1.) A constant: simply move
- * 2.) A load: siply load
+ * 2.) A load: simply load
  */
-static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
+static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg)
+{
+	(void) bl;
+
 	if (is_Const(arg)) {
 		tarval *tv = get_Const_tarval(arg);
 		unsigned v;
@@ -426,7 +448,7 @@ static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) {
 static void handle_calls(ir_node *call, void *env)
 {
 	arm_code_gen_t *cg = env;
-	int i, j, n, size, idx, flag, n_param, n_res;
+	int i, j, n, size, idx, flag, n_param, n_res, first_variadic;
 	ir_type *mtp, *new_mtd, *new_tp[5];
 	ir_node *new_in[5], **in;
 	ir_node *bl;
@@ -505,7 +527,9 @@ static void handle_calls(ir_node *call, void *env)
 		set_method_res_type(new_mtd, i, get_method_res_type(mtp, i));
 
 	set_method_calling_convention(new_mtd, get_method_calling_convention(mtp));
-	set_method_first_variadic_param_index(new_mtd, get_method_first_variadic_param_index(mtp));
+	first_variadic = get_method_first_variadic_param_index(mtp);
+	if (first_variadic >= 0)
+		set_method_first_variadic_param_index(new_mtd, first_variadic);
 
 	if (is_lowered_type(mtp)) {
 		mtp = get_associated_type(mtp);
@@ -537,6 +561,7 @@ static void arm_before_abi(void *self) {
 	irg_walk_graph(cg->irg, NULL, handle_calls, cg);
 }
 
+/* forward */
 static void *arm_cg_init(be_irg_t *birg);
 
 static const arch_code_generator_if_t arm_code_gen_if = {
@@ -546,7 +571,7 @@ static const arch_code_generator_if_t arm_code_gen_if = {
 	NULL,               /* spill */
 	arm_before_sched,   /* before scheduling hook */
 	arm_before_ra,      /* before register allocation hook */
-	NULL,               /* after register allocation */
+	arm_after_ra,
 	arm_finish_irg,
 	arm_emit_and_done,
 };
@@ -565,24 +590,20 @@ static void *arm_cg_init(be_irg_t *birg) {
 	}
 
 	cg = xmalloc(sizeof(*cg));
-	cg->impl     = &arm_code_gen_if;
-	cg->irg      = birg->irg;
-	cg->reg_set  = new_set(arm_cmp_irn_reg_assoc, 1024);
-	cg->arch_env = birg->main_env->arch_env;
-	cg->isa      = isa;
-	cg->birg     = birg;
-	cg->int_tp   = int_tp;
-	cg->have_fp  = 0;
+	cg->impl         = &arm_code_gen_if;
+	cg->irg          = birg->irg;
+	cg->reg_set      = new_set(arm_cmp_irn_reg_assoc, 1024);
+	cg->arch_env     = birg->main_env->arch_env;
+	cg->isa          = isa;
+	cg->birg         = birg;
+	cg->int_tp       = int_tp;
+	cg->have_fp_insn = 0;
+	cg->unknown_gp   = NULL;
+	cg->unknown_fpa  = NULL;
+	cg->dump         = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
 
 	FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg");
 
-	isa->num_codegens++;
-
-	if (isa->num_codegens > 1)
-		cg->emit_decls = 0;
-	else
-		cg->emit_decls = 1;
-
 	cur_reg_set = cg->reg_set;
 
 	arm_irn_ops.cg = cg;
@@ -600,114 +621,122 @@ static void *arm_cg_init(be_irg_t *birg) {
  * to runtime calls.
  */
 static void arm_handle_intrinsics(void) {
-  ir_type *tp, *int_tp, *uint_tp;
-  i_record records[8];
-  int n_records = 0;
+	ir_type *tp, *int_tp, *uint_tp;
+	i_record records[8];
+	int n_records = 0;
 
 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
 
-  int_tp  = new_type_primitive(ID("int"), mode_Is);
-  uint_tp = new_type_primitive(ID("uint"), mode_Iu);
+	int_tp  = new_type_primitive(ID("int"), mode_Is);
+	uint_tp = new_type_primitive(ID("uint"), mode_Iu);
 
 	/* ARM has neither a signed div instruction ... */
-  {
-    runtime_rt rt_Div;
-    i_instr_record *map_Div = &records[n_records++].i_instr;
-
-    tp = new_type_method(ID("rt_iDiv"), 2, 1);
-    set_method_param_type(tp, 0, int_tp);
-    set_method_param_type(tp, 1, int_tp);
-    set_method_res_type(tp, 0, int_tp);
-
-    rt_Div.ent             = new_entity(get_glob_type(), ID("__divsi3"), tp);
-    rt_Div.mode            = mode_T;
-    rt_Div.mem_proj_nr     = pn_Div_M;
-    rt_Div.exc_proj_nr     = pn_Div_X_except;
-    rt_Div.exc_mem_proj_nr = pn_Div_M;
-    rt_Div.res_proj_nr     = pn_Div_res;
-
-    set_entity_visibility(rt_Div.ent, visibility_external_allocated);
-
-    map_Div->kind     = INTRINSIC_INSTR;
-    map_Div->op       = op_Div;
-    map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
-    map_Div->ctx      = &rt_Div;
-  }
-	/* ... nor a signed div instruction ... */
-  {
-    runtime_rt rt_Div;
-    i_instr_record *map_Div = &records[n_records++].i_instr;
-
-    tp = new_type_method(ID("rt_uDiv"), 2, 1);
-    set_method_param_type(tp, 0, uint_tp);
-    set_method_param_type(tp, 1, uint_tp);
-    set_method_res_type(tp, 0, uint_tp);
-
-    rt_Div.ent             = new_entity(get_glob_type(), ID("__udivsi3"), tp);
-    rt_Div.mode            = mode_T;
-    rt_Div.mem_proj_nr     = pn_Div_M;
-    rt_Div.exc_proj_nr     = pn_Div_X_except;
-    rt_Div.exc_mem_proj_nr = pn_Div_M;
-    rt_Div.res_proj_nr     = pn_Div_res;
-
-    set_entity_visibility(rt_Div.ent, visibility_external_allocated);
-
-    map_Div->kind     = INTRINSIC_INSTR;
-    map_Div->op       = op_Div;
-    map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
-    map_Div->ctx      = &rt_Div;
-  }
+	{
+		runtime_rt rt_Div;
+		i_instr_record *map_Div = &records[n_records++].i_instr;
+
+		tp = new_type_method(ID("rt_iDiv"), 2, 1);
+		set_method_param_type(tp, 0, int_tp);
+		set_method_param_type(tp, 1, int_tp);
+		set_method_res_type(tp, 0, int_tp);
+
+		rt_Div.ent             = new_entity(get_glob_type(), ID("__divsi3"), tp);
+		rt_Div.mode            = mode_T;
+		rt_Div.res_mode        = mode_Is;
+		rt_Div.mem_proj_nr     = pn_Div_M;
+		rt_Div.regular_proj_nr = pn_Div_X_regular;
+		rt_Div.exc_proj_nr     = pn_Div_X_except;
+		rt_Div.exc_mem_proj_nr = pn_Div_M;
+		rt_Div.res_proj_nr     = pn_Div_res;
+
+		set_entity_visibility(rt_Div.ent, visibility_external_allocated);
+
+		map_Div->kind     = INTRINSIC_INSTR;
+		map_Div->op       = op_Div;
+		map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+		map_Div->ctx      = &rt_Div;
+	}
+	/* ... nor an unsigned div instruction ... */
+	{
+		runtime_rt rt_Div;
+		i_instr_record *map_Div = &records[n_records++].i_instr;
+
+		tp = new_type_method(ID("rt_uDiv"), 2, 1);
+		set_method_param_type(tp, 0, uint_tp);
+		set_method_param_type(tp, 1, uint_tp);
+		set_method_res_type(tp, 0, uint_tp);
+
+		rt_Div.ent             = new_entity(get_glob_type(), ID("__udivsi3"), tp);
+		rt_Div.mode            = mode_T;
+		rt_Div.res_mode        = mode_Iu;
+		rt_Div.mem_proj_nr     = pn_Div_M;
+		rt_Div.regular_proj_nr = pn_Div_X_regular;
+		rt_Div.exc_proj_nr     = pn_Div_X_except;
+		rt_Div.exc_mem_proj_nr = pn_Div_M;
+		rt_Div.res_proj_nr     = pn_Div_res;
+
+		set_entity_visibility(rt_Div.ent, visibility_external_allocated);
+
+		map_Div->kind     = INTRINSIC_INSTR;
+		map_Div->op       = op_Div;
+		map_Div->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+		map_Div->ctx      = &rt_Div;
+	}
 	/* ... nor a signed mod instruction ... */
-  {
-    runtime_rt rt_Mod;
-    i_instr_record *map_Mod = &records[n_records++].i_instr;
-
-    tp = new_type_method(ID("rt_iMod"), 2, 1);
-    set_method_param_type(tp, 0, int_tp);
-    set_method_param_type(tp, 1, int_tp);
-    set_method_res_type(tp, 0, int_tp);
-
-    rt_Mod.ent             = new_entity(get_glob_type(), ID("__modsi3"), tp);
-    rt_Mod.mode            = mode_T;
-    rt_Mod.mem_proj_nr     = pn_Mod_M;
-    rt_Mod.exc_proj_nr     = pn_Mod_X_except;
-    rt_Mod.exc_mem_proj_nr = pn_Mod_M;
-    rt_Mod.res_proj_nr     = pn_Mod_res;
-
-    set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
-
-    map_Mod->kind     = INTRINSIC_INSTR;
-    map_Mod->op       = op_Mod;
-    map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
-    map_Mod->ctx      = &rt_Mod;
-  }
-	/* ... nor a unsigned mod. */
-  {
-    runtime_rt rt_Mod;
-    i_instr_record *map_Mod = &records[n_records++].i_instr;
-
-    tp = new_type_method(ID("rt_uMod"), 2, 1);
-    set_method_param_type(tp, 0, uint_tp);
-    set_method_param_type(tp, 1, uint_tp);
-    set_method_res_type(tp, 0, uint_tp);
-
-    rt_Mod.ent             = new_entity(get_glob_type(), ID("__umodsi3"), tp);
-    rt_Mod.mode            = mode_T;
-    rt_Mod.mem_proj_nr     = pn_Mod_M;
-    rt_Mod.exc_proj_nr     = pn_Mod_X_except;
-    rt_Mod.exc_mem_proj_nr = pn_Mod_M;
-    rt_Mod.res_proj_nr     = pn_Mod_res;
-
-    set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
-
-    map_Mod->kind     = INTRINSIC_INSTR;
-    map_Mod->op       = op_Mod;
-    map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
-    map_Mod->ctx      = &rt_Mod;
-  }
-
-  if (n_records > 0)
-    lower_intrinsics(records, n_records);
+	{
+		runtime_rt rt_Mod;
+		i_instr_record *map_Mod = &records[n_records++].i_instr;
+
+		tp = new_type_method(ID("rt_iMod"), 2, 1);
+		set_method_param_type(tp, 0, int_tp);
+		set_method_param_type(tp, 1, int_tp);
+		set_method_res_type(tp, 0, int_tp);
+
+		rt_Mod.ent             = new_entity(get_glob_type(), ID("__modsi3"), tp);
+		rt_Mod.mode            = mode_T;
+		rt_Mod.res_mode        = mode_Is;
+		rt_Mod.mem_proj_nr     = pn_Mod_M;
+		rt_Mod.regular_proj_nr = pn_Mod_X_regular;
+		rt_Mod.exc_proj_nr     = pn_Mod_X_except;
+		rt_Mod.exc_mem_proj_nr = pn_Mod_M;
+		rt_Mod.res_proj_nr     = pn_Mod_res;
+
+		set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
+
+		map_Mod->kind     = INTRINSIC_INSTR;
+		map_Mod->op       = op_Mod;
+		map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+		map_Mod->ctx      = &rt_Mod;
+	}
+	/* ... nor an unsigned mod. */
+	{
+		runtime_rt rt_Mod;
+		i_instr_record *map_Mod = &records[n_records++].i_instr;
+
+		tp = new_type_method(ID("rt_uMod"), 2, 1);
+		set_method_param_type(tp, 0, uint_tp);
+		set_method_param_type(tp, 1, uint_tp);
+		set_method_res_type(tp, 0, uint_tp);
+
+		rt_Mod.ent             = new_entity(get_glob_type(), ID("__umodsi3"), tp);
+		rt_Mod.mode            = mode_T;
+		rt_Mod.res_mode        = mode_Iu;
+		rt_Mod.mem_proj_nr     = pn_Mod_M;
+		rt_Mod.regular_proj_nr = pn_Mod_X_regular;
+		rt_Mod.exc_proj_nr     = pn_Mod_X_except;
+		rt_Mod.exc_mem_proj_nr = pn_Mod_M;
+		rt_Mod.res_proj_nr     = pn_Mod_res;
+
+		set_entity_visibility(rt_Mod.ent, visibility_external_allocated);
+
+		map_Mod->kind     = INTRINSIC_INSTR;
+		map_Mod->op       = op_Mod;
+		map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
+		map_Mod->ctx      = &rt_Mod;
+	}
+
+	if (n_records > 0)
+		lower_intrinsics(records, n_records);
 }
 
 /*****************************************************************
@@ -721,15 +750,19 @@ static void arm_handle_intrinsics(void) {
  *****************************************************************/
 
 static arm_isa_t arm_isa_template = {
-	&arm_isa_if,           /* isa interface */
-	&arm_gp_regs[REG_SP],  /* stack pointer */
-	&arm_gp_regs[REG_R11], /* base pointer */
-	-1,                    /* stack direction */
-	0,                     /* number of codegenerator objects */
+	{
+		&arm_isa_if,           /* isa interface */
+		&arm_gp_regs[REG_SP],  /* stack pointer */
+		&arm_gp_regs[REG_R11], /* base pointer */
+		-1,                    /* stack direction */
+		NULL,                  /* main environment */
+		7,                     /* spill costs */
+		5,                     /* reload costs */
+	},
 	0,                     /* use generic register names instead of SP, LR, PC */
-	NULL,                  /* current code generator */
-	NULL,                  /* output file */
 	ARM_FPU_ARCH_FPE,      /* FPU architecture */
+	NULL,                  /* current code generator */
+	NULL_EMITTER,          /* emitter environment */
 };
 
 /**
@@ -745,21 +778,20 @@ static void *arm_init(FILE *file_handle) {
 	isa = xmalloc(sizeof(*isa));
 	memcpy(isa, &arm_isa_template, sizeof(*isa));
 
-	arm_register_init(isa);
-	if (isa->gen_reg_names) {
-		/* patch register names */
-		arm_gp_regs[REG_R11].name = "r11";
-		arm_gp_regs[REG_SP].name  = "r13";
-		arm_gp_regs[REG_LR].name  = "r14";
-		arm_gp_regs[REG_PC].name  = "r15";
-	}
+	arm_register_init();
 
 	isa->cg  = NULL;
-	isa->out = file_handle;
+	be_emit_init_env(&isa->emit, file_handle);
 
 	arm_create_opcodes();
+	arm_register_copy_attr_func();
 	arm_handle_intrinsics();
-	arm_switch_section(NULL, NO_SECTION);
+
+	/* we mark referenced global entities, so we can only emit those which
+	 * are actually referenced. (Note: you mustn't use the type visited flag
+	 * elsewhere in the backend)
+	 */
+	inc_master_type_visited();
 
 	inited = 1;
 	return isa;
@@ -768,9 +800,14 @@ static void *arm_init(FILE *file_handle) {
 
 
 /**
- * frees the ISA structure.
+ * Closes the output file and frees the ISA structure.
  */
 static void arm_done(void *self) {
+	arm_isa_t *isa = self;
+
+	be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
+
+	be_emit_destroy_env(&isa->emit);
 	free(self);
 }
 
@@ -784,13 +821,16 @@ static void arm_done(void *self) {
 static int arm_get_n_reg_class(const void *self) {
 	const arm_isa_t *isa = self;
 
-	return isa->cg->have_fp ? 2 : 1;
+	/* ARGH! is called BEFORE transform */
+	return 2;
+	return isa->cg->have_fp_insn ? 2 : 1;
 }
 
 /**
  * Return the register class with requested index.
  */
 static const arch_register_class_t *arm_get_reg_class(const void *self, int i) {
+	(void) self;
 	return i == 0 ? &arm_reg_classes[CLASS_arm_gp] : &arm_reg_classes[CLASS_arm_fpa];
 }
 
@@ -872,9 +912,6 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
 //	ir_node *regs[16];
 //	int n_regs = 0;
 	arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp];
-	static const arm_register_req_t *fp_req[] = {
-		&arm_default_req_arm_gp_r11
-	};
 
 	ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp);
 	ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]);
@@ -901,23 +938,25 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
 //		set_arm_req_out(sp, &arm_default_req_arm_gp_sp, 0);
 //		arch_set_irn_register(env->arch_env, sp, env->isa->sp);
 	store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
-		set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
-//		arch_set_irn_register(env->arch_env, store, env->isa->sp);
+	// TODO
+	// set_arm_req_out(store, &arm_default_req_arm_gp_sp, 0);
+	// arch_set_irn_register(env->arch_env, store, env->isa->sp);
 
 	sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr);
-		arch_set_irn_register(env->arch_env, sp, env->isa->sp);
+	arch_set_irn_register(env->arch_env, sp, env->isa->sp);
 	*mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
 
 	keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
-		be_node_set_reg_class(keep, 1, gp);
-		arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
-		be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
+	be_node_set_reg_class(keep, 1, gp);
+	arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]);
+	be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
 
 	fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp),
 	                      new_tarval_from_long(4, get_irn_mode(fp)));
-		set_arm_req_out_all(fp, fp_req);
-		//set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
-		arch_set_irn_register(env->arch_env, fp, env->isa->bp);
+	// TODO...
+	//set_arm_req_out_all(fp, fp_req);
+	//set_arm_req_out(fp, &arm_default_req_arm_gp_r11, 0);
+	arch_set_irn_register(env->arch_env, fp, env->isa->bp);
 
 // 	be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R0], r0);
 // 	be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R1], r1);
@@ -938,11 +977,8 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
 	ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
 	ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]);
 	ir_node	*curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]);
-	static const arm_register_req_t *sub12_req[] = {
-		&arm_default_req_arm_gp_sp
-	};
 
-//	TODO: Activate Omit fp in epilogue
+	// TODO: Activate Omit fp in epilogue
 	if(env->flags.try_omit_fp) {
 		curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
 		add_irn_dep(curr_sp, *mem);
@@ -955,17 +991,20 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
 		curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
 		arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]);
 		be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
+		be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
 	} else {
 		ir_node *sub12_node;
 		ir_node *load_node;
 		tarval *tv = new_tarval_from_long(12,mode_Iu);
 		sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, tv);
-		set_arm_req_out_all(sub12_node, sub12_req);
+		// FIXME
+		//set_arm_req_out_all(sub12_node, sub12_req);
 		arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp);
 		load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem );
-		set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
-		set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
-		set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
+		// FIXME
+		//set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0);
+		//set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1);
+		//set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2);
 		curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0);
 		curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1);
 		curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2);
@@ -1024,14 +1063,34 @@ void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi
 			be_abi_call_param_stack(abi, i, 4, 0, 0);
 	}
 
-	/* default: return value is in R0 resp. F0 */
-	assert(get_method_n_ress(method_type) < 2);
-	if (get_method_n_ress(method_type) > 0) {
+	/* set return registers */
+	n = get_method_n_ress(method_type);
+
+	assert(n <= 2 && "more than two results not supported");
+
+	/* In case of 64bit returns, we will have two 32bit values */
+	if (n == 2) {
+		tp   = get_method_res_type(method_type, 0);
+		mode = get_type_mode(tp);
+
+		assert(!mode_is_float(mode) && "two FP results not supported");
+
+		tp   = get_method_res_type(method_type, 1);
+		mode = get_type_mode(tp);
+
+		assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
+
+		be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]);
+		be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]);
+	} else if (n == 1) {
+		const arch_register_t *reg;
+
 		tp   = get_method_res_type(method_type, 0);
+		assert(is_atomic_type(tp));
 		mode = get_type_mode(tp);
 
-		be_abi_call_res_reg(abi, 0,
-			mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]);
+		reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0];
+		be_abi_call_res_reg(abi, 0, reg);
 	}
 }
 
@@ -1048,7 +1107,10 @@ const arch_irn_handler_t *arm_get_irn_handler(const void *self) {
 }
 
 int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) {
-	return is_arm_irn(irn);
+	if(!is_arm_irn(irn))
+		return -1;
+
+	return 1;
 }
 
 /**
@@ -1077,8 +1139,8 @@ static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self)
  * Returns the necessary byte alignment for storing a register of given class.
  */
 static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
-	ir_mode *mode = arch_register_class_mode(cls);
-	return get_mode_size_bytes(mode);
+	/* ARM is a 32 bit CPU, no need for other alignment */
+	return 4;
 }
 
 static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) {
@@ -1093,32 +1155,39 @@ static const be_machine_t *arm_get_machine(const void *self) {
 	return NULL;
 }
 
+/**
+ * Return irp irgs in the desired order.
+ */
+static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) {
+	return NULL;
+}
+
 /**
  * Returns the libFirm configuration parameter for this backend.
  */
 static const backend_params *arm_get_libfirm_params(void) {
 	static arch_dep_params_t ad = {
 		1,  /* allow subs */
-		0,	/* Muls are fast enough on ARM */
-		31, /* shift would be ok */
+		1,	/* Muls are fast enough on ARM but ... */
+		1,  /* ... one shift would be possible better */
 		0,  /* SMUL is needed, only in Arch M*/
 		0,  /* UMUL is needed, only in Arch M */
 		32, /* SMUL & UMUL available for 32 bit */
 	};
 	static backend_params p = {
+		1,     /* need dword lowering */
+		0,     /* don't support inline assembler yet */
 		NULL,  /* no additional opcodes */
 		NULL,  /* will be set later */
-		1,     /* need dword lowering */
 		NULL,  /* but yet no creator function */
 		NULL,  /* context for create_intrinsic_fkt */
+		NULL,  /* no if conversion settings */
 	};
 
 	p.dep_param = &ad;
 	return &p;
 }
 
-#ifdef WITH_LIBCORE
-
 /* fpu set architectures. */
 static const lc_opt_enum_int_items_t arm_fpu_items[] = {
 	{ "softfloat", ARM_FPU_ARCH_SOFTFLOAT },
@@ -1140,21 +1209,6 @@ static const lc_opt_table_entry_t arm_options[] = {
 	{ NULL }
 };
 
-/**
- * Register command line options for the ARM backend.
- *
- * Options so far:
- *
- * arm-fpuunit=unit     select the floating point unit
- * arm-gen_reg_names    use generic register names instead of SP, LR, PC
- */
-static void arm_register_options(lc_opt_entry_t *ent)
-{
-	lc_opt_entry_t *be_grp_arm = lc_opt_get_grp(ent, "arm");
-	lc_opt_add_table(be_grp_arm, arm_options);
-}
-#endif /* WITH_LIBCORE */
-
 const arch_isa_if_t arm_isa_if = {
 	arm_init,
 	arm_done,
@@ -1170,7 +1224,19 @@ const arch_isa_if_t arm_isa_if = {
 	arm_get_libfirm_params,
 	arm_get_allowed_execution_units,
 	arm_get_machine,
-#ifdef WITH_LIBCORE
-	arm_register_options
-#endif
+	arm_get_irg_list,
 };
+
+void be_init_arch_arm(void)
+{
+	lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
+	lc_opt_entry_t *arm_grp = lc_opt_get_grp(be_grp, "arm");
+
+	lc_opt_add_table(arm_grp, arm_options);
+
+	be_register_isa_if("arm", &arm_isa_if);
+
+	arm_init_transform();
+}
+
+BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);