X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Fbearch_arm.c;h=caaa8e5567e711751efc82b82dfaceace05872e4;hb=ad9464a5db0b98cb926aae609abe84db70b74291;hp=63dcbed260ee033ee2fa267654b2f27cf5558904;hpb=c23b55879df97f49fc6f1e95651f9f28a980b620;p=libfirm diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c index 63dcbed26..caaa8e556 100644 --- a/ir/be/arm/bearch_arm.c +++ b/ir/be/arm/bearch_arm.c @@ -20,17 +20,14 @@ /** * @file * @brief The main arm backend driver file. - * @author Oliver Richter, Tobias Gneist + * @author Matthias Braun, Oliver Richter, Tobias Gneist * @version $Id$ */ -#ifdef HAVE_CONFIG_H #include "config.h" -#endif #include "lc_opts.h" #include "lc_opts_enum.h" -#include "pseudo_irg.h" #include "irgwalk.h" #include "irprog.h" #include "irprintf.h" @@ -38,213 +35,83 @@ #include "irgmod.h" #include "irgopt.h" #include "iroptimize.h" +#include "irdump.h" #include "lowering.h" +#include "error.h" #include "bitset.h" #include "debug.h" +#include "array_t.h" #include "irtools.h" -#include "../bearch_t.h" /* the general register allocator interface */ -#include "../benode_t.h" +#include "../bearch.h" +#include "../benode.h" #include "../belower.h" -#include "../besched_t.h" +#include "../besched.h" #include "be.h" -#include "../beabi.h" #include "../bemachine.h" #include "../beilpsched.h" #include "../bemodule.h" -#include "../beirg_t.h" +#include "../beirg.h" #include "../bespillslots.h" #include "../begnuas.h" +#include "../belistsched.h" +#include "../beflags.h" #include "bearch_arm_t.h" -#include "arm_new_nodes.h" /* arm nodes interface */ -#include "gen_arm_regalloc_if.h" /* the generated interface (register type and class defenitions) */ +#include "arm_new_nodes.h" +#include "gen_arm_regalloc_if.h" #include "arm_transform.h" +#include "arm_optimize.h" #include "arm_emitter.h" #include "arm_map_regs.h" -#define DEBUG_MODULE "firm.be.arm.isa" - -/* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */ -static set *cur_reg_set = NULL; - -/************************************************** - * _ _ _ __ - * | | | (_)/ _| - * _ __ ___ __ _ __ _| | | ___ ___ _| |_ - * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _| - * | | | __/ (_| | | (_| | | | (_) | (__ | | | - * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_| - * __/ | - * |___/ - **************************************************/ - -/** - * Return register requirements for a arm node. - * If the node returns a tuple (mode_T) then the proj's - * will be asked for this information. - */ -static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node, - int pos) -{ - long node_pos = pos == -1 ? 0 : pos; - ir_mode *mode = get_irn_mode(node); - - if (is_Block(node) || mode == mode_X) { - return arch_no_register_req; - } - - if (mode == mode_T && pos < 0) { - return arch_no_register_req; - } - - if (is_Proj(node)) { - if(mode == mode_M) - return arch_no_register_req; - - if(pos >= 0) { - return arch_no_register_req; - } - - node_pos = (pos == -1) ? get_Proj_proj(node) : pos; - node = skip_Proj_const(node); - } - - /* get requirements for our own nodes */ - if (is_arm_irn(node)) { - const arch_register_req_t *req; - if (pos >= 0) { - req = get_arm_in_req(node, pos); - } else { - req = get_arm_out_req(node, node_pos); - } - - return req; - } - - /* unknown should be transformed by now */ - assert(!is_Unknown(node)); - return arch_no_register_req; -} - -static void arm_set_irn_reg(ir_node *irn, const arch_register_t *reg) -{ - int pos = 0; - - if (get_irn_mode(irn) == mode_X) { - return; - } - - if (is_Proj(irn)) { - pos = get_Proj_proj(irn); - irn = skip_Proj(irn); - } - - if (is_arm_irn(irn)) { - const arch_register_t **slots; - - slots = get_arm_slots(irn); - slots[pos] = reg; - } - else { - /* here we set the registers for the Phi nodes */ - arm_set_firm_reg(irn, reg, cur_reg_set); - } -} - -static const arch_register_t *arm_get_irn_reg(const ir_node *irn) -{ - int pos = 0; - const arch_register_t *reg = NULL; - - if (is_Proj(irn)) { - - if (get_irn_mode(irn) == mode_X) { - return NULL; - } - - pos = get_Proj_proj(irn); - irn = skip_Proj_const(irn); - } - - if (is_arm_irn(irn)) { - const arch_register_t **slots; - slots = get_arm_slots(irn); - reg = slots[pos]; - } - else { - reg = arm_get_firm_reg(irn, cur_reg_set); - } - - return reg; -} - static arch_irn_class_t arm_classify(const ir_node *irn) { - irn = skip_Proj_const(irn); - - if (is_cfop(irn)) { - return arch_irn_class_branch; - } - else if (is_arm_irn(irn)) { - return arch_irn_class_normal; - } - + (void) irn; + /* TODO: we should mark reload/spill instructions and classify them here */ return 0; } -static arch_irn_flags_t arm_get_flags(const ir_node *irn) +static ir_entity *arm_get_frame_entity(const ir_node *irn) { - arch_irn_flags_t flags = arch_irn_flags_none; + const arm_attr_t *attr = get_arm_attr_const(irn); - if(is_Unknown(irn)) { - return arch_irn_flags_ignore; + if (is_arm_FrameAddr(irn)) { + const arm_SymConst_attr_t *attr = get_irn_generic_attr_const(irn); + return attr->entity; } - - if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) { - ir_node *pred = get_Proj_pred(irn); - if (is_arm_irn(pred)) { - flags = get_arm_out_flags(pred, get_Proj_proj(irn)); + if (attr->is_load_store) { + const arm_load_store_attr_t *load_store_attr + = get_arm_load_store_attr_const(irn); + if (load_store_attr->is_frame_entity) { + return load_store_attr->entity; } - irn = pred; } - - if (is_arm_irn(irn)) { - flags |= get_arm_flags(irn); - } - - return flags; -} - -static ir_entity *arm_get_frame_entity(const ir_node *irn) -{ - (void) irn; - /* TODO: return the entity assigned to the frame */ return NULL; } -static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) -{ - (void) irn; - (void) ent; - /* TODO: set the entity assigned to the frame */ -} - /** * This function is called by the generic backend to correct offsets for * nodes accessing the stack. */ static void arm_set_stack_bias(ir_node *irn, int bias) { - (void) irn; - (void) bias; - /* TODO: correct offset if irn accesses the stack */ + if (is_arm_FrameAddr(irn)) { + arm_SymConst_attr_t *attr = get_irn_generic_attr(irn); + attr->fp_offset += bias; + } else { + arm_load_store_attr_t *attr = get_arm_load_store_attr(irn); + assert(attr->base.is_load_store); + attr->offset += bias; + } } static int arm_get_sp_bias(const ir_node *irn) { + /* We don't have any nodes changing the stack pointer. + We probably want to support post-/pre increment/decrement later */ (void) irn; return 0; } @@ -252,13 +119,8 @@ static int arm_get_sp_bias(const ir_node *irn) /* fill register allocator interface */ static const arch_irn_ops_t arm_irn_ops = { - arm_get_irn_reg_req, - arm_set_irn_reg, - arm_get_irn_reg, arm_classify, - arm_get_flags, arm_get_frame_entity, - arm_set_frame_entity, arm_set_stack_bias, arm_get_sp_bias, NULL, /* get_inverse */ @@ -267,342 +129,161 @@ static const arch_irn_ops_t arm_irn_ops = { NULL, /* perform_memory_operand */ }; -/************************************************** - * _ _ __ - * | | (_)/ _| - * ___ ___ __| | ___ __ _ ___ _ __ _| |_ - * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _| - * | (_| (_) | (_| | __/ (_| | __/ | | | | | | - * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_| - * __/ | - * |___/ - **************************************************/ - /** * Transforms the standard Firm graph into * a ARM firm graph. */ -static void arm_prepare_graph(void *self) { - arm_code_gen_t *cg = self; - +static void arm_prepare_graph(ir_graph *irg) +{ /* transform nodes into assembler instructions */ - arm_transform_graph(cg); + arm_transform_graph(irg); /* do local optimizations (mainly CSE) */ - local_optimize_graph(cg->irg); - - if (cg->dump) - be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched); + local_optimize_graph(irg); /* do code placement, to optimize the position of constants */ - place_code(cg->irg); - - if (cg->dump) - be_dump(cg->irg, "-place", dump_ir_block_graph_sched); + place_code(irg); } /** * Called immediately before emit phase. */ -static void arm_finish_irg(void *self) +static void arm_finish_irg(ir_graph *irg) { - (void) self; - /* TODO: - fix offsets for nodes accessing stack - - ... - */ + /* do peephole optimizations and fix stack offsets */ + arm_peephole_optimization(irg); } - -/** - * These are some hooks which must be filled but are probably not needed. - */ -static void arm_before_sched(void *self) +static void arm_before_ra(ir_graph *irg) { - (void) self; - /* Some stuff you need to do after scheduling but before register allocation */ + be_sched_fix_flags(irg, &arm_reg_classes[CLASS_arm_flags], NULL, NULL); } -static void arm_before_ra(void *self) +static void transform_Reload(ir_node *node) { - (void) self; - /* Some stuff you need to do immediately after register allocation */ -} + ir_node *block = get_nodes_block(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *ptr = get_irn_n(node, be_pos_Reload_frame); + ir_node *mem = get_irn_n(node, be_pos_Reload_mem); + ir_mode *mode = get_irn_mode(node); + ir_entity *entity = be_get_frame_entity(node); + const arch_register_t *reg; + ir_node *proj; + ir_node *load; -/** - * We transform Spill and Reload here. This needs to be done before - * stack biasing otherwise we would miss the corrected offset for these nodes. - */ -static void arm_after_ra(void *self) -{ - arm_code_gen_t *cg = self; - be_coalesce_spillslots(cg->birg); -} + ir_node *sched_point = sched_prev(node); -/** - * Emits the code, closes the output file and frees - * the code generator interface. - */ -static void arm_emit_and_done(void *self) { - arm_code_gen_t *cg = self; - ir_graph *irg = cg->irg; + load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true); + sched_add_after(sched_point, load); + sched_remove(node); - arm_gen_routine(cg, irg); + proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res); - cur_reg_set = NULL; + reg = arch_get_irn_register(node); + arch_set_irn_register(proj, reg); - /* de-allocate code generator */ - del_set(cg->reg_set); - free(self); + exchange(node, proj); } -/** - * Move a double floating point value into an integer register. - * Place the move operation into block bl. - * - * Handle some special cases here: - * 1.) A constant: simply split into two - * 2.) A load: simply split into two - */ -static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem, - ir_node **resH, ir_node **resL) { - if (is_Const(arg)) { - tarval *tv = get_Const_tarval(arg); - unsigned v; - - /* get the upper 32 bits */ - v = get_tarval_sub_bits(tv, 7); - v = (v << 8) | get_tarval_sub_bits(tv, 6); - v = (v << 8) | get_tarval_sub_bits(tv, 5); - v = (v << 8) | get_tarval_sub_bits(tv, 4); - *resH = new_Const_long(mode_Is, v); - - /* get the lower 32 bits */ - v = get_tarval_sub_bits(tv, 3); - v = (v << 8) | get_tarval_sub_bits(tv, 2); - v = (v << 8) | get_tarval_sub_bits(tv, 1); - v = (v << 8) | get_tarval_sub_bits(tv, 0); - *resL = new_Const_long(mode_Is, v); - } - else if (get_irn_op(skip_Proj(arg)) == op_Load) { - /* FIXME: handling of low/high depends on LE/BE here */ - assert(0); - } - else { - ir_graph *irg = current_ir_graph; - ir_node *conv; - - conv = new_rd_arm_fpaDbl2GP(NULL, irg, bl, arg, mem); - /* move high/low */ - *resL = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_low); - *resH = new_r_Proj(irg, bl, conv, mode_Is, pn_arm_fpaDbl2GP_high); - mem = new_r_Proj(irg, bl, conv, mode_M, pn_arm_fpaDbl2GP_M); - } - return mem; -} - -/** - * Move a single floating point value into an integer register. - * Place the move operation into block bl. - * - * Handle some special cases here: - * 1.) A constant: simply move - * 2.) A load: simply load - */ -static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) +static void transform_Spill(ir_node *node) { - (void) bl; - - if (is_Const(arg)) { - tarval *tv = get_Const_tarval(arg); - unsigned v; - - /* get the lower 32 bits */ - v = get_tarval_sub_bits(tv, 3); - v = (v << 8) | get_tarval_sub_bits(tv, 2); - v = (v << 8) | get_tarval_sub_bits(tv, 1); - v = (v << 8) | get_tarval_sub_bits(tv, 0); - return new_Const_long(mode_Is, v); - } - else if (get_irn_op(skip_Proj(arg)) == op_Load) { - ir_node *load; + ir_node *block = get_nodes_block(node); + dbg_info *dbgi = get_irn_dbg_info(node); + ir_node *ptr = get_irn_n(node, be_pos_Spill_frame); + ir_node *mem = new_NoMem(); + ir_node *val = get_irn_n(node, be_pos_Spill_val); + ir_mode *mode = get_irn_mode(val); + ir_entity *entity = be_get_frame_entity(node); + ir_node *sched_point; + ir_node *store; - load = skip_Proj(arg); - } - assert(0); - return NULL; + sched_point = sched_prev(node); + store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0, + true); + + sched_remove(node); + sched_add_after(sched_point, store); + + exchange(node, store); } -/** - * Convert the arguments of a call to support the - * ARM calling convention of general purpose AND floating - * point arguments. - */ -static void handle_calls(ir_node *call, void *env) +static void arm_after_ra_walker(ir_node *block, void *data) { - arm_code_gen_t *cg = env; - int i, j, n, size, idx, flag, n_param, n_res, first_variadic; - ir_type *mtp, *new_mtd, *new_tp[5]; - ir_node *new_in[5], **in; - ir_node *bl; + ir_node *node, *prev; + (void) data; - if (! is_Call(call)) - return; + for (node = sched_last(block); !sched_is_begin(node); node = prev) { + prev = sched_prev(node); - /* check, if we need conversions */ - n = get_Call_n_params(call); - mtp = get_Call_type(call); - assert(get_method_n_params(mtp) == n); - - /* it's always enough to handle the first 4 parameters */ - if (n > 4) - n = 4; - flag = size = idx = 0; - bl = get_nodes_block(call); - for (i = 0; i < n; ++i) { - ir_type *param_tp = get_method_param_type(mtp, i); - - if (is_compound_type(param_tp)) { - /* an aggregate parameter: bad case */ - assert(0); - } - else { - /* a primitive parameter */ - ir_mode *mode = get_type_mode(param_tp); - - if (mode_is_float(mode)) { - if (get_mode_size_bits(mode) > 32) { - ir_node *mem = get_Call_mem(call); - - /* Beware: ARM wants the high part first */ - size += 2 * 4; - new_tp[idx] = cg->int_tp; - new_tp[idx+1] = cg->int_tp; - mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]); - idx += 2; - set_Call_mem(call, mem); - } - else { - size += 4; - new_tp[idx] = cg->int_tp; - new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i)); - ++idx; - } - flag = 1; - } - else { - size += 4; - new_tp[idx] = param_tp; - new_in[idx] = get_Call_param(call, i); - ++idx; - } + if (be_is_Reload(node)) { + transform_Reload(node); + } else if (be_is_Spill(node)) { + transform_Spill(node); } - - if (size >= 16) - break; } +} - /* if flag is NOT set, no need to translate the method type */ - if (! flag) +static void arm_collect_frame_entity_nodes(ir_node *node, void *data) +{ + be_fec_env_t *env = data; + const ir_mode *mode; + int align; + ir_entity *entity; + const arm_load_store_attr_t *attr; + + if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) { + mode = get_irn_mode(node); + align = get_mode_size_bytes(mode); + be_node_needs_frame_entity(env, node, mode, align); return; - - /* construct a new method type */ - n = i; - n_param = get_method_n_params(mtp) - n + idx; - n_res = get_method_n_ress(mtp); - new_mtd = new_d_type_method(get_type_ident(mtp), n_param, n_res, get_type_dbg_info(mtp)); - - for (i = 0; i < idx; ++i) - set_method_param_type(new_mtd, i, new_tp[i]); - for (i = n, j = idx; i < get_method_n_params(mtp); ++i) - set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i)); - for (i = 0; i < n_res; ++i) - set_method_res_type(new_mtd, i, get_method_res_type(mtp, i)); - - set_method_calling_convention(new_mtd, get_method_calling_convention(mtp)); - first_variadic = get_method_first_variadic_param_index(mtp); - if (first_variadic >= 0) - set_method_first_variadic_param_index(new_mtd, first_variadic); - - if (is_lowered_type(mtp)) { - mtp = get_associated_type(mtp); } - set_lowered_type(mtp, new_mtd); - - set_Call_type(call, new_mtd); - /* calculate new in array of the Call */ - NEW_ARR_A(ir_node *, in, n_param + 2); - for (i = 0; i < idx; ++i) - in[2 + i] = new_in[i]; - for (i = n, j = idx; i < get_method_n_params(mtp); ++i) - in[2 + j++] = get_Call_param(call, i); - - in[0] = get_Call_mem(call); - in[1] = get_Call_ptr(call); + switch (get_arm_irn_opcode(node)) { + case iro_arm_Ldf: + case iro_arm_Ldr: + break; + default: + return; + } - /* finally, change the call inputs */ - set_irn_in(call, n_param + 2, in); + attr = get_arm_load_store_attr_const(node); + entity = attr->entity; + mode = attr->load_store_mode; + align = get_mode_size_bytes(mode); + if (entity != NULL) + return; + if (!attr->is_frame_entity) + return; + be_node_needs_frame_entity(env, node, mode, align); } -/** - * Handle graph transformations before the abi converter does its work. - */ -static void arm_before_abi(void *self) { - arm_code_gen_t *cg = self; - - irg_walk_graph(cg->irg, NULL, handle_calls, cg); +static void arm_set_frame_entity(ir_node *node, ir_entity *entity) +{ + if (is_be_node(node)) { + be_node_set_frame_entity(node, entity); + } else { + arm_load_store_attr_t *attr = get_arm_load_store_attr(node); + attr->entity = entity; + } } -/* forward */ -static void *arm_cg_init(be_irg_t *birg); +static void arm_after_ra(ir_graph *irg) +{ + be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg); -static const arch_code_generator_if_t arm_code_gen_if = { - arm_cg_init, - NULL, /* get_pic_base */ - arm_before_abi, /* before abi introduce */ - arm_prepare_graph, - NULL, /* spill */ - arm_before_sched, /* before scheduling hook */ - arm_before_ra, /* before register allocation hook */ - arm_after_ra, - arm_finish_irg, - arm_emit_and_done, -}; + irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env); + be_assign_entities(fec_env, arm_set_frame_entity); + be_free_frame_entity_coalescer(fec_env); + + irg_block_walk_graph(irg, NULL, arm_after_ra_walker, NULL); +} /** * Initializes the code generator. */ -static void *arm_cg_init(be_irg_t *birg) { - static ir_type *int_tp = NULL; - arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env.isa; - arm_code_gen_t *cg; - - if (! int_tp) { - /* create an integer type with machine size */ - int_tp = new_type_primitive(new_id_from_chars("int", 3), mode_Is); - } - - cg = xmalloc(sizeof(*cg)); - cg->impl = &arm_code_gen_if; - cg->irg = birg->irg; - cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024); - cg->arch_env = &birg->main_env->arch_env; - cg->isa = isa; - cg->birg = birg; - cg->int_tp = int_tp; - cg->have_fp_insn = 0; - cg->unknown_gp = NULL; - cg->unknown_fpa = NULL; - cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; - - FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg"); - - cur_reg_set = cg->reg_set; - - /* enter the current code generator */ - isa->cg = cg; - - return (arch_code_generator_t *)cg; +static void arm_init_graph(ir_graph *irg) +{ + (void) irg; } @@ -611,7 +292,8 @@ static void *arm_cg_init(be_irg_t *birg) { * and map all instructions the backend did not support * to runtime calls. */ -static void arm_handle_intrinsics(void) { +static void arm_handle_intrinsics(void) +{ ir_type *tp, *int_tp, *uint_tp; i_record records[8]; int n_records = 0; @@ -620,14 +302,14 @@ static void arm_handle_intrinsics(void) { #define ID(x) new_id_from_chars(x, sizeof(x)-1) - int_tp = new_type_primitive(ID("int"), mode_Is); - uint_tp = new_type_primitive(ID("uint"), mode_Iu); + int_tp = get_type_for_mode(mode_Is); + uint_tp = get_type_for_mode(mode_Iu); /* ARM has neither a signed div instruction ... */ { i_instr_record *map_Div = &records[n_records++].i_instr; - tp = new_type_method(ID("rt_iDiv"), 2, 1); + tp = new_type_method(2, 1); set_method_param_type(tp, 0, int_tp); set_method_param_type(tp, 1, int_tp); set_method_res_type(tp, 0, int_tp); @@ -642,7 +324,8 @@ static void arm_handle_intrinsics(void) { rt_iDiv.exc_mem_proj_nr = pn_Div_M; rt_iDiv.res_proj_nr = pn_Div_res; - set_entity_visibility(rt_iDiv.ent, visibility_external_allocated); + add_entity_linkage(rt_iDiv.ent, IR_LINKAGE_CONSTANT); + set_entity_visibility(rt_iDiv.ent, ir_visibility_external); map_Div->kind = INTRINSIC_INSTR; map_Div->op = op_Div; @@ -653,7 +336,7 @@ static void arm_handle_intrinsics(void) { { i_instr_record *map_Div = &records[n_records++].i_instr; - tp = new_type_method(ID("rt_uDiv"), 2, 1); + tp = new_type_method(2, 1); set_method_param_type(tp, 0, uint_tp); set_method_param_type(tp, 1, uint_tp); set_method_res_type(tp, 0, uint_tp); @@ -668,7 +351,7 @@ static void arm_handle_intrinsics(void) { rt_uDiv.exc_mem_proj_nr = pn_Div_M; rt_uDiv.res_proj_nr = pn_Div_res; - set_entity_visibility(rt_uDiv.ent, visibility_external_allocated); + set_entity_visibility(rt_uDiv.ent, ir_visibility_external); map_Div->kind = INTRINSIC_INSTR; map_Div->op = op_Div; @@ -679,7 +362,7 @@ static void arm_handle_intrinsics(void) { { i_instr_record *map_Mod = &records[n_records++].i_instr; - tp = new_type_method(ID("rt_iMod"), 2, 1); + tp = new_type_method(2, 1); set_method_param_type(tp, 0, int_tp); set_method_param_type(tp, 1, int_tp); set_method_res_type(tp, 0, int_tp); @@ -694,7 +377,7 @@ static void arm_handle_intrinsics(void) { rt_iMod.exc_mem_proj_nr = pn_Mod_M; rt_iMod.res_proj_nr = pn_Mod_res; - set_entity_visibility(rt_iMod.ent, visibility_external_allocated); + set_entity_visibility(rt_iMod.ent, ir_visibility_external); map_Mod->kind = INTRINSIC_INSTR; map_Mod->op = op_Mod; @@ -705,7 +388,7 @@ static void arm_handle_intrinsics(void) { { i_instr_record *map_Mod = &records[n_records++].i_instr; - tp = new_type_method(ID("rt_uMod"), 2, 1); + tp = new_type_method(2, 1); set_method_param_type(tp, 0, uint_tp); set_method_param_type(tp, 1, uint_tp); set_method_res_type(tp, 0, uint_tp); @@ -720,7 +403,7 @@ static void arm_handle_intrinsics(void) { rt_uMod.exc_mem_proj_nr = pn_Mod_M; rt_uMod.res_proj_nr = pn_Mod_res; - set_entity_visibility(rt_uMod.ent, visibility_external_allocated); + set_entity_visibility(rt_uMod.ent, ir_visibility_external); map_Mod->kind = INTRINSIC_INSTR; map_Mod->op = op_Mod; @@ -732,61 +415,53 @@ static void arm_handle_intrinsics(void) { lower_intrinsics(records, n_records, /*part_block_used=*/0); } -/***************************************************************** - * ____ _ _ _____ _____ - * | _ \ | | | | |_ _|/ ____| /\ - * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \ - * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \ - * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \ - * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\ - * - *****************************************************************/ - +const arch_isa_if_t arm_isa_if; static arm_isa_t arm_isa_template = { { &arm_isa_if, /* isa interface */ &arm_gp_regs[REG_SP], /* stack pointer */ &arm_gp_regs[REG_R11], /* base pointer */ + &arm_reg_classes[CLASS_arm_gp], /* static link pointer class */ -1, /* stack direction */ - 1, /* stack alignment for calls */ + 2, /* power of two stack alignment for calls, 2^2 == 4 */ NULL, /* main environment */ 7, /* spill costs */ 5, /* reload costs */ + true, /* we do have custom abi handling */ }, - 0, /* use generic register names instead of SP, LR, PC */ ARM_FPU_ARCH_FPE, /* FPU architecture */ - NULL, /* current code generator */ }; /** * Initializes the backend ISA and opens the output file. */ -static void *arm_init(FILE *file_handle) { +static arch_env_t *arm_init(FILE *file_handle) +{ static int inited = 0; arm_isa_t *isa; - if(inited) + if (inited) return NULL; - isa = xmalloc(sizeof(*isa)); + isa = XMALLOC(arm_isa_t); memcpy(isa, &arm_isa_template, sizeof(*isa)); arm_register_init(); - isa->cg = NULL; be_emit_init(file_handle); arm_create_opcodes(&arm_irn_ops); arm_handle_intrinsics(); - /* we mark referenced global entities, so we can only emit those which - * are actually referenced. (Note: you mustn't use the type visited flag - * elsewhere in the backend) - */ - inc_master_type_visited(); + be_gas_emit_types = false; + + /* needed for the debug support */ + be_gas_emit_switch_section(GAS_SECTION_TEXT); + be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix()); + be_emit_write_line(); inited = 1; - return isa; + return &isa->base; } @@ -794,10 +469,11 @@ static void *arm_init(FILE *file_handle) { /** * Closes the output file and frees the ISA structure. */ -static void arm_done(void *self) { +static void arm_done(void *self) +{ arm_isa_t *isa = self; - be_gas_emit_decls(isa->arch_isa.main_env, 1); + be_gas_emit_decls(isa->base.main_env); be_emit_exit(); free(self); @@ -810,17 +486,16 @@ static void arm_done(void *self) { * here to speed up register allocation (and makes dumps * smaller and more readable). */ -static unsigned arm_get_n_reg_class(const void *self) { - (void) self; +static unsigned arm_get_n_reg_class(void) +{ return N_CLASSES; } /** * Return the register class with requested index. */ -static const arch_register_class_t *arm_get_reg_class(const void *self, - unsigned i) { - (void) self; +static const arch_register_class_t *arm_get_reg_class(unsigned i) +{ assert(i < N_CLASSES); return &arm_reg_classes[i]; } @@ -831,264 +506,30 @@ static const arch_register_class_t *arm_get_reg_class(const void *self, * @param mode The mode in question. * @return A register class which can hold values of the given mode. */ -const arch_register_class_t *arm_get_reg_class_for_mode(const void *self, const ir_mode *mode) { - (void) self; +static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode) +{ if (mode_is_float(mode)) return &arm_reg_classes[CLASS_arm_fpa]; else return &arm_reg_classes[CLASS_arm_gp]; } -/** - * Produces the type which sits between the stack args and the locals on the stack. - * it will contain the return address and space to store the old base pointer. - * @return The Firm type modeling the ABI between type. - */ -static ir_type *arm_get_between_type(void *self) { - static ir_type *between_type = NULL; - static ir_entity *old_bp_ent = NULL; - (void) self; - - if (between_type == NULL) { - ir_entity *ret_addr_ent; - ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P); - ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P); - - between_type = new_type_class(new_id_from_str("arm_between_type")); - old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type); - ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type); - - set_entity_offset(old_bp_ent, 0); - set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type)); - set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type)); - } - - return between_type; -} - - -typedef struct { - be_abi_call_flags_bits_t flags; - const arch_env_t *arch_env; - const arch_isa_t *isa; - ir_graph *irg; -} arm_abi_env_t; - -static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg) -{ - arm_abi_env_t *env = xmalloc(sizeof(env[0])); - be_abi_call_flags_t fl = be_abi_call_get_flags(call); - env->flags = fl.bits; - env->irg = irg; - env->arch_env = arch_env; - env->isa = arch_env->isa; - return env; -} - -static void arm_abi_dont_save_regs(void *self, pset *s) +static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) { - arm_abi_env_t *env = self; - if (env->flags.try_omit_fp) - pset_insert_ptr(s, env->isa->bp); -} - - - -/** - * Build the ARM prolog - */ -static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map) { - ir_node *keep, *store; - arm_abi_env_t *env = self; - ir_graph *irg = env->irg; - ir_node *block = get_irg_start_block(irg); - arch_register_class_t *gp = &arm_reg_classes[CLASS_arm_gp]; - - ir_node *fp = be_abi_reg_map_get(reg_map, env->isa->bp); - ir_node *ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]); - ir_node *sp = be_abi_reg_map_get(reg_map, env->isa->sp); - ir_node *lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); - ir_node *pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]); - - if (env->flags.try_omit_fp) - return env->isa->sp; - - ip = be_new_Copy(gp, irg, block, sp); - arch_set_irn_register(env->arch_env, ip, &arm_gp_regs[REG_R12]); - be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] ); - - store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem); - - sp = new_r_Proj(irg, block, store, env->isa->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr); - arch_set_irn_register(env->arch_env, sp, env->isa->sp); - *mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M); - - keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip)); - be_node_set_reg_class(keep, 1, gp); - arch_set_irn_register(env->arch_env, keep, &arm_gp_regs[REG_R12]); - be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] ); - - fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4); - arch_set_irn_register(env->arch_env, fp, env->isa->bp); - - be_abi_reg_map_set(reg_map, env->isa->bp, fp); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep); - be_abi_reg_map_set(reg_map, env->isa->sp, sp); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc); - - return env->isa->bp; -} - -/** - * Builds the ARM epilogue - */ -static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) { - arm_abi_env_t *env = self; - ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp); - ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp); - ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]); - ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); - - // TODO: Activate Omit fp in epilogue - if (env->flags.try_omit_fp) { - curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0); - add_irn_dep(curr_sp, *mem); - - curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr)); - be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]); - arch_set_irn_register(env->arch_env, curr_lr, &arm_gp_regs[REG_LR]); - be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] ); - - curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr ); - arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]); - be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] ); - be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore); - } else { - ir_node *sub12_node; - ir_node *load_node; - sub12_node = new_rd_arm_Sub_i(NULL, env->irg, bl, curr_bp, mode_Iu, 12); - // FIXME - //set_arm_req_out_all(sub12_node, sub12_req); - arch_set_irn_register(env->arch_env, sub12_node, env->isa->sp); - load_node = new_rd_arm_LoadStackM3( NULL, env->irg, bl, sub12_node, *mem ); - // FIXME - //set_arm_req_out(load_node, &arm_default_req_arm_gp_r11, 0); - //set_arm_req_out(load_node, &arm_default_req_arm_gp_sp, 1); - //set_arm_req_out(load_node, &arm_default_req_arm_gp_pc, 2); - curr_bp = new_r_Proj(env->irg, bl, load_node, env->isa->bp->reg_class->mode, pn_arm_LoadStackM3_res0); - curr_sp = new_r_Proj(env->irg, bl, load_node, env->isa->sp->reg_class->mode, pn_arm_LoadStackM3_res1); - curr_pc = new_r_Proj(env->irg, bl, load_node, mode_Iu, pn_arm_LoadStackM3_res2); - *mem = new_r_Proj(env->irg, bl, load_node, mode_M, pn_arm_LoadStackM3_M); - arch_set_irn_register(env->arch_env, curr_bp, env->isa->bp); - arch_set_irn_register(env->arch_env, curr_sp, env->isa->sp); - arch_set_irn_register(env->arch_env, curr_pc, &arm_gp_regs[REG_PC]); - } - be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp); - be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc); -} - -static const be_abi_callbacks_t arm_abi_callbacks = { - arm_abi_init, - free, - arm_get_between_type, - arm_abi_dont_save_regs, - arm_abi_prologue, - arm_abi_epilogue, -}; - - -/** - * Get the ABI restrictions for procedure calls. - * @param self The this pointer. - * @param method_type The type of the method (procedure) in question. - * @param abi The abi object to be modified - */ -void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) { - ir_type *tp; - ir_mode *mode; - int i; - int n = get_method_n_params(method_type); - be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi); - (void) self; - - /* set abi flags for calls */ - call_flags.bits.left_to_right = 0; - call_flags.bits.store_args_sequential = 0; - /* call_flags.bits.try_omit_fp don't change this we can handle both */ - call_flags.bits.fp_free = 0; - call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */ - - /* set stack parameter passing style */ - be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks); - - for (i = 0; i < n; i++) { - /* reg = get reg for param i; */ - /* be_abi_call_param_reg(abi, i, reg); */ - if (i < 4) { - be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i)); - } else { - tp = get_method_param_type(method_type, i); - mode = get_type_mode(tp); - be_abi_call_param_stack(abi, i, mode, 4, 0, 0); - } - } - - /* set return registers */ - n = get_method_n_ress(method_type); - - assert(n <= 2 && "more than two results not supported"); - - /* In case of 64bit returns, we will have two 32bit values */ - if (n == 2) { - tp = get_method_res_type(method_type, 0); - mode = get_type_mode(tp); - - assert(!mode_is_float(mode) && "two FP results not supported"); - - tp = get_method_res_type(method_type, 1); - mode = get_type_mode(tp); - - assert(!mode_is_float(mode) && "mixed INT, FP results not supported"); - - be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]); - be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]); - } else if (n == 1) { - const arch_register_t *reg; - - tp = get_method_res_type(method_type, 0); - assert(is_atomic_type(tp)); - mode = get_type_mode(tp); - - reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]; - be_abi_call_res_reg(abi, 0, reg); - } -} - -int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) { (void) block_env; - if(!is_arm_irn(irn)) + if (!is_arm_irn(irn)) return -1; return 1; } -/** - * Initializes the code generator interface. - */ -static const arch_code_generator_if_t *arm_get_code_generator_if(void *self) { - (void) self; - return &arm_code_gen_if; -} - list_sched_selector_t arm_sched_selector; /** * Returns the reg_pressure scheduler with to_appear_in_schedule() over\loaded */ -static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) { +static const list_sched_selector_t *arm_get_list_sched_selector(const void *self, list_sched_selector_t *selector) +{ (void) self; memcpy(&arm_sched_selector, selector, sizeof(arm_sched_selector)); /* arm_sched_selector.exectime = arm_sched_exectime; */ @@ -1097,7 +538,8 @@ static const list_sched_selector_t *arm_get_list_sched_selector(const void *self } -static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) { +static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) +{ (void) self; return NULL; } @@ -1105,32 +547,32 @@ static const ilp_sched_selector_t *arm_get_ilp_sched_selector(const void *self) /** * Returns the necessary byte alignment for storing a register of given class. */ -static int arm_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) { - (void) self; +static int arm_get_reg_class_alignment(const arch_register_class_t *cls) +{ (void) cls; /* ARM is a 32 bit CPU, no need for other alignment */ return 4; } -static const be_execution_unit_t ***arm_get_allowed_execution_units(const void *self, const ir_node *irn) { - (void) self; +static const be_execution_unit_t ***arm_get_allowed_execution_units(const ir_node *irn) +{ (void) irn; /* TODO */ - assert(0); - return NULL; + panic("Unimplemented arm_get_allowed_execution_units()"); } -static const be_machine_t *arm_get_machine(const void *self) { +static const be_machine_t *arm_get_machine(const void *self) +{ (void) self; /* TODO */ - assert(0); - return NULL; + panic("Unimplemented arm_get_machine()"); } /** * Return irp irgs in the desired order. */ -static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) { +static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) +{ (void) self; (void) irg_list; return NULL; @@ -1140,51 +582,45 @@ static ir_graph **arm_get_irg_list(const void *self, ir_graph ***irg_list) { * Allows or disallows the creation of Psi nodes for the given Phi nodes. * @return 1 if allowed, 0 otherwise */ -static int arm_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j) { - ir_node *cmp, *cmp_a, *phi; - ir_mode *mode; - +static int arm_is_mux_allowed(ir_node *sel, ir_node *mux_false, + ir_node *mux_true) +{ + (void) sel; + (void) mux_false; + (void) mux_true; - /* currently Psi support is not implemented */ return 0; +} -/* we don't want long long Psi */ -#define IS_BAD_PSI_MODE(mode) (!mode_is_float(mode) && get_mode_size_bits(mode) > 32) - - if (get_irn_mode(sel) != mode_b) - return 0; - - cmp = get_Proj_pred(sel); - cmp_a = get_Cmp_left(cmp); - mode = get_irn_mode(cmp_a); +static asm_constraint_flags_t arm_parse_asm_constraint(const char **c) +{ + /* asm not supported */ + (void) c; + return ASM_CONSTRAINT_FLAG_INVALID; +} - if (IS_BAD_PSI_MODE(mode)) - return 0; +static int arm_is_valid_clobber(const char *clobber) +{ + (void) clobber; + return 0; +} - /* check the Phi nodes */ - for (phi = phi_list; phi; phi = get_irn_link(phi)) { - ir_node *pred_i = get_irn_n(phi, i); - ir_node *pred_j = get_irn_n(phi, j); - ir_mode *mode_i = get_irn_mode(pred_i); - ir_mode *mode_j = get_irn_mode(pred_j); +static void arm_lower_for_target(void) +{ + int i; + int n_irgs = get_irp_n_irgs(); - if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j)) - return 0; + for (i = 0; i < n_irgs; ++i) { + ir_graph *irg = get_irp_irg(i); + lower_switch(irg, 256, true); } - -#undef IS_BAD_PSI_MODE - - return 1; } /** * Returns the libFirm configuration parameter for this backend. */ -static const backend_params *arm_get_libfirm_params(void) { - static const ir_settings_if_conv_t ifconv = { - 4, /* maxdepth, doesn't matter for Psi-conversion */ - arm_is_psi_allowed /* allows or disallows Psi creation for given selector */ - }; +static const backend_params *arm_get_libfirm_params(void) +{ static ir_settings_arch_dep_t ad = { 1, /* allow subs */ 1, /* Muls are fast enough on ARM but ... */ @@ -1195,17 +631,19 @@ static const backend_params *arm_get_libfirm_params(void) { 32, /* SMUL & UMUL available for 32 bit */ }; static backend_params p = { - 1, /* need dword lowering */ 0, /* don't support inline assembler yet */ - NULL, /* no additional opcodes */ - NULL, /* will be set later */ - NULL, /* but yet no creator function */ - NULL, /* context for create_intrinsic_fkt */ - NULL, /* will be set below */ + 1, /* support Rotl nodes */ + 1, /* big endian */ + arm_lower_for_target, /* lowering function */ + &ad, /* will be set later */ + arm_is_mux_allowed, /* allow_ifconv function */ + NULL, /* float arithmetic mode (TODO) */ + 0, /* no trampoline support: size 0 */ + 0, /* no trampoline support: align 0 */ + NULL, /* no trampoline support: no trampoline builder */ + 4 /* alignment of stack parameter */ }; - p.dep_param = &ad; - p.if_conv_info = &ifconv; return &p; } @@ -1226,18 +664,17 @@ static lc_opt_enum_int_var_t arch_fpu_var = { static const lc_opt_table_entry_t arm_options[] = { LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var), - LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names), LC_OPT_LAST }; const arch_isa_if_t arm_isa_if = { arm_init, arm_done, + NULL, /* handle_intrinsics */ arm_get_n_reg_class, arm_get_reg_class, arm_get_reg_class_for_mode, - arm_get_call_abi, - arm_get_code_generator_if, + NULL, arm_get_list_sched_selector, arm_get_ilp_sched_selector, arm_get_reg_class_alignment, @@ -1245,8 +682,21 @@ const arch_isa_if_t arm_isa_if = { arm_get_allowed_execution_units, arm_get_machine, arm_get_irg_list, + NULL, /* mark remat */ + arm_parse_asm_constraint, + arm_is_valid_clobber, + + arm_init_graph, + NULL, /* get_pic_base */ + NULL, /* before_abi */ + arm_prepare_graph, + arm_before_ra, + arm_after_ra, + arm_finish_irg, + arm_gen_routine, }; +BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm); void be_init_arch_arm(void) { lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be"); @@ -1259,5 +709,3 @@ void be_init_arch_arm(void) arm_init_transform(); arm_init_emitter(); } - -BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);