X-Git-Url: http://nsz.repo.hu/git/?a=blobdiff_plain;f=ir%2Fbe%2Farm%2Fbearch_arm.c;h=c844dc102c9cefb56a5401479e83491987fe09dd;hb=64a28ffcfdabd5111dda5705c65f5830e1fc3980;hp=c7b11b665757ca87dd479ad3bf58dff698b9c546;hpb=ca21c59ea00ff05918de26952e91ac39f1589e01;p=libfirm diff --git a/ir/be/arm/bearch_arm.c b/ir/be/arm/bearch_arm.c index c7b11b665..c844dc102 100644 --- a/ir/be/arm/bearch_arm.c +++ b/ir/be/arm/bearch_arm.c @@ -28,7 +28,6 @@ #include "lc_opts.h" #include "lc_opts_enum.h" -#include "pseudo_irg.h" #include "irgwalk.h" #include "irprog.h" #include "irprintf.h" @@ -36,6 +35,7 @@ #include "irgmod.h" #include "irgopt.h" #include "iroptimize.h" +#include "irdump.h" #include "lowering.h" #include "error.h" @@ -49,7 +49,6 @@ #include "../belower.h" #include "../besched.h" #include "be.h" -#include "../beabi.h" #include "../bemachine.h" #include "../beilpsched.h" #include "../bemodule.h" @@ -71,6 +70,7 @@ static arch_irn_class_t arm_classify(const ir_node *irn) { (void) irn; + /* TODO: we should mark reload/spill instructions and classify them here */ return 0; } @@ -92,13 +92,6 @@ static ir_entity *arm_get_frame_entity(const ir_node *irn) return NULL; } -static void arm_set_frame_entity(ir_node *irn, ir_entity *ent) -{ - (void) irn; - (void) ent; - panic("arm_set_frame_entity() called. This should not happen."); -} - /** * This function is called by the generic backend to correct offsets for * nodes accessing the stack. @@ -118,7 +111,7 @@ static void arm_set_stack_bias(ir_node *irn, int bias) static int arm_get_sp_bias(const ir_node *irn) { /* We don't have any nodes changing the stack pointer. - TODO: we probably want to support post-/pre increment/decrement later */ + We probably want to support post-/pre increment/decrement later */ (void) irn; return 0; } @@ -129,7 +122,6 @@ static const arch_irn_ops_t arm_irn_ops = { get_arm_in_req, arm_classify, arm_get_frame_entity, - arm_set_frame_entity, arm_set_stack_bias, arm_get_sp_bias, NULL, /* get_inverse */ @@ -153,13 +145,13 @@ static void arm_prepare_graph(void *self) local_optimize_graph(cg->irg); if (cg->dump) - be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched); + dump_ir_graph(cg->irg, "transformed"); /* do code placement, to optimize the position of constants */ place_code(cg->irg); if (cg->dump) - be_dump(cg->irg, "-place", dump_ir_block_graph_sched); + dump_ir_graph(cg->irg, "place"); } /** @@ -193,16 +185,15 @@ static void arm_before_ra(void *self) { arm_code_gen_t *cg = self; - be_sched_fix_flags(cg->birg, &arm_reg_classes[CLASS_arm_flags], + be_sched_fix_flags(cg->irg, &arm_reg_classes[CLASS_arm_flags], &arm_flags_remat); } static void transform_Reload(ir_node *node) { - ir_graph *irg = get_irn_irg(node); ir_node *block = get_nodes_block(node); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *ptr = get_irg_frame(irg); + ir_node *ptr = get_irn_n(node, be_pos_Reload_frame); ir_node *mem = get_irn_n(node, be_pos_Reload_mem); ir_mode *mode = get_irn_mode(node); ir_entity *entity = be_get_frame_entity(node); @@ -226,10 +217,9 @@ static void transform_Reload(ir_node *node) static void transform_Spill(ir_node *node) { - ir_graph *irg = get_irn_irg(node); ir_node *block = get_nodes_block(node); dbg_info *dbgi = get_irn_dbg_info(node); - ir_node *ptr = get_irg_frame(irg); + ir_node *ptr = get_irn_n(node, be_pos_Spill_frame); ir_node *mem = new_NoMem(); ir_node *val = get_irn_n(node, be_pos_Spill_val); ir_mode *mode = get_irn_mode(val); @@ -263,233 +253,86 @@ static void arm_after_ra_walker(ir_node *block, void *data) } } -static void arm_after_ra(void *self) -{ - arm_code_gen_t *cg = self; - be_coalesce_spillslots(cg->birg); - - irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL); -} - -/** - * Emits the code, closes the output file and frees - * the code generator interface. - */ -static void arm_emit_and_done(void *self) +static void arm_collect_frame_entity_nodes(ir_node *node, void *data) { - arm_code_gen_t *cg = self; - ir_graph *irg = cg->irg; - - arm_gen_routine(cg, irg); - - /* de-allocate code generator */ - del_set(cg->reg_set); - free(self); -} - -/** - * Move a double floating point value into an integer register. - * Place the move operation into block bl. - * - * Handle some special cases here: - * 1.) A constant: simply split into two - * 2.) A load: simply split into two - */ -static ir_node *convert_dbl_to_int(ir_node *bl, ir_node *arg, ir_node *mem, - ir_node **resH, ir_node **resL) -{ - if (is_Const(arg)) { - tarval *tv = get_Const_tarval(arg); - unsigned v; - - /* get the upper 32 bits */ - v = get_tarval_sub_bits(tv, 7); - v = (v << 8) | get_tarval_sub_bits(tv, 6); - v = (v << 8) | get_tarval_sub_bits(tv, 5); - v = (v << 8) | get_tarval_sub_bits(tv, 4); - *resH = new_Const_long(mode_Is, v); - - /* get the lower 32 bits */ - v = get_tarval_sub_bits(tv, 3); - v = (v << 8) | get_tarval_sub_bits(tv, 2); - v = (v << 8) | get_tarval_sub_bits(tv, 1); - v = (v << 8) | get_tarval_sub_bits(tv, 0); - *resL = new_Const_long(mode_Is, v); - } else if (is_Load(skip_Proj(arg))) { - /* FIXME: handling of low/high depends on LE/BE here */ - panic("Unimplemented convert_dbl_to_int() case"); - } - else { - ir_node *conv; - - conv = new_bd_arm_fpaDbl2GP(NULL, bl, arg, mem); - /* move high/low */ - *resL = new_r_Proj(conv, mode_Is, pn_arm_fpaDbl2GP_low); - *resH = new_r_Proj(conv, mode_Is, pn_arm_fpaDbl2GP_high); - mem = new_r_Proj(conv, mode_M, pn_arm_fpaDbl2GP_M); - } - return mem; -} + be_fec_env_t *env = data; + const ir_mode *mode; + int align; + ir_entity *entity; + const arm_load_store_attr_t *attr; -/** - * Move a single floating point value into an integer register. - * Place the move operation into block bl. - * - * Handle some special cases here: - * 1.) A constant: simply move - * 2.) A load: simply load - */ -static ir_node *convert_sng_to_int(ir_node *bl, ir_node *arg) -{ - (void) bl; - - if (is_Const(arg)) { - tarval *tv = get_Const_tarval(arg); - unsigned v; - - /* get the lower 32 bits */ - v = get_tarval_sub_bits(tv, 3); - v = (v << 8) | get_tarval_sub_bits(tv, 2); - v = (v << 8) | get_tarval_sub_bits(tv, 1); - v = (v << 8) | get_tarval_sub_bits(tv, 0); - return new_Const_long(mode_Is, v); - } else if (is_Load(skip_Proj(arg))) { - ir_node *load; - - load = skip_Proj(arg); + if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) { + mode = get_irn_mode(node); + align = get_mode_size_bytes(mode); + be_node_needs_frame_entity(env, node, mode, align); + return; } - panic("Unimplemented convert_sng_to_int() case"); -} - -/** - * Convert the arguments of a call to support the - * ARM calling convention of general purpose AND floating - * point arguments. - */ -static void handle_calls(ir_node *call, void *env) -{ - arm_code_gen_t *cg = env; - int i, j, n, size, idx, flag, n_param, n_res, first_variadic; - ir_type *mtp, *new_mtd, *new_tp[5]; - ir_node *new_in[5], **in; - ir_node *bl; - if (! is_Call(call)) + switch (get_arm_irn_opcode(node)) { + case iro_arm_Ldf: + case iro_arm_Ldr: + break; + default: return; - - /* check, if we need conversions */ - n = get_Call_n_params(call); - mtp = get_Call_type(call); - assert(get_method_n_params(mtp) == n); - - /* it's always enough to handle the first 4 parameters */ - if (n > 4) - n = 4; - flag = size = idx = 0; - bl = get_nodes_block(call); - for (i = 0; i < n; ++i) { - ir_type *param_tp = get_method_param_type(mtp, i); - - if (is_compound_type(param_tp)) { - /* an aggregate parameter: bad case */ - assert(0); - } - else { - /* a primitive parameter */ - ir_mode *mode = get_type_mode(param_tp); - - if (mode_is_float(mode)) { - if (get_mode_size_bits(mode) > 32) { - ir_node *mem = get_Call_mem(call); - - /* Beware: ARM wants the high part first */ - size += 2 * 4; - new_tp[idx] = cg->int_tp; - new_tp[idx+1] = cg->int_tp; - mem = convert_dbl_to_int(bl, get_Call_param(call, i), mem, &new_in[idx], &new_in[idx+1]); - idx += 2; - set_Call_mem(call, mem); - } - else { - size += 4; - new_tp[idx] = cg->int_tp; - new_in[idx] = convert_sng_to_int(bl, get_Call_param(call, i)); - ++idx; - } - flag = 1; - } - else { - size += 4; - new_tp[idx] = param_tp; - new_in[idx] = get_Call_param(call, i); - ++idx; - } - } - - if (size >= 16) - break; } - /* if flag is NOT set, no need to translate the method type */ - if (! flag) + attr = get_arm_load_store_attr_const(node); + entity = attr->entity; + mode = attr->load_store_mode; + align = get_mode_size_bytes(mode); + if (entity != NULL) + return; + if (!attr->is_frame_entity) return; + be_node_needs_frame_entity(env, node, mode, align); +} - /* construct a new method type */ - n = i; - n_param = get_method_n_params(mtp) - n + idx; - n_res = get_method_n_ress(mtp); - new_mtd = new_d_type_method(n_param, n_res, get_type_dbg_info(mtp)); - - for (i = 0; i < idx; ++i) - set_method_param_type(new_mtd, i, new_tp[i]); - for (i = n, j = idx; i < get_method_n_params(mtp); ++i) - set_method_param_type(new_mtd, j++, get_method_param_type(mtp, i)); - for (i = 0; i < n_res; ++i) - set_method_res_type(new_mtd, i, get_method_res_type(mtp, i)); - - set_method_calling_convention(new_mtd, get_method_calling_convention(mtp)); - first_variadic = get_method_first_variadic_param_index(mtp); - if (first_variadic >= 0) - set_method_first_variadic_param_index(new_mtd, first_variadic); - - if (is_lowered_type(mtp)) { - mtp = get_associated_type(mtp); +static void arm_set_frame_entity(ir_node *node, ir_entity *entity) +{ + if (is_be_node(node)) { + be_node_set_frame_entity(node, entity); + } else { + arm_load_store_attr_t *attr = get_arm_load_store_attr(node); + attr->entity = entity; } - set_lowered_type(mtp, new_mtd); +} - set_Call_type(call, new_mtd); +static void arm_after_ra(void *self) +{ + arm_code_gen_t *cg = self; + ir_graph *irg = cg->irg; - /* calculate new in array of the Call */ - NEW_ARR_A(ir_node *, in, n_param + 2); - for (i = 0; i < idx; ++i) - in[2 + i] = new_in[i]; - for (i = n, j = idx; i < get_method_n_params(mtp); ++i) - in[2 + j++] = get_Call_param(call, i); + be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg); - in[0] = get_Call_mem(call); - in[1] = get_Call_ptr(call); + irg_walk_graph(irg, NULL, arm_collect_frame_entity_nodes, fec_env); + be_assign_entities(fec_env, arm_set_frame_entity); + be_free_frame_entity_coalescer(fec_env); - /* finally, change the call inputs */ - set_irn_in(call, n_param + 2, in); + irg_block_walk_graph(cg->irg, NULL, arm_after_ra_walker, NULL); } /** - * Handle graph transformations before the abi converter does its work. + * Emits the code, closes the output file and frees + * the code generator interface. */ -static void arm_before_abi(void *self) +static void arm_emit_and_done(void *self) { arm_code_gen_t *cg = self; + ir_graph *irg = cg->irg; - irg_walk_graph(cg->irg, NULL, handle_calls, cg); + arm_gen_routine(cg, irg); + + /* de-allocate code generator */ + free(self); } /* forward */ -static void *arm_cg_init(be_irg_t *birg); +static void *arm_cg_init(ir_graph *irg); static const arch_code_generator_if_t arm_code_gen_if = { arm_cg_init, NULL, /* get_pic_base */ - arm_before_abi, /* before abi introduce */ + NULL, /* before abi introduce */ arm_prepare_graph, NULL, /* spill */ arm_before_ra, /* before register allocation hook */ @@ -501,30 +344,16 @@ static const arch_code_generator_if_t arm_code_gen_if = { /** * Initializes the code generator. */ -static void *arm_cg_init(be_irg_t *birg) +static void *arm_cg_init(ir_graph *irg) { - static ir_type *int_tp = NULL; - arm_isa_t *isa = (arm_isa_t *)birg->main_env->arch_env; + arm_isa_t *isa = (arm_isa_t*) be_get_irg_arch_env(irg); arm_code_gen_t *cg; - if (! int_tp) { - /* create an integer type with machine size */ - int_tp = new_type_primitive(mode_Is); - } - - cg = XMALLOC(arm_code_gen_t); - cg->impl = &arm_code_gen_if; - cg->irg = birg->irg; - cg->reg_set = new_set(arm_cmp_irn_reg_assoc, 1024); - cg->isa = isa; - cg->birg = birg; - cg->int_tp = int_tp; - cg->have_fp_insn = 0; - cg->unknown_gp = NULL; - cg->unknown_fpa = NULL; - cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0; - - FIRM_DBG_REGISTER(cg->mod, "firm.be.arm.cg"); + cg = XMALLOCZ(arm_code_gen_t); + cg->impl = &arm_code_gen_if; + cg->irg = irg; + cg->isa = isa; + cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0; /* enter the current code generator */ isa->cg = cg; @@ -548,8 +377,8 @@ static void arm_handle_intrinsics(void) #define ID(x) new_id_from_chars(x, sizeof(x)-1) - int_tp = new_type_primitive(mode_Is); - uint_tp = new_type_primitive(mode_Iu); + int_tp = get_type_for_mode(mode_Is); + uint_tp = get_type_for_mode(mode_Iu); /* ARM has neither a signed div instruction ... */ { @@ -661,16 +490,7 @@ static void arm_handle_intrinsics(void) lower_intrinsics(records, n_records, /*part_block_used=*/0); } -/***************************************************************** - * ____ _ _ _____ _____ - * | _ \ | | | | |_ _|/ ____| /\ - * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \ - * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \ - * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \ - * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\ - * - *****************************************************************/ - +const arch_isa_if_t arm_isa_if; static arm_isa_t arm_isa_template = { { &arm_isa_if, /* isa interface */ @@ -682,8 +502,8 @@ static arm_isa_t arm_isa_template = { NULL, /* main environment */ 7, /* spill costs */ 5, /* reload costs */ + true, /* we do have custom abi handling */ }, - 0, /* use generic register names instead of SP, LR, PC */ ARM_FPU_ARCH_FPE, /* FPU architecture */ NULL, /* current code generator */ }; @@ -718,7 +538,7 @@ static arch_env_t *arm_init(FILE *file_handle) be_emit_write_line(); inited = 1; - return &isa->arch_env; + return &isa->base; } @@ -730,7 +550,7 @@ static void arm_done(void *self) { arm_isa_t *isa = self; - be_gas_emit_decls(isa->arch_env.main_env); + be_gas_emit_decls(isa->base.main_env); be_emit_exit(); free(self); @@ -763,7 +583,7 @@ static const arch_register_class_t *arm_get_reg_class(unsigned i) * @param mode The mode in question. * @return A register class which can hold values of the given mode. */ -const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode) +static const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode) { if (mode_is_float(mode)) return &arm_reg_classes[CLASS_arm_fpa]; @@ -771,230 +591,7 @@ const arch_register_class_t *arm_get_reg_class_for_mode(const ir_mode *mode) return &arm_reg_classes[CLASS_arm_gp]; } -/** - * Produces the type which sits between the stack args and the locals on the stack. - * it will contain the return address and space to store the old base pointer. - * @return The Firm type modeling the ABI between type. - */ -static ir_type *arm_get_between_type(void *self) -{ - static ir_type *between_type = NULL; - (void) self; - - if (between_type == NULL) { - between_type = new_type_class(new_id_from_str("arm_between_type")); - set_type_size_bytes(between_type, 0); - } - - return between_type; -} - - -typedef struct { - be_abi_call_flags_bits_t flags; - const arch_env_t *arch_env; - ir_graph *irg; -} arm_abi_env_t; - -static void *arm_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg) -{ - arm_abi_env_t *env = XMALLOC(arm_abi_env_t); - be_abi_call_flags_t fl = be_abi_call_get_flags(call); - env->flags = fl.bits; - env->irg = irg; - env->arch_env = arch_env; - return env; -} - -/** - * Generate the routine prologue. - * - * @param self The callback object. - * @param mem A pointer to the mem node. Update this if you define new memory. - * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes. - * @param stack_bias Points to the current stack bias, can be modified if needed. - * - * @return The register which shall be used as a stack frame base. - * - * All nodes which define registers in @p reg_map must keep @p reg_map current. - */ -static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias) -{ - arm_abi_env_t *env = self; - ir_node *store; - ir_graph *irg; - ir_node *block; - arch_register_class_t *gp; - - ir_node *fp, *ip, *lr, *pc; - ir_node *sp = be_abi_reg_map_get(reg_map, env->arch_env->sp); - - (void) stack_bias; - - if (env->flags.try_omit_fp) - return env->arch_env->sp; - - fp = be_abi_reg_map_get(reg_map, env->arch_env->bp); - ip = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_R12]); - lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); - pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]); - - gp = &arm_reg_classes[CLASS_arm_gp]; - irg = env->irg; - block = get_irg_start_block(irg); - - /* mark bp register as ignore */ - be_set_constr_single_reg_out(get_Proj_pred(fp), - get_Proj_proj(fp), env->arch_env->bp, - arch_register_req_type_ignore); - - /* copy SP to IP (so we can spill it */ - ip = be_new_Copy(gp, block, sp); - be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], 0); - - /* spill stuff */ - store = new_bd_arm_StoreStackM4Inc(NULL, block, sp, fp, ip, lr, pc, *mem); - - sp = new_r_Proj(store, env->arch_env->sp->reg_class->mode, pn_arm_StoreStackM4Inc_ptr); - arch_set_irn_register(sp, env->arch_env->sp); - *mem = new_r_Proj(store, mode_M, pn_arm_StoreStackM4Inc_M); - - /* frame pointer is ip-4 (because ip is our old sp value) */ - fp = new_bd_arm_Sub_imm(NULL, block, ip, 4, 0); - arch_set_irn_register(fp, env->arch_env->bp); - - /* beware: we change the fp but the StoreStackM4Inc above wants the old - * fp value. We are not allowed to spill or anything in the prolog, so we - * have to enforce some order here. (scheduler/regalloc are too stupid - * to extract this order from register requirements) */ - add_irn_dep(fp, store); - - fp = be_new_Copy(gp, block, fp); // XXX Gammelfix: only be_ have custom register requirements - be_set_constr_single_reg_out(fp, 0, env->arch_env->bp, - arch_register_req_type_ignore); - arch_set_irn_register(fp, env->arch_env->bp); - - be_abi_reg_map_set(reg_map, env->arch_env->bp, fp); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], ip); - be_abi_reg_map_set(reg_map, env->arch_env->sp, sp); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], lr); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], pc); - - return env->arch_env->bp; -} - -/** - * Builds the ARM epilogue - */ -static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map) -{ - arm_abi_env_t *env = self; - ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->arch_env->sp); - ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->arch_env->bp); - ir_node *curr_pc = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_PC]); - ir_node *curr_lr = be_abi_reg_map_get(reg_map, &arm_gp_regs[REG_LR]); - - // TODO: Activate Omit fp in epilogue - if (env->flags.try_omit_fp) { - ir_node *incsp = be_new_IncSP(env->arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0); - curr_sp = incsp; - } else { - ir_node *load_node; - - load_node = new_bd_arm_LoadStackM3Epilogue(NULL, bl, curr_bp, *mem); - - curr_bp = new_r_Proj(load_node, env->arch_env->bp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res0); - curr_sp = new_r_Proj(load_node, env->arch_env->sp->reg_class->mode, pn_arm_LoadStackM3Epilogue_res1); - curr_pc = new_r_Proj(load_node, mode_Iu, pn_arm_LoadStackM3Epilogue_res2); - *mem = new_r_Proj(load_node, mode_M, pn_arm_LoadStackM3Epilogue_M); - arch_set_irn_register(curr_bp, env->arch_env->bp); - arch_set_irn_register(curr_sp, env->arch_env->sp); - arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]); - } - be_abi_reg_map_set(reg_map, env->arch_env->sp, curr_sp); - be_abi_reg_map_set(reg_map, env->arch_env->bp, curr_bp); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_LR], curr_lr); - be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_PC], curr_pc); -} - -static const be_abi_callbacks_t arm_abi_callbacks = { - arm_abi_init, - free, - arm_get_between_type, - arm_abi_prologue, - arm_abi_epilogue, -}; - - -/** - * Get the ABI restrictions for procedure calls. - * @param self The this pointer. - * @param method_type The type of the method (procedure) in question. - * @param abi The abi object to be modified - */ -void arm_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) -{ - ir_type *tp; - ir_mode *mode; - int i; - int n = get_method_n_params(method_type); - be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi); - (void) self; - - /* set abi flags for calls */ - call_flags.bits.left_to_right = 0; - call_flags.bits.store_args_sequential = 0; - /* call_flags.bits.try_omit_fp don't change this we can handle both */ - call_flags.bits.fp_free = 0; - call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */ - - /* set stack parameter passing style */ - be_abi_call_set_flags(abi, call_flags, &arm_abi_callbacks); - - for (i = 0; i < n; i++) { - /* reg = get reg for param i; */ - /* be_abi_call_param_reg(abi, i, reg); */ - if (i < 4) { - be_abi_call_param_reg(abi, i, arm_get_RegParam_reg(i)); - } else { - tp = get_method_param_type(method_type, i); - mode = get_type_mode(tp); - be_abi_call_param_stack(abi, i, mode, 4, 0, 0); - } - } - - /* set return registers */ - n = get_method_n_ress(method_type); - - assert(n <= 2 && "more than two results not supported"); - - /* In case of 64bit returns, we will have two 32bit values */ - if (n == 2) { - tp = get_method_res_type(method_type, 0); - mode = get_type_mode(tp); - - assert(!mode_is_float(mode) && "two FP results not supported"); - - tp = get_method_res_type(method_type, 1); - mode = get_type_mode(tp); - - assert(!mode_is_float(mode) && "mixed INT, FP results not supported"); - - be_abi_call_res_reg(abi, 0, &arm_gp_regs[REG_R0]); - be_abi_call_res_reg(abi, 1, &arm_gp_regs[REG_R1]); - } else if (n == 1) { - const arch_register_t *reg; - - tp = get_method_res_type(method_type, 0); - assert(is_atomic_type(tp)); - mode = get_type_mode(tp); - - reg = mode_is_float(mode) ? &arm_fpa_regs[REG_F0] : &arm_gp_regs[REG_R0]; - be_abi_call_res_reg(abi, 0, reg); - } -} - -int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) +static int arm_to_appear_in_schedule(void *block_env, const ir_node *irn) { (void) block_env; if (!is_arm_irn(irn)) @@ -1148,7 +745,6 @@ static lc_opt_enum_int_var_t arch_fpu_var = { static const lc_opt_table_entry_t arm_options[] = { LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var), - LC_OPT_ENT_BOOL("gen_reg_names", "use generic register names", &arm_isa_template.gen_reg_names), LC_OPT_LAST }; @@ -1159,7 +755,7 @@ const arch_isa_if_t arm_isa_if = { arm_get_n_reg_class, arm_get_reg_class, arm_get_reg_class_for_mode, - arm_get_call_abi, + NULL, arm_get_code_generator_if, arm_get_list_sched_selector, arm_get_ilp_sched_selector, @@ -1173,6 +769,7 @@ const arch_isa_if_t arm_isa_if = { arm_is_valid_clobber }; +BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm); void be_init_arch_arm(void) { lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be"); @@ -1185,5 +782,3 @@ void be_init_arch_arm(void) arm_init_transform(); arm_init_emitter(); } - -BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_arm);